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difftest
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difftest/vcs.mk

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Add MulanPSL-2.0 License (#824) In this commit, we add License for XiangShan project.
2021-06-04 09:06:35 +08:00
#***************************************************************************************
vcs: add target `simv-run` to run simv easily (#397)
2024-06-13 22:13:05 +08:00
# Copyright (c) 2024 Beijing Institute of Open Source Chip (BOSC)
# Copyright (c) 2020-2024 Institute of Computing Technology, Chinese Academy of Sciences
misc: update PCL information
2021-07-27 17:05:42 +08:00
# Copyright (c) 2020-2021 Peng Cheng Laboratory
Add MulanPSL-2.0 License (#824) In this commit, we add License for XiangShan project.
2021-06-04 09:06:35 +08:00
#
Update License comments (#134)
2023-09-06 16:40:04 +08:00
# DiffTest is licensed under Mulan PSL v2.
Add MulanPSL-2.0 License (#824) In this commit, we add License for XiangShan project.
2021-06-04 09:06:35 +08:00
# You can use this software according to the terms and conditions of the Mulan PSL v2.
# You may obtain a copy of Mulan PSL v2 at:
# http://license.coscl.org.cn/MulanPSL2
#
# THIS SOFTWARE IS PROVIDED ON AN "AS IS" BASIS, WITHOUT WARRANTIES OF ANY KIND,
# EITHER EXPRESS OR IMPLIED, INCLUDING BUT NOT LIMITED TO NON-INFRINGEMENT,
# MERCHANTABILITY OR FIT FOR A PARTICULAR PURPOSE.
#
# See the Mulan PSL v2 for more details.
#***************************************************************************************
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
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VCS = vcs
VCS_TOP = tb_top
VCS_TARGET = $(abspath $(BUILD_DIR)/simv)
VCS_BUILD_DIR = $(abspath $(BUILD_DIR)/simv-compile)
vcs: add target `simv-run` to run simv easily (#397)
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VCS_RUN_DIR = $(abspath $(BUILD_DIR)/$(notdir $(RUN_BIN)))
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
2021-05-07 09:34:59 +08:00
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
2023-09-21 19:23:25 +08:00
VCS_CSRC_DIR = $(abspath ./src/test/csrc/vcs)
VCS_CONFIG_DIR = $(abspath ./config)
VCS_CXXFILES = $(SIM_CXXFILES) $(shell find $(VCS_CSRC_DIR) -name "*.cpp")
VCS_CXXFLAGS = $(SIM_CXXFLAGS) -I$(VCS_CSRC_DIR) -DNUM_CORES=$(NUM_CORES)
VCS_LDFLAGS = $(SIM_LDFLAGS) -lpthread -ldl
# DiffTest support
vcs: add target `simv-run` to run simv easily (#397)
2024-06-13 22:13:05 +08:00
ifneq ($(NO_DIFF),1)
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
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VCS_FLAGS += +define+DIFFTEST
endif
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
2021-05-07 09:34:59 +08:00
difftest: add DIFFTEST macro This commit adds DIFFTEST macro to wrap difftest modules. Makefiles for verilator and vcs are updated as well.
2022-03-24 18:38:34 +08:00
ifeq ($(RELEASE),1)
VCS_FLAGS += +define+SNPS_FAST_SIM_FFV +define+USE_RF_DEBUG
endif
vcs: add support for --workload-list option (#293) Support --workload-list option for vcs simulation framework. By add running args like `--workload-list=<listfile_name>`，user can run several workload in a single launch on VCS or Palladium. This feature will greatly reduce time required to run many short workloads. Each line of list file should `workload-name max-instr-limit`. To support this feature, we add workload-switch logic. When a workload is done (or exceed max-instr-limit)，we will raise workload-switch signal according to simv_result. Then the reset signal will be set to high. Other logic will only rely on reset logic, so we can see each workload independently. Note: Now DUT memory has two implementation schemes: load memory to Hardware memory when initial, or load memory in software, then read/write by DPIC. Currently the first scheme cannot support reload memory when reset again. So we must ensure using DPIC memory. The whole progress of handling workload-list is like follows: 1. When initial, user pass workload-list. 2. When `reset` is set to high. User will trigger simv_init, it will get workload and max-instr from workload-list, just like only a workload is run. Software and DUT memory(DPIC) will be inited in this. 3. When `simv_nstep` is ended successfully. `workload-switch` will set `reset` to high. Software should be free by difftest_finish. Then Back to Point 2. 4. When `simv_init` gets no more workload from list. The whole simulation is ended.
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# core soft rst
ifeq ($(WORKLOAD_SWITCH),1)
VCS_FLAGS += +define+ENABLE_WORKLOAD_SWITCH
endif
ci: test simv simulation for SYNTHESIS and disable DPIC RAM/FLASH (#314)
2024-03-14 15:47:07 +08:00
ifeq ($(SYNTHESIS), 1)
VCS_FLAGS += +define+SYNTHESIS +define+TB_NO_DPIC
else
ifeq ($(DISABLE_DIFFTEST_RAM_DPIC), 1)
VCS_FLAGS += +define+DISABLE_DIFFTEST_RAM_DPIC
endif
ifeq ($(DISABLE_DIFFTEST_FLASH_DPIC), 1)
VCS_FLAGS += +define+DISABLE_DIFFTEST_FLASH_DPIC
endif
endif
vcs: could disable fsdb dump at compile stage usage: make simv CONSIDER_FSDB=0 Note: 1. $CONSIDER_FSDB is 1 at default. 2. Verdi is needed if wanna dump fsdb.
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# if fsdb is considered
vcs: set CONSIDER_FSDB default to none
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# CONSIDER_FSDB ?= 0
vcs: could disable fsdb dump at compile stage usage: make simv CONSIDER_FSDB=0 Note: 1. $CONSIDER_FSDB is 1 at default. 2. Verdi is needed if wanna dump fsdb.
2022-05-27 11:39:18 +08:00
ifeq ($(CONSIDER_FSDB),1)
EXTRA = +define+CONSIDER_FSDB
# if VERDI_HOME is not set automatically after 'module load', please set manually.
ifndef VERDI_HOME
$(error VERDI_HOME is not set. Try whereis verdi, abandon /bin/verdi and set VERID_HOME manually)
else
NOVAS_HOME = $(VERDI_HOME)
NOVAS = $(NOVAS_HOME)/share/PLI/VCS/LINUX64
EXTRA += -P $(NOVAS)/novas.tab $(NOVAS)/pli.a
endif
endif
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
2023-09-21 19:23:25 +08:00
ifeq ($(VCS),verilator)
Batch: pack DPIC to reduce sync times (#281) * Batch: pack DPIC to reduce sync times We pack DPIC of DifftestBundles on Hardware and unpack it in Software. So tens of DPIC called times will be reduced to one, which reduce sync times in platform such as palladium. It can speed up full-difftest of XiangShan from 0.23MHz to 0.29MHz with GlobalEnable,Squash and Gfifo(Non-block) in Palladium. Without Gfifo, it can speed up from 0.025 MHz to 0.11MHz. Difftest cycle delayed for DifftestBundles to collect valid bundles in bundleNum cycles, which cause delayed comparision result. BatchInterval and BatchFinish are appended to infoVec to seperate DPIC packed for different Cycle. Other elements contains BundleType and BundleLen to help unpack DataVec. Now we set maximum data byte packed as 3900, and maximum info byte packed as 90, because Palladium limits total bytes of gfifo param should less than 4000. We add --max-num-width verilator args to increase bit width limits. See related issue verilator/verilator#2082 For misalignment of struct member, we add packed attribute to struct declaration so all member will be aligned by byte, which helps use memcpy for DPIC. Note: When run full-difftest in XiangShan with Batch mode, it is possible to contains only one cycle DPICs each time for larger possible maximum bytes each cycle. So diffStateSelect should also be open for VCS and Palladium. We reshape GatewaySink for same control interface and different IO interface corresponding to DufftestBundle(single-pack) and batchIO(Batch). DPIC for different io interface should extend DPICBase for general methods.
2024-02-08 11:10:26 +08:00
VCS_FLAGS += --exe --cc --main --top-module $(VCS_TOP) -Wno-WIDTH --max-num-width 150000
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
2023-09-21 19:23:25 +08:00
VCS_FLAGS += --instr-count-dpi 1 --timing +define+VERILATOR_5
VCS_FLAGS += -Mdir $(VCS_BUILD_DIR) --compiler gcc
VCS_CXXFLAGS += -std=c++20
else
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
2021-05-07 09:34:59 +08:00
VCS_FLAGS += -full64 +v2k -timescale=1ns/1ns -sverilog -debug_access+all +lint=TFIPC-L
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
2023-09-21 19:23:25 +08:00
VCS_FLAGS += -Mdir=$(VCS_BUILD_DIR) -j200
vcs: implement optional xprop examination (#398)
2024-06-13 22:13:35 +08:00
VCS_FLAGS += +define+VCS
ifeq ($(ENABLE_XPROP),1)
VCS_FLAGS += -xprop
else
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
2021-05-07 09:34:59 +08:00
# randomize all undefined signals (instead of using X)
vcs: implement optional xprop examination (#398)
2024-06-13 22:13:35 +08:00
VCS_FLAGS += +vcs+initreg+random
endif
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
2023-09-21 19:23:25 +08:00
VCS_CXXFLAGS += -std=c++11 -static
endif
VCS_FLAGS += -o $(VCS_TARGET)
vcs: implement optional xprop examination (#398)
2024-06-13 22:13:35 +08:00
ifneq ($(ENABLE_XPROP),1)
vcs: fix incorrect random initialization (X) (#81) Set RANDOMIZE_DELAY to 0 will cause some random initialized reg be initialized to X. RANDOMIZE_DELAY should satisfy: * round(RANDOMIZE_DELAY) > 0 * RANDOMIZE_DELAY < reset delay See https://github.com/chipsalliance/firrtl/pull/835
2022-06-04 16:47:05 +08:00
VCS_FLAGS += +define+RANDOMIZE_GARBAGE_ASSIGN
VCS_FLAGS += +define+RANDOMIZE_INVALID_ASSIGN
VCS_FLAGS += +define+RANDOMIZE_MEM_INIT
VCS_FLAGS += +define+RANDOMIZE_REG_INIT
vcs: implement optional xprop examination (#398)
2024-06-13 22:13:35 +08:00
endif
vcs: fix incorrect random initialization (X) (#81) Set RANDOMIZE_DELAY to 0 will cause some random initialized reg be initialized to X. RANDOMIZE_DELAY should satisfy: * round(RANDOMIZE_DELAY) > 0 * RANDOMIZE_DELAY < reset delay See https://github.com/chipsalliance/firrtl/pull/835
2022-06-04 16:47:05 +08:00
# manually set RANDOMIZE_DELAY to avoid VCS from incorrect random initialize
# NOTE: RANDOMIZE_DELAY must NOT be rounded to 0
VCS_FLAGS += +define+RANDOMIZE_DELAY=1
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
2021-05-07 09:34:59 +08:00
# SRAM lib defines
difftest: add DIFFTEST macro This commit adds DIFFTEST macro to wrap difftest modules. Makefiles for verilator and vcs are updated as well.
2022-03-24 18:38:34 +08:00
VCS_FLAGS += +define+UNIT_DELAY +define+no_warning
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
2021-05-07 09:34:59 +08:00
# C++ flags
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
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VCS_FLAGS += -CFLAGS "$(VCS_CXXFLAGS)" -LDFLAGS "$(VCS_LDFLAGS)"
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
2021-05-07 09:34:59 +08:00
# search build for other missing verilog files
vcs: enable search for missing sv files (#285)
2024-02-07 10:25:17 +08:00
VCS_FLAGS += -y $(RTL_DIR) +libext+.v +libext+.sv
vcs: fix including generated vsrc (#282) In vcs, -y only used for missing modules, +incdir is used for file include. And +incdir is also support by verilator
2024-02-04 10:14:55 +08:00
# search generated-src for verilog included files
VCS_FLAGS += +incdir+$(GEN_VSRC_DIR)
vcs: enrich param dump-wave=[vpd,fsdb]
2022-05-19 19:04:57 +08:00
# enable fsdb dump
vcs: could disable fsdb dump at compile stage usage: make simv CONSIDER_FSDB=0 Note: 1. $CONSIDER_FSDB is 1 at default. 2. Verdi is needed if wanna dump fsdb.
2022-05-27 11:39:18 +08:00
VCS_FLAGS += $(EXTRA)
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
2021-05-07 09:34:59 +08:00
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
2023-09-21 19:23:25 +08:00
VCS_VSRC_DIR = $(abspath ./src/test/vsrc/vcs)
VCS_VFILES = $(SIM_VSRC) $(shell find $(VCS_VSRC_DIR) -name "*.v")
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
2021-05-07 09:34:59 +08:00
$(VCS_TARGET): $(SIM_TOP_V) $(VCS_CXXFILES) $(VCS_VFILES)
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
2023-09-21 19:23:25 +08:00
$(VCS) $(VCS_FLAGS) $(SIM_TOP_V) $(VCS_CXXFILES) $(VCS_VFILES)
ifeq ($(VCS),verilator)
CI: switch to ubuntu-22.04 runners (#252)
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$(MAKE) -s -C $(VCS_BUILD_DIR) -f V$(VCS_TOP).mk
Fix the VCS simulation flow and scripts (#172) * add `VCS` macro to indicate VCS * add a CI test case for using Verilator to simulate VCS top
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endif
simv: $(VCS_TARGET)
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
2021-05-07 09:34:59 +08:00
vcs: add target `simv-run` to run simv easily (#397)
2024-06-13 22:13:05 +08:00
RUN_OPTS := +workload=$(RUN_BIN)
ifeq ($(TRACE),1)
ifeq ($(CONSIDER_FSDB),1)
RUN_OPTS += +dump-wave=fsdb
else
RUN_OPTS += +dump-wave=vpd
endif
endif
ifneq ($(REF_SO),)
RUN_OPTS += +diff=$(REF_SO)
endif
ifeq ($(NO_DIFF),1)
RUN_OPTS += +no-diff
endif
RUN_OPTS += -assert finish_maxfail=30 -assert global_finish_maxfail=10000
simv-run:
$(shell if [ ! -e $(VCS_RUN_DIR) ]; then mkdir -p $(VCS_RUN_DIR); fi)
touch $(VCS_RUN_DIR)/sim.log
$(shell if [ -e $(VCS_RUN_DIR)/simv ]; then rm -f $(VCS_RUN_DIR)/simv; fi)
$(shell if [ -e $(VCS_RUN_DIR)/simv.daidir ]; then rm -rf $(VCS_RUN_DIR)/simv.daidir; fi)
ln -s $(VCS_TARGET) $(VCS_RUN_DIR)/simv
ln -s $(BUILD_DIR)/simv.daidir $(VCS_RUN_DIR)/simv.daidir
cd $(VCS_RUN_DIR) && (./simv $(RUN_OPTS) 2> assert.log | tee sim.log)
test: add support for VCS simulation (#803) This commit adds support for using Synopsys VCS to simulate SimTop. Difftest is also supported. For now, we use src/test/vsrc/vcs/top.v as the top-level module. In the future, we may support VCS slave mode for better scalability.
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vcs-clean:
rm -rf simv csrc DVEfiles simv.daidir stack.info.* ucli.key $(VCS_BUILD_DIR)