Go to file
Hazard 9e56439d0b
top: add real-time clock for CLINT (#1553)
2022-05-12 20:03:45 +08:00
.github/workflows Fix vcs simulation support, support manually set ram_size (#1551) 2022-05-11 19:55:01 +08:00
debug Integer SRT16 Divider (#1019) 2021-09-23 14:17:39 +08:00
difftest@9b17ca076a Fix vcs simulation support, support manually set ram_size (#1551) 2022-05-11 19:55:01 +08:00
fudian@3dd05b0881 Bump rocket-chip (#1502) 2022-03-26 09:32:13 +08:00
huancun@f2da3bef29 Fix vcs simulation support, support manually set ram_size (#1551) 2022-05-11 19:55:01 +08:00
images misc: fix typo in nanhu arch figure (#1552) 2022-05-11 17:12:52 +08:00
project update sbt version 2019-03-03 16:54:26 +08:00
ready-to-run@ec61625c16 Fix vcs simulation support, support manually set ram_size (#1551) 2022-05-11 19:55:01 +08:00
rocket-chip@85f319c62f Bump rocket-chip (#1502) 2022-03-26 09:32:13 +08:00
scripts Fix vcs simulation support, support manually set ram_size (#1551) 2022-05-11 19:55:01 +08:00
src top: add real-time clock for CLINT (#1553) 2022-05-12 20:03:45 +08:00
tools/readmemh misc: update PCL information (#899) 2021-07-24 23:26:38 +08:00
.gitignore feat: parameterize load store (#1527) 2022-05-06 23:01:31 +08:00
.gitmodules Clean up project dependencies (#1282) 2021-12-01 08:52:47 +08:00
.mill-version build.sc: remove `testOnly` (#843) 2021-06-26 16:26:01 +08:00
LICENSE Add MulanPSL-2.0 License (#824) 2021-06-04 09:06:35 +08:00
Makefile fix some typos (#1537) 2022-04-25 12:47:48 +08:00
README.md readme: update new information and sync zh/en version (#1494) 2022-03-22 16:51:14 +08:00
build.sbt Add sbt build support (#857) 2021-07-03 09:34:31 +08:00
build.sc Misc: add support for compiling with CIRCT 2022-03-31 14:03:00 +08:00
readme.zh-cn.md readme: update new information and sync zh/en version (#1494) 2022-03-22 16:51:14 +08:00
scalastyle-config.xml first commit 2019-02-06 11:06:33 +08:00
scalastyle-test-config.xml first commit 2019-02-06 11:06:33 +08:00

README.md

XiangShan

XiangShan (香山) is an open-source high-performance RISC-V processor project.

中文说明在此

Copyright 2020-2022 by Institute of Computing Technology, Chinese Academy of Sciences.

Copyright 2020-2022 by Peng Cheng Laboratory.

Docs and slides

XiangShan-doc is our official documentation repository. It contains design spec., technical slides, tutorial and more.

Follow us

Wechat/微信:香山开源处理器

Zhihu/知乎:香山开源处理器

Weibo/微博:香山开源处理器

You can contact us through our mail list. All mails from this list will be archived to here.

Architecture

The first stable micro-architecture of XiangShan is called Yanqihu (雁栖湖) on this branch, which has been developed since June 2020. The current version of XiangShan, also known as Nanhu (南湖), is still under development on the master branch.

The micro-architecture overview of Nanhu (南湖) is shown below.

xs-arch-nanhu

Sub-directories Overview

Some of the key directories are shown below.

.
├── src
│   └── main/scala         # design files
│       ├── device         # virtual device for simulation
│       ├── system         # SoC wrapper
│       ├── top            # top module
│       ├── utils          # utilization code
│       ├── xiangshan      # main design code
│       └── xstransforms   # some useful firrtl transforms
├── scripts                # scripts for agile development
├── fudian                 # floating unit submodule of XiangShan
├── huancun                # L2/L3 cache submodule of XiangShan
├── difftest               # difftest co-simulation framework
└── ready-to-run           # pre-built simulation images

IDE Support

bsp

make bsp

IDEA

make idea

Generate Verilog

  • Run make verilog to generate verilog code. The output file is build/XSTop.v.
  • Refer to Makefile for more information.

Run Programs by Simulation

Prepare environment

  • Set environment variable NEMU_HOME to the absolute path of the NEMU project.
  • Set environment variable NOOP_HOME to the absolute path of the XiangShan project.
  • Set environment variable AM_HOME to the absolute path of the AM project.
  • Install mill. Refer to the Manual section in this guide.
  • Clone this project and run make init to initialize submodules.

Run with simulator

  • Install Verilator, the open-source Verilog simulator.
  • Run make emu to build the C++ simulator ./build/emu with Verilator.
  • Refer to ./build/emu --help for run-time arguments of the simulator.
  • Refer to Makefile and verilator.mk for more information.

Example:

make emu CONFIG=MinimalConfig EMU_THREADS=2 -j10
./build/emu -b 0 -e 0 -i ./ready-to-run/coremark-2-iteration.bin --diff ./ready-to-run/riscv64-nemu-interpreter-so

Troubleshooting Guide

Troubleshooting Guide

Acknowledgement

In the development of XiangShan, some sub-modules from the open-source community are employed. All relevant usage is listed below.

Sub-module Source Detail
L2 Cache/LLC Sifive block-inclusivecache Our new L2/L3 design are inspired by Sifive's block-inclusivecache.
Diplomacy/TileLink Rocket-chip We reused the Diplomacy framework and TileLink utility that exist in rocket-chip to negotiate bus.

We are grateful for the support of the open-source community and encourage other open-source projects to reuse our code within the scope of the license.