OpenXiangShan
/
XS-Verilog-Library
mirror of https://github.com/OpenXiangShan/XS-Verilog-Library.git
3
0
Fork 0
Code Issues Projects Releases Wiki Activity
XS-Verilog-Library/int_div_radix_4_v1
History
HYF 7cfa3d6622
upload R16 SRT divider, overlapped by 4 R2 SRT (#5) 
* upload R16 SRT divider, overlapped by 4 R2 SRT

* 1. Improve timing of "pre_cmp_res" in int_div_radix_4_v1/int_div_radix_4_v1.sv

2. Upload R16 SRT Divider, overlapped by 2 R4 SRT blocks.

* Improve the timing of "lzc_diff".
 		2021-10-09 10:50:27 +08:00
..
doc Update readme.md 2021-07-22 20:51:16 +08:00
rtl upload R16 SRT divider, overlapped by 4 R2 SRT (#5) 2021-10-09 10:50:27 +08:00
sim upload R16 SRT divider, overlapped by 4 R2 SRT (#5) 2021-10-09 10:50:27 +08:00
tb 1. 改进激励，现在绝大部分激励都需要至少迭代一次，提高发现错误概率。 2021-08-11 17:35:56 +08:00
README.md 添加改进版Radix-4 SRT整数除法器 (#2) 2021-07-22 20:50:48 +08:00

README.md

相比于标准的R4 SRT算法，使用了Retiming结构设计，理论上PPA会好。 支持64/32/16-bit的unsigned/signed整数除法计算，并且支持计算余数。