Add Radix-8 Restoring integer divider.
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hyf_sysu
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# References
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[1] https://digitalsystemdesign.in/signed-array-divider/
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// ========================================================================================================
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// File Name : int64_div_cla3.sv
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// Author : Yifei He
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// How to Contact : hyf_sysu@qq.com
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// Created Time : 2021-10-29 10:21:29
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// Last Modified Time : 2021-11-01 15:50:36
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// ========================================================================================================
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// Description :
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// Radix-8 restoring interger division algorithm.
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// This algorithm is suitable for multicycle implementation.
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// This module could do 16/32/64-bit signed/unsigned integer division.
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// ========================================================================================================
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// ========================================================================================================
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// Copyright (C) 2021, HYF. All Rights Reserved.
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// ========================================================================================================
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// This file is licensed under BSD 3-Clause License.
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// Redistribution and use in source and binary forms, with or without
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// modification, are permitted provided that the following conditions are met:
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// Redistribution and use in source and binary forms, with or without modification,
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// are permitted provided that the following conditions are met:
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//
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// 1. Redistributions of source code must retain the above copyright notice, this list of
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// conditions and the following disclaimer.
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//
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// 2. Redistributions in binary form must reproduce the above copyright notice, this list of
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// conditions and the following disclaimer in the documentation and/or other materials provided
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// with the distribution.
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//
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// 3. Neither the name of the copyright holder nor the names of its contributors may be used
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// to endorse or promote products derived from this software without specific prior written permission.
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//
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// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
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// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
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// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
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// THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
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// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
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// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
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// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
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// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
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// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
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// ========================================================================================================
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// include your definitions here
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module int64_div_cla3 #(
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// Put your parameters here, which can be changed by other modules.
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)(
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// 00: int16
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// 01: int32
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// 10: int64
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input logic [1:0] op_format_i,
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input logic op_sign_i,
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input logic [64-1:0] dividend_i,
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input logic [64-1:0] divisor_i,
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output logic [64-1:0] quotient_o,
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output logic [64-1:0] remainder_o,
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output logic divisor_is_zero_o
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);
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// ==================================================================================================================================================
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// (local) params
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// ==================================================================================================================================================
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// ==================================================================================================================================================
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// functions
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// ==================================================================================================================================================
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// ==================================================================================================================================================
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// signals
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// ==================================================================================================================================================
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genvar i;
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logic int16_en;
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logic int32_en;
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logic int64_en;
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logic dividend_sign;
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logic divisor_sign;
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logic quo_sign;
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logic rem_sign;
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logic [64-1:0] dividend_abs;
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logic [64-1:0] negated_dividend;
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logic [64-1:0] dividend_adjusted;
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logic [64-1:0] divisor_adjusted;
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logic [64-1:0] D;
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logic [(64 + 2)-1:0] D_times_3;
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logic [(64 + 3)-1:0] D_times_5;
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logic [(64 + 3)-1:0] D_times_7;
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logic [64-1:0] rem [64-1:0];
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logic [64-1:0] rem_prev_q_0 [64-1:0];
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logic [64-1:0] rem_prev_q_1 [64-1:0];
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logic [64-1:0] rem_prev_q_00 [64-1:0];
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logic [64-1:0] rem_prev_q_01 [64-1:0];
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logic [64-1:0] rem_prev_q_10 [64-1:0];
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logic [64-1:0] rem_prev_q_11 [64-1:0];
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logic rem_cout [64-1:0];
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logic rem_cout_prev_q_0 [64-1:0];
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logic rem_cout_prev_q_1 [64-1:0];
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logic rem_cout_prev_q_00 [64-1:0];
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logic rem_cout_prev_q_01 [64-1:0];
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logic rem_cout_prev_q_10 [64-1:0];
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logic rem_cout_prev_q_11 [64-1:0];
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logic [64-1:0] rem_sum [64-1:0];
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logic [64-1:0] rem_sum_prev_q_0 [64-1:0];
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logic [64-1:0] rem_sum_prev_q_1 [64-1:0];
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logic [64-1:0] rem_sum_prev_q_00 [64-1:0];
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logic [64-1:0] rem_sum_prev_q_01 [64-1:0];
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logic [64-1:0] rem_sum_prev_q_10 [64-1:0];
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logic [64-1:0] rem_sum_prev_q_11 [64-1:0];
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logic [64-1:0] quo_iter;
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logic q_prev_q_0 [64-1:0];
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logic q_prev_q_1 [64-1:0];
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logic q_prev_q_00 [64-1:0];
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logic q_prev_q_01 [64-1:0];
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logic q_prev_q_10 [64-1:0];
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logic q_prev_q_11 [64-1:0];
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logic force_q_to_zero [64-1:0];
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logic force_q_to_zero_prev_q_0 [64-1:0];
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logic force_q_to_zero_prev_q_1 [64-1:0];
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logic force_q_to_zero_prev_q_00 [64-1:0];
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logic force_q_to_zero_prev_q_01 [64-1:0];
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logic force_q_to_zero_prev_q_10 [64-1:0];
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logic force_q_to_zero_prev_q_11 [64-1:0];
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logic D_msb_to_lsb_flag [64-1:0];
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logic D_lsb_to_msb_flag [64-1:0];
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logic D_times_3_msb_to_lsb_flag [64-1:0];
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logic D_times_3_lsb_to_msb_flag [64-1:0];
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logic D_times_5_msb_to_lsb_flag [64-1:0];
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logic D_times_5_lsb_to_msb_flag [64-1:0];
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logic D_times_7_msb_to_lsb_flag [64-1:0];
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logic D_times_7_lsb_to_msb_flag [64-1:0];
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logic [64-1:0] final_rem;
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logic [64-1:0] final_quo;
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logic [64-1:0] final_quo_pre;
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// ==================================================================================================================================================
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// main codes
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// ==================================================================================================================================================
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assign int16_en = (op_format_i == 2'b00);
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assign int32_en = (op_format_i == 2'b01);
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assign int64_en = (op_format_i == 2'b10);
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assign dividend_sign = op_sign_i & (int16_en ? dividend_i[15] : int32_en ? dividend_i[31] : dividend_i[63]);
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assign divisor_sign = op_sign_i & (int16_en ? divisor_i[15] : int32_en ? divisor_i[31] : divisor_i[63]);
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assign quo_sign = dividend_sign ^ divisor_sign;
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assign rem_sign = dividend_sign;
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assign dividend_adjusted = int32_en ? {{(32){dividend_sign}}, dividend_i[31:0]} : int16_en ? {{(48){dividend_sign}}, dividend_i[15:0]} : dividend_i[63:0];
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assign divisor_adjusted = int32_en ? {{(32){divisor_sign}}, divisor_i[31:0]} : int16_en ? {{(48){divisor_sign}}, divisor_i[15:0]} : divisor_i[63:0];
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assign negated_dividend = -dividend_adjusted;
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assign dividend_abs = dividend_sign ? negated_dividend : dividend_adjusted;
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assign D = divisor_adjusted;
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// Sign-ext and add
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assign D_times_3[(64 + 2)-1:0] = {D[63], D[63], D} + {D[63], D, 1'b0};
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assign D_times_5[(64 + 3)-1:0] = {D[63], D[63], D[63], D} + {D[63], D, 2'b0};
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assign D_times_7[(64 + 3)-1:0] = {D[63], D[63], D[63], D} + {D[63], D, 2'b0} + {D[63], D[63], D, 1'b0};
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// When "D < 0, and D is the power of 2", we need to make sure that we detect the index of the leading "1" in its abs value (leading one index, loi) correctly.
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// For simplicity, let's assume D is a 8-bit signed integer:
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// Ex0.
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// D = 1101_0000, abs(D) = 0011_0000
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// &(D[7:6]) = 1, loi = 5 -> This is correct.
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// Ex1.
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// D = 1001_1101, abs(D) = 0110_0011
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// &(D[7:7]) = 1, loi = 6 -> This is correct.
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// Ex2.
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// D = 1111_0100, abs(D) = 0000_1100
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// &(D[7:4]) = 1, loi = 3 -> This is correct.
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// Ex3.
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// D = 1111_0000, abs(D) = 0001_0000
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// &(D[7:4]) = 1, loi = 3 -> This is wrong !!!
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// So, we need to use "D_lsb_to_msb_flag" to get the correct "loi".
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// D = 1111_0000, abs(D) = 0001_0000
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// &(D[7:4]) = 1, |(D[3:0]) = 0 -> loi is not 3.
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// &(D[7:5]) = 1, |(D[4:0]) = 1 -> loi is 4, correct !!!
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// The same logic will be used in "D_times_3".
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// When D is negative, D[64] must be 1, so we don't need to include it.
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assign D_msb_to_lsb_flag[ 0] = ~divisor_sign ? |(D[63: 1]) : ~(&(D[62: 1]));
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assign D_msb_to_lsb_flag[ 1] = ~divisor_sign ? |(D[63: 2]) : ~(&(D[62: 2]));
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assign D_msb_to_lsb_flag[ 2] = ~divisor_sign ? |(D[63: 3]) : ~(&(D[62: 3]));
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assign D_msb_to_lsb_flag[ 3] = ~divisor_sign ? |(D[63: 4]) : ~(&(D[62: 4]));
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assign D_msb_to_lsb_flag[ 4] = ~divisor_sign ? |(D[63: 5]) : ~(&(D[62: 5]));
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assign D_msb_to_lsb_flag[ 5] = ~divisor_sign ? |(D[63: 6]) : ~(&(D[62: 6]));
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assign D_msb_to_lsb_flag[ 6] = ~divisor_sign ? |(D[63: 7]) : ~(&(D[62: 7]));
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assign D_msb_to_lsb_flag[ 7] = ~divisor_sign ? |(D[63: 8]) : ~(&(D[62: 8]));
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assign D_msb_to_lsb_flag[ 8] = ~divisor_sign ? |(D[63: 9]) : ~(&(D[62: 9]));
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assign D_msb_to_lsb_flag[ 9] = ~divisor_sign ? |(D[63:10]) : ~(&(D[62:10]));
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assign D_msb_to_lsb_flag[10] = ~divisor_sign ? |(D[63:11]) : ~(&(D[62:11]));
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assign D_msb_to_lsb_flag[11] = ~divisor_sign ? |(D[63:12]) : ~(&(D[62:12]));
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assign D_msb_to_lsb_flag[12] = ~divisor_sign ? |(D[63:13]) : ~(&(D[62:13]));
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assign D_msb_to_lsb_flag[13] = ~divisor_sign ? |(D[63:14]) : ~(&(D[62:14]));
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assign D_msb_to_lsb_flag[14] = ~divisor_sign ? |(D[63:15]) : ~(&(D[62:15]));
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assign D_msb_to_lsb_flag[15] = ~divisor_sign ? |(D[63:16]) : ~(&(D[62:16]));
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assign D_msb_to_lsb_flag[16] = ~divisor_sign ? |(D[63:17]) : ~(&(D[62:17]));
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assign D_msb_to_lsb_flag[17] = ~divisor_sign ? |(D[63:18]) : ~(&(D[62:18]));
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assign D_msb_to_lsb_flag[18] = ~divisor_sign ? |(D[63:19]) : ~(&(D[62:19]));
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assign D_msb_to_lsb_flag[19] = ~divisor_sign ? |(D[63:20]) : ~(&(D[62:20]));
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assign D_msb_to_lsb_flag[20] = ~divisor_sign ? |(D[63:21]) : ~(&(D[62:21]));
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assign D_msb_to_lsb_flag[21] = ~divisor_sign ? |(D[63:22]) : ~(&(D[62:22]));
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assign D_msb_to_lsb_flag[22] = ~divisor_sign ? |(D[63:23]) : ~(&(D[62:23]));
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assign D_msb_to_lsb_flag[23] = ~divisor_sign ? |(D[63:24]) : ~(&(D[62:24]));
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assign D_msb_to_lsb_flag[24] = ~divisor_sign ? |(D[63:25]) : ~(&(D[62:25]));
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assign D_msb_to_lsb_flag[25] = ~divisor_sign ? |(D[63:26]) : ~(&(D[62:26]));
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assign D_msb_to_lsb_flag[26] = ~divisor_sign ? |(D[63:27]) : ~(&(D[62:27]));
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assign D_msb_to_lsb_flag[27] = ~divisor_sign ? |(D[63:28]) : ~(&(D[62:28]));
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assign D_msb_to_lsb_flag[28] = ~divisor_sign ? |(D[63:29]) : ~(&(D[62:29]));
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assign D_msb_to_lsb_flag[29] = ~divisor_sign ? |(D[63:30]) : ~(&(D[62:30]));
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assign D_msb_to_lsb_flag[30] = ~divisor_sign ? |(D[63:31]) : ~(&(D[62:31]));
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assign D_msb_to_lsb_flag[31] = ~divisor_sign ? |(D[63:32]) : ~(&(D[62:32]));
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assign D_msb_to_lsb_flag[32] = ~divisor_sign ? |(D[63:33]) : ~(&(D[62:33]));
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assign D_msb_to_lsb_flag[33] = ~divisor_sign ? |(D[63:34]) : ~(&(D[62:34]));
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assign D_msb_to_lsb_flag[34] = ~divisor_sign ? |(D[63:35]) : ~(&(D[62:35]));
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assign D_msb_to_lsb_flag[35] = ~divisor_sign ? |(D[63:36]) : ~(&(D[62:36]));
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assign D_msb_to_lsb_flag[36] = ~divisor_sign ? |(D[63:37]) : ~(&(D[62:37]));
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assign D_msb_to_lsb_flag[37] = ~divisor_sign ? |(D[63:38]) : ~(&(D[62:38]));
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assign D_msb_to_lsb_flag[38] = ~divisor_sign ? |(D[63:39]) : ~(&(D[62:39]));
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assign D_msb_to_lsb_flag[39] = ~divisor_sign ? |(D[63:40]) : ~(&(D[62:40]));
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assign D_msb_to_lsb_flag[40] = ~divisor_sign ? |(D[63:41]) : ~(&(D[62:41]));
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assign D_msb_to_lsb_flag[41] = ~divisor_sign ? |(D[63:42]) : ~(&(D[62:42]));
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assign D_msb_to_lsb_flag[42] = ~divisor_sign ? |(D[63:43]) : ~(&(D[62:43]));
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assign D_msb_to_lsb_flag[43] = ~divisor_sign ? |(D[63:44]) : ~(&(D[62:44]));
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assign D_msb_to_lsb_flag[44] = ~divisor_sign ? |(D[63:45]) : ~(&(D[62:45]));
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assign D_msb_to_lsb_flag[45] = ~divisor_sign ? |(D[63:46]) : ~(&(D[62:46]));
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assign D_msb_to_lsb_flag[46] = ~divisor_sign ? |(D[63:47]) : ~(&(D[62:47]));
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assign D_msb_to_lsb_flag[47] = ~divisor_sign ? |(D[63:48]) : ~(&(D[62:48]));
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assign D_msb_to_lsb_flag[48] = ~divisor_sign ? |(D[63:49]) : ~(&(D[62:49]));
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assign D_msb_to_lsb_flag[49] = ~divisor_sign ? |(D[63:50]) : ~(&(D[62:50]));
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assign D_msb_to_lsb_flag[50] = ~divisor_sign ? |(D[63:51]) : ~(&(D[62:51]));
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assign D_msb_to_lsb_flag[51] = ~divisor_sign ? |(D[63:52]) : ~(&(D[62:52]));
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assign D_msb_to_lsb_flag[52] = ~divisor_sign ? |(D[63:53]) : ~(&(D[62:53]));
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assign D_msb_to_lsb_flag[53] = ~divisor_sign ? |(D[63:54]) : ~(&(D[62:54]));
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assign D_msb_to_lsb_flag[54] = ~divisor_sign ? |(D[63:55]) : ~(&(D[62:55]));
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assign D_msb_to_lsb_flag[55] = ~divisor_sign ? |(D[63:56]) : ~(&(D[62:56]));
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assign D_msb_to_lsb_flag[56] = ~divisor_sign ? |(D[63:57]) : ~(&(D[62:57]));
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assign D_msb_to_lsb_flag[57] = ~divisor_sign ? |(D[63:58]) : ~(&(D[62:58]));
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assign D_msb_to_lsb_flag[58] = ~divisor_sign ? |(D[63:59]) : ~(&(D[62:59]));
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assign D_msb_to_lsb_flag[59] = ~divisor_sign ? |(D[63:60]) : ~(&(D[62:60]));
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assign D_msb_to_lsb_flag[60] = ~divisor_sign ? |(D[63:61]) : ~(&(D[62:61]));
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assign D_msb_to_lsb_flag[61] = ~divisor_sign ? |(D[63:62]) : ~(&(D[62:62]));
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assign D_msb_to_lsb_flag[62] = ~divisor_sign ? |(D[63:63]) : 1'b0;
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assign D_msb_to_lsb_flag[63] = 1'b0;
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// This flag is only useful when D < 0
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assign D_lsb_to_msb_flag[ 0] = divisor_sign ? ~(|(D[ 0:0])) : 1'b0;
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assign D_lsb_to_msb_flag[ 1] = divisor_sign ? ~(|(D[ 1:0])) : 1'b0;
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assign D_lsb_to_msb_flag[ 2] = divisor_sign ? ~(|(D[ 2:0])) : 1'b0;
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assign D_lsb_to_msb_flag[ 3] = divisor_sign ? ~(|(D[ 3:0])) : 1'b0;
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assign D_lsb_to_msb_flag[ 4] = divisor_sign ? ~(|(D[ 4:0])) : 1'b0;
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assign D_lsb_to_msb_flag[ 5] = divisor_sign ? ~(|(D[ 5:0])) : 1'b0;
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assign D_lsb_to_msb_flag[ 6] = divisor_sign ? ~(|(D[ 6:0])) : 1'b0;
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assign D_lsb_to_msb_flag[ 7] = divisor_sign ? ~(|(D[ 7:0])) : 1'b0;
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assign D_lsb_to_msb_flag[ 8] = divisor_sign ? ~(|(D[ 8:0])) : 1'b0;
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assign D_lsb_to_msb_flag[ 9] = divisor_sign ? ~(|(D[ 9:0])) : 1'b0;
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assign D_lsb_to_msb_flag[10] = divisor_sign ? ~(|(D[10:0])) : 1'b0;
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assign D_lsb_to_msb_flag[11] = divisor_sign ? ~(|(D[11:0])) : 1'b0;
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assign D_lsb_to_msb_flag[12] = divisor_sign ? ~(|(D[12:0])) : 1'b0;
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assign D_lsb_to_msb_flag[13] = divisor_sign ? ~(|(D[13:0])) : 1'b0;
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assign D_lsb_to_msb_flag[14] = divisor_sign ? ~(|(D[14:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[15] = divisor_sign ? ~(|(D[15:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[16] = divisor_sign ? ~(|(D[16:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[17] = divisor_sign ? ~(|(D[17:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[18] = divisor_sign ? ~(|(D[18:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[19] = divisor_sign ? ~(|(D[19:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[20] = divisor_sign ? ~(|(D[20:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[21] = divisor_sign ? ~(|(D[21:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[22] = divisor_sign ? ~(|(D[22:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[23] = divisor_sign ? ~(|(D[23:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[24] = divisor_sign ? ~(|(D[24:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[25] = divisor_sign ? ~(|(D[25:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[26] = divisor_sign ? ~(|(D[26:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[27] = divisor_sign ? ~(|(D[27:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[28] = divisor_sign ? ~(|(D[28:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[29] = divisor_sign ? ~(|(D[29:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[30] = divisor_sign ? ~(|(D[30:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[31] = divisor_sign ? ~(|(D[31:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[32] = divisor_sign ? ~(|(D[32:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[33] = divisor_sign ? ~(|(D[33:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[34] = divisor_sign ? ~(|(D[34:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[35] = divisor_sign ? ~(|(D[35:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[36] = divisor_sign ? ~(|(D[36:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[37] = divisor_sign ? ~(|(D[37:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[38] = divisor_sign ? ~(|(D[38:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[39] = divisor_sign ? ~(|(D[39:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[40] = divisor_sign ? ~(|(D[40:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[41] = divisor_sign ? ~(|(D[41:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[42] = divisor_sign ? ~(|(D[42:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[43] = divisor_sign ? ~(|(D[43:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[44] = divisor_sign ? ~(|(D[44:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[45] = divisor_sign ? ~(|(D[45:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[46] = divisor_sign ? ~(|(D[46:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[47] = divisor_sign ? ~(|(D[47:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[48] = divisor_sign ? ~(|(D[48:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[49] = divisor_sign ? ~(|(D[49:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[50] = divisor_sign ? ~(|(D[50:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[51] = divisor_sign ? ~(|(D[51:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[52] = divisor_sign ? ~(|(D[52:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[53] = divisor_sign ? ~(|(D[53:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[54] = divisor_sign ? ~(|(D[54:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[55] = divisor_sign ? ~(|(D[55:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[56] = divisor_sign ? ~(|(D[56:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[57] = divisor_sign ? ~(|(D[57:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[58] = divisor_sign ? ~(|(D[58:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[59] = divisor_sign ? ~(|(D[59:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[60] = divisor_sign ? ~(|(D[60:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[61] = divisor_sign ? ~(|(D[61:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[62] = divisor_sign ? ~(|(D[62:0])) : 1'b0;
|
||||
assign D_lsb_to_msb_flag[63] = 1'b0;
|
||||
|
||||
// Only useful in stage[1, 2, 4, 5, 7, 8, ..., 61, 62]
|
||||
assign D_times_3_msb_to_lsb_flag[ 0] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[ 1] = ~divisor_sign ? |(D_times_3[65: 2]) : ~(&(D_times_3[64: 2]));
|
||||
assign D_times_3_msb_to_lsb_flag[ 2] = ~divisor_sign ? |(D_times_3[65: 3]) : ~(&(D_times_3[64: 3]));
|
||||
assign D_times_3_msb_to_lsb_flag[ 3] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[ 4] = ~divisor_sign ? |(D_times_3[65: 5]) : ~(&(D_times_3[64: 5]));
|
||||
assign D_times_3_msb_to_lsb_flag[ 5] = ~divisor_sign ? |(D_times_3[65: 6]) : ~(&(D_times_3[64: 6]));
|
||||
assign D_times_3_msb_to_lsb_flag[ 6] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[ 7] = ~divisor_sign ? |(D_times_3[65: 8]) : ~(&(D_times_3[64: 8]));
|
||||
assign D_times_3_msb_to_lsb_flag[ 8] = ~divisor_sign ? |(D_times_3[65: 9]) : ~(&(D_times_3[64: 9]));
|
||||
assign D_times_3_msb_to_lsb_flag[ 9] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[10] = ~divisor_sign ? |(D_times_3[65:11]) : ~(&(D_times_3[64:11]));
|
||||
assign D_times_3_msb_to_lsb_flag[11] = ~divisor_sign ? |(D_times_3[65:12]) : ~(&(D_times_3[64:12]));
|
||||
assign D_times_3_msb_to_lsb_flag[12] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[13] = ~divisor_sign ? |(D_times_3[65:14]) : ~(&(D_times_3[64:14]));
|
||||
assign D_times_3_msb_to_lsb_flag[14] = ~divisor_sign ? |(D_times_3[65:15]) : ~(&(D_times_3[64:15]));
|
||||
assign D_times_3_msb_to_lsb_flag[15] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[16] = ~divisor_sign ? |(D_times_3[65:17]) : ~(&(D_times_3[64:17]));
|
||||
assign D_times_3_msb_to_lsb_flag[17] = ~divisor_sign ? |(D_times_3[65:18]) : ~(&(D_times_3[64:18]));
|
||||
assign D_times_3_msb_to_lsb_flag[18] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[19] = ~divisor_sign ? |(D_times_3[65:20]) : ~(&(D_times_3[64:20]));
|
||||
assign D_times_3_msb_to_lsb_flag[20] = ~divisor_sign ? |(D_times_3[65:21]) : ~(&(D_times_3[64:21]));
|
||||
assign D_times_3_msb_to_lsb_flag[21] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[22] = ~divisor_sign ? |(D_times_3[65:23]) : ~(&(D_times_3[64:23]));
|
||||
assign D_times_3_msb_to_lsb_flag[23] = ~divisor_sign ? |(D_times_3[65:24]) : ~(&(D_times_3[64:24]));
|
||||
assign D_times_3_msb_to_lsb_flag[24] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[25] = ~divisor_sign ? |(D_times_3[65:26]) : ~(&(D_times_3[64:26]));
|
||||
assign D_times_3_msb_to_lsb_flag[26] = ~divisor_sign ? |(D_times_3[65:27]) : ~(&(D_times_3[64:27]));
|
||||
assign D_times_3_msb_to_lsb_flag[27] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[28] = ~divisor_sign ? |(D_times_3[65:29]) : ~(&(D_times_3[64:29]));
|
||||
assign D_times_3_msb_to_lsb_flag[29] = ~divisor_sign ? |(D_times_3[65:30]) : ~(&(D_times_3[64:30]));
|
||||
assign D_times_3_msb_to_lsb_flag[30] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[31] = ~divisor_sign ? |(D_times_3[65:32]) : ~(&(D_times_3[64:32]));
|
||||
assign D_times_3_msb_to_lsb_flag[32] = ~divisor_sign ? |(D_times_3[65:33]) : ~(&(D_times_3[64:33]));
|
||||
assign D_times_3_msb_to_lsb_flag[33] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[34] = ~divisor_sign ? |(D_times_3[65:35]) : ~(&(D_times_3[64:35]));
|
||||
assign D_times_3_msb_to_lsb_flag[35] = ~divisor_sign ? |(D_times_3[65:36]) : ~(&(D_times_3[64:36]));
|
||||
assign D_times_3_msb_to_lsb_flag[36] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[37] = ~divisor_sign ? |(D_times_3[65:38]) : ~(&(D_times_3[64:38]));
|
||||
assign D_times_3_msb_to_lsb_flag[38] = ~divisor_sign ? |(D_times_3[65:39]) : ~(&(D_times_3[64:39]));
|
||||
assign D_times_3_msb_to_lsb_flag[39] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[40] = ~divisor_sign ? |(D_times_3[65:41]) : ~(&(D_times_3[64:41]));
|
||||
assign D_times_3_msb_to_lsb_flag[41] = ~divisor_sign ? |(D_times_3[65:42]) : ~(&(D_times_3[64:42]));
|
||||
assign D_times_3_msb_to_lsb_flag[42] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[43] = ~divisor_sign ? |(D_times_3[65:44]) : ~(&(D_times_3[64:44]));
|
||||
assign D_times_3_msb_to_lsb_flag[44] = ~divisor_sign ? |(D_times_3[65:45]) : ~(&(D_times_3[64:45]));
|
||||
assign D_times_3_msb_to_lsb_flag[45] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[46] = ~divisor_sign ? |(D_times_3[65:47]) : ~(&(D_times_3[64:47]));
|
||||
assign D_times_3_msb_to_lsb_flag[47] = ~divisor_sign ? |(D_times_3[65:48]) : ~(&(D_times_3[64:48]));
|
||||
assign D_times_3_msb_to_lsb_flag[48] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[49] = ~divisor_sign ? |(D_times_3[65:50]) : ~(&(D_times_3[64:50]));
|
||||
assign D_times_3_msb_to_lsb_flag[50] = ~divisor_sign ? |(D_times_3[65:51]) : ~(&(D_times_3[64:51]));
|
||||
assign D_times_3_msb_to_lsb_flag[51] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[52] = ~divisor_sign ? |(D_times_3[65:53]) : ~(&(D_times_3[64:53]));
|
||||
assign D_times_3_msb_to_lsb_flag[53] = ~divisor_sign ? |(D_times_3[65:54]) : ~(&(D_times_3[64:54]));
|
||||
assign D_times_3_msb_to_lsb_flag[54] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[55] = ~divisor_sign ? |(D_times_3[65:56]) : ~(&(D_times_3[64:56]));
|
||||
assign D_times_3_msb_to_lsb_flag[56] = ~divisor_sign ? |(D_times_3[65:57]) : ~(&(D_times_3[64:57]));
|
||||
assign D_times_3_msb_to_lsb_flag[57] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[58] = ~divisor_sign ? |(D_times_3[65:59]) : ~(&(D_times_3[64:59]));
|
||||
assign D_times_3_msb_to_lsb_flag[59] = ~divisor_sign ? |(D_times_3[65:60]) : ~(&(D_times_3[64:60]));
|
||||
assign D_times_3_msb_to_lsb_flag[60] = 1'b0;
|
||||
assign D_times_3_msb_to_lsb_flag[61] = ~divisor_sign ? |(D_times_3[65:62]) : ~(&(D_times_3[64:62]));
|
||||
assign D_times_3_msb_to_lsb_flag[62] = ~divisor_sign ? |(D_times_3[65:63]) : ~(&(D_times_3[64:63]));
|
||||
assign D_times_3_msb_to_lsb_flag[63] = 1'b0;
|
||||
|
||||
// Only useful in stage[1, 2, 4, 5, 7, 8, ..., 61, 62], when D < 0.
|
||||
assign D_times_3_lsb_to_msb_flag[ 0] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[ 1] = divisor_sign ? ~(|(D_times_3[ 1:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[ 2] = divisor_sign ? ~(|(D_times_3[ 2:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[ 3] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[ 4] = divisor_sign ? ~(|(D_times_3[ 4:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[ 5] = divisor_sign ? ~(|(D_times_3[ 5:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[ 6] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[ 7] = divisor_sign ? ~(|(D_times_3[ 7:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[ 8] = divisor_sign ? ~(|(D_times_3[ 8:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[ 9] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[10] = divisor_sign ? ~(|(D_times_3[10:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[11] = divisor_sign ? ~(|(D_times_3[11:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[12] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[13] = divisor_sign ? ~(|(D_times_3[13:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[14] = divisor_sign ? ~(|(D_times_3[14:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[15] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[16] = divisor_sign ? ~(|(D_times_3[16:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[17] = divisor_sign ? ~(|(D_times_3[17:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[18] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[19] = divisor_sign ? ~(|(D_times_3[19:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[20] = divisor_sign ? ~(|(D_times_3[20:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[21] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[22] = divisor_sign ? ~(|(D_times_3[22:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[23] = divisor_sign ? ~(|(D_times_3[23:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[24] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[25] = divisor_sign ? ~(|(D_times_3[25:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[26] = divisor_sign ? ~(|(D_times_3[26:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[27] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[28] = divisor_sign ? ~(|(D_times_3[28:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[29] = divisor_sign ? ~(|(D_times_3[29:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[30] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[31] = divisor_sign ? ~(|(D_times_3[31:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[32] = divisor_sign ? ~(|(D_times_3[32:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[33] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[34] = divisor_sign ? ~(|(D_times_3[34:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[35] = divisor_sign ? ~(|(D_times_3[35:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[36] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[37] = divisor_sign ? ~(|(D_times_3[37:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[38] = divisor_sign ? ~(|(D_times_3[38:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[39] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[40] = divisor_sign ? ~(|(D_times_3[40:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[41] = divisor_sign ? ~(|(D_times_3[41:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[42] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[43] = divisor_sign ? ~(|(D_times_3[43:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[44] = divisor_sign ? ~(|(D_times_3[44:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[45] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[46] = divisor_sign ? ~(|(D_times_3[46:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[47] = divisor_sign ? ~(|(D_times_3[47:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[48] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[49] = divisor_sign ? ~(|(D_times_3[49:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[50] = divisor_sign ? ~(|(D_times_3[50:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[51] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[52] = divisor_sign ? ~(|(D_times_3[52:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[53] = divisor_sign ? ~(|(D_times_3[53:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[54] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[55] = divisor_sign ? ~(|(D_times_3[55:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[56] = divisor_sign ? ~(|(D_times_3[56:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[57] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[58] = divisor_sign ? ~(|(D_times_3[58:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[59] = divisor_sign ? ~(|(D_times_3[59:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[60] = 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[61] = divisor_sign ? ~(|(D_times_3[61:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[62] = divisor_sign ? ~(|(D_times_3[62:0])) : 1'b0;
|
||||
assign D_times_3_lsb_to_msb_flag[63] = 1'b0;
|
||||
|
||||
// Only useful in stage[1, 2, 4, 5, 7, 8, ..., 61, 62]
|
||||
assign D_times_5_msb_to_lsb_flag[ 0] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[ 1] = ~divisor_sign ? |(D_times_5[66: 2]) : ~(&(D_times_5[65: 2]));
|
||||
assign D_times_5_msb_to_lsb_flag[ 2] = ~divisor_sign ? |(D_times_5[66: 3]) : ~(&(D_times_5[65: 3]));
|
||||
assign D_times_5_msb_to_lsb_flag[ 3] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[ 4] = ~divisor_sign ? |(D_times_5[66: 5]) : ~(&(D_times_5[65: 5]));
|
||||
assign D_times_5_msb_to_lsb_flag[ 5] = ~divisor_sign ? |(D_times_5[66: 6]) : ~(&(D_times_5[65: 6]));
|
||||
assign D_times_5_msb_to_lsb_flag[ 6] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[ 7] = ~divisor_sign ? |(D_times_5[66: 8]) : ~(&(D_times_5[65: 8]));
|
||||
assign D_times_5_msb_to_lsb_flag[ 8] = ~divisor_sign ? |(D_times_5[66: 9]) : ~(&(D_times_5[65: 9]));
|
||||
assign D_times_5_msb_to_lsb_flag[ 9] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[10] = ~divisor_sign ? |(D_times_5[66:11]) : ~(&(D_times_5[65:11]));
|
||||
assign D_times_5_msb_to_lsb_flag[11] = ~divisor_sign ? |(D_times_5[66:12]) : ~(&(D_times_5[65:12]));
|
||||
assign D_times_5_msb_to_lsb_flag[12] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[13] = ~divisor_sign ? |(D_times_5[66:14]) : ~(&(D_times_5[65:14]));
|
||||
assign D_times_5_msb_to_lsb_flag[14] = ~divisor_sign ? |(D_times_5[66:15]) : ~(&(D_times_5[65:15]));
|
||||
assign D_times_5_msb_to_lsb_flag[15] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[16] = ~divisor_sign ? |(D_times_5[66:17]) : ~(&(D_times_5[65:17]));
|
||||
assign D_times_5_msb_to_lsb_flag[17] = ~divisor_sign ? |(D_times_5[66:18]) : ~(&(D_times_5[65:18]));
|
||||
assign D_times_5_msb_to_lsb_flag[18] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[19] = ~divisor_sign ? |(D_times_5[66:20]) : ~(&(D_times_5[65:20]));
|
||||
assign D_times_5_msb_to_lsb_flag[20] = ~divisor_sign ? |(D_times_5[66:21]) : ~(&(D_times_5[65:21]));
|
||||
assign D_times_5_msb_to_lsb_flag[21] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[22] = ~divisor_sign ? |(D_times_5[66:23]) : ~(&(D_times_5[65:23]));
|
||||
assign D_times_5_msb_to_lsb_flag[23] = ~divisor_sign ? |(D_times_5[66:24]) : ~(&(D_times_5[65:24]));
|
||||
assign D_times_5_msb_to_lsb_flag[24] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[25] = ~divisor_sign ? |(D_times_5[66:26]) : ~(&(D_times_5[65:26]));
|
||||
assign D_times_5_msb_to_lsb_flag[26] = ~divisor_sign ? |(D_times_5[66:27]) : ~(&(D_times_5[65:27]));
|
||||
assign D_times_5_msb_to_lsb_flag[27] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[28] = ~divisor_sign ? |(D_times_5[66:29]) : ~(&(D_times_5[65:29]));
|
||||
assign D_times_5_msb_to_lsb_flag[29] = ~divisor_sign ? |(D_times_5[66:30]) : ~(&(D_times_5[65:30]));
|
||||
assign D_times_5_msb_to_lsb_flag[30] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[31] = ~divisor_sign ? |(D_times_5[66:32]) : ~(&(D_times_5[65:32]));
|
||||
assign D_times_5_msb_to_lsb_flag[32] = ~divisor_sign ? |(D_times_5[66:33]) : ~(&(D_times_5[65:33]));
|
||||
assign D_times_5_msb_to_lsb_flag[33] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[34] = ~divisor_sign ? |(D_times_5[66:35]) : ~(&(D_times_5[65:35]));
|
||||
assign D_times_5_msb_to_lsb_flag[35] = ~divisor_sign ? |(D_times_5[66:36]) : ~(&(D_times_5[65:36]));
|
||||
assign D_times_5_msb_to_lsb_flag[36] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[37] = ~divisor_sign ? |(D_times_5[66:38]) : ~(&(D_times_5[65:38]));
|
||||
assign D_times_5_msb_to_lsb_flag[38] = ~divisor_sign ? |(D_times_5[66:39]) : ~(&(D_times_5[65:39]));
|
||||
assign D_times_5_msb_to_lsb_flag[39] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[40] = ~divisor_sign ? |(D_times_5[66:41]) : ~(&(D_times_5[65:41]));
|
||||
assign D_times_5_msb_to_lsb_flag[41] = ~divisor_sign ? |(D_times_5[66:42]) : ~(&(D_times_5[65:42]));
|
||||
assign D_times_5_msb_to_lsb_flag[42] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[43] = ~divisor_sign ? |(D_times_5[66:44]) : ~(&(D_times_5[65:44]));
|
||||
assign D_times_5_msb_to_lsb_flag[44] = ~divisor_sign ? |(D_times_5[66:45]) : ~(&(D_times_5[65:45]));
|
||||
assign D_times_5_msb_to_lsb_flag[45] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[46] = ~divisor_sign ? |(D_times_5[66:47]) : ~(&(D_times_5[65:47]));
|
||||
assign D_times_5_msb_to_lsb_flag[47] = ~divisor_sign ? |(D_times_5[66:48]) : ~(&(D_times_5[65:48]));
|
||||
assign D_times_5_msb_to_lsb_flag[48] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[49] = ~divisor_sign ? |(D_times_5[66:50]) : ~(&(D_times_5[65:50]));
|
||||
assign D_times_5_msb_to_lsb_flag[50] = ~divisor_sign ? |(D_times_5[66:51]) : ~(&(D_times_5[65:51]));
|
||||
assign D_times_5_msb_to_lsb_flag[51] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[52] = ~divisor_sign ? |(D_times_5[66:53]) : ~(&(D_times_5[65:53]));
|
||||
assign D_times_5_msb_to_lsb_flag[53] = ~divisor_sign ? |(D_times_5[66:54]) : ~(&(D_times_5[65:54]));
|
||||
assign D_times_5_msb_to_lsb_flag[54] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[55] = ~divisor_sign ? |(D_times_5[66:56]) : ~(&(D_times_5[65:56]));
|
||||
assign D_times_5_msb_to_lsb_flag[56] = ~divisor_sign ? |(D_times_5[66:57]) : ~(&(D_times_5[65:57]));
|
||||
assign D_times_5_msb_to_lsb_flag[57] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[58] = ~divisor_sign ? |(D_times_5[66:59]) : ~(&(D_times_5[65:59]));
|
||||
assign D_times_5_msb_to_lsb_flag[59] = ~divisor_sign ? |(D_times_5[66:60]) : ~(&(D_times_5[65:60]));
|
||||
assign D_times_5_msb_to_lsb_flag[60] = 1'b0;
|
||||
assign D_times_5_msb_to_lsb_flag[61] = ~divisor_sign ? |(D_times_5[66:62]) : ~(&(D_times_5[65:62]));
|
||||
assign D_times_5_msb_to_lsb_flag[62] = ~divisor_sign ? |(D_times_5[66:63]) : ~(&(D_times_5[65:63]));
|
||||
assign D_times_5_msb_to_lsb_flag[63] = 1'b0;
|
||||
|
||||
// Only useful in stage[1, 2, 4, 5, 7, 8, ..., 61, 62], when D < 0.
|
||||
assign D_times_5_lsb_to_msb_flag[ 0] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[ 1] = divisor_sign ? ~(|(D_times_5[ 1:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[ 2] = divisor_sign ? ~(|(D_times_5[ 2:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[ 3] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[ 4] = divisor_sign ? ~(|(D_times_5[ 4:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[ 5] = divisor_sign ? ~(|(D_times_5[ 5:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[ 6] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[ 7] = divisor_sign ? ~(|(D_times_5[ 7:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[ 8] = divisor_sign ? ~(|(D_times_5[ 8:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[ 9] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[10] = divisor_sign ? ~(|(D_times_5[10:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[11] = divisor_sign ? ~(|(D_times_5[11:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[12] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[13] = divisor_sign ? ~(|(D_times_5[13:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[14] = divisor_sign ? ~(|(D_times_5[14:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[15] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[16] = divisor_sign ? ~(|(D_times_5[16:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[17] = divisor_sign ? ~(|(D_times_5[17:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[18] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[19] = divisor_sign ? ~(|(D_times_5[19:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[20] = divisor_sign ? ~(|(D_times_5[20:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[21] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[22] = divisor_sign ? ~(|(D_times_5[22:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[23] = divisor_sign ? ~(|(D_times_5[23:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[24] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[25] = divisor_sign ? ~(|(D_times_5[25:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[26] = divisor_sign ? ~(|(D_times_5[26:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[27] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[28] = divisor_sign ? ~(|(D_times_5[28:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[29] = divisor_sign ? ~(|(D_times_5[29:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[30] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[31] = divisor_sign ? ~(|(D_times_5[31:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[32] = divisor_sign ? ~(|(D_times_5[32:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[33] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[34] = divisor_sign ? ~(|(D_times_5[34:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[35] = divisor_sign ? ~(|(D_times_5[35:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[36] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[37] = divisor_sign ? ~(|(D_times_5[37:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[38] = divisor_sign ? ~(|(D_times_5[38:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[39] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[40] = divisor_sign ? ~(|(D_times_5[40:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[41] = divisor_sign ? ~(|(D_times_5[41:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[42] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[43] = divisor_sign ? ~(|(D_times_5[43:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[44] = divisor_sign ? ~(|(D_times_5[44:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[45] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[46] = divisor_sign ? ~(|(D_times_5[46:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[47] = divisor_sign ? ~(|(D_times_5[47:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[48] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[49] = divisor_sign ? ~(|(D_times_5[49:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[50] = divisor_sign ? ~(|(D_times_5[50:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[51] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[52] = divisor_sign ? ~(|(D_times_5[52:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[53] = divisor_sign ? ~(|(D_times_5[53:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[54] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[55] = divisor_sign ? ~(|(D_times_5[55:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[56] = divisor_sign ? ~(|(D_times_5[56:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[57] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[58] = divisor_sign ? ~(|(D_times_5[58:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[59] = divisor_sign ? ~(|(D_times_5[59:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[60] = 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[61] = divisor_sign ? ~(|(D_times_5[61:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[62] = divisor_sign ? ~(|(D_times_5[62:0])) : 1'b0;
|
||||
assign D_times_5_lsb_to_msb_flag[63] = 1'b0;
|
||||
|
||||
// Only useful in stage[1, 2, 4, 5, 7, 8, ..., 61, 62]
|
||||
assign D_times_7_msb_to_lsb_flag[ 0] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[ 1] = ~divisor_sign ? |(D_times_7[66: 2]) : ~(&(D_times_7[65: 2]));
|
||||
assign D_times_7_msb_to_lsb_flag[ 2] = ~divisor_sign ? |(D_times_7[66: 3]) : ~(&(D_times_7[65: 3]));
|
||||
assign D_times_7_msb_to_lsb_flag[ 3] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[ 4] = ~divisor_sign ? |(D_times_7[66: 5]) : ~(&(D_times_7[65: 5]));
|
||||
assign D_times_7_msb_to_lsb_flag[ 5] = ~divisor_sign ? |(D_times_7[66: 6]) : ~(&(D_times_7[65: 6]));
|
||||
assign D_times_7_msb_to_lsb_flag[ 6] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[ 7] = ~divisor_sign ? |(D_times_7[66: 8]) : ~(&(D_times_7[65: 8]));
|
||||
assign D_times_7_msb_to_lsb_flag[ 8] = ~divisor_sign ? |(D_times_7[66: 9]) : ~(&(D_times_7[65: 9]));
|
||||
assign D_times_7_msb_to_lsb_flag[ 9] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[10] = ~divisor_sign ? |(D_times_7[66:11]) : ~(&(D_times_7[65:11]));
|
||||
assign D_times_7_msb_to_lsb_flag[11] = ~divisor_sign ? |(D_times_7[66:12]) : ~(&(D_times_7[65:12]));
|
||||
assign D_times_7_msb_to_lsb_flag[12] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[13] = ~divisor_sign ? |(D_times_7[66:14]) : ~(&(D_times_7[65:14]));
|
||||
assign D_times_7_msb_to_lsb_flag[14] = ~divisor_sign ? |(D_times_7[66:15]) : ~(&(D_times_7[65:15]));
|
||||
assign D_times_7_msb_to_lsb_flag[15] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[16] = ~divisor_sign ? |(D_times_7[66:17]) : ~(&(D_times_7[65:17]));
|
||||
assign D_times_7_msb_to_lsb_flag[17] = ~divisor_sign ? |(D_times_7[66:18]) : ~(&(D_times_7[65:18]));
|
||||
assign D_times_7_msb_to_lsb_flag[18] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[19] = ~divisor_sign ? |(D_times_7[66:20]) : ~(&(D_times_7[65:20]));
|
||||
assign D_times_7_msb_to_lsb_flag[20] = ~divisor_sign ? |(D_times_7[66:21]) : ~(&(D_times_7[65:21]));
|
||||
assign D_times_7_msb_to_lsb_flag[21] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[22] = ~divisor_sign ? |(D_times_7[66:23]) : ~(&(D_times_7[65:23]));
|
||||
assign D_times_7_msb_to_lsb_flag[23] = ~divisor_sign ? |(D_times_7[66:24]) : ~(&(D_times_7[65:24]));
|
||||
assign D_times_7_msb_to_lsb_flag[24] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[25] = ~divisor_sign ? |(D_times_7[66:26]) : ~(&(D_times_7[65:26]));
|
||||
assign D_times_7_msb_to_lsb_flag[26] = ~divisor_sign ? |(D_times_7[66:27]) : ~(&(D_times_7[65:27]));
|
||||
assign D_times_7_msb_to_lsb_flag[27] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[28] = ~divisor_sign ? |(D_times_7[66:29]) : ~(&(D_times_7[65:29]));
|
||||
assign D_times_7_msb_to_lsb_flag[29] = ~divisor_sign ? |(D_times_7[66:30]) : ~(&(D_times_7[65:30]));
|
||||
assign D_times_7_msb_to_lsb_flag[30] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[31] = ~divisor_sign ? |(D_times_7[66:32]) : ~(&(D_times_7[65:32]));
|
||||
assign D_times_7_msb_to_lsb_flag[32] = ~divisor_sign ? |(D_times_7[66:33]) : ~(&(D_times_7[65:33]));
|
||||
assign D_times_7_msb_to_lsb_flag[33] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[34] = ~divisor_sign ? |(D_times_7[66:35]) : ~(&(D_times_7[65:35]));
|
||||
assign D_times_7_msb_to_lsb_flag[35] = ~divisor_sign ? |(D_times_7[66:36]) : ~(&(D_times_7[65:36]));
|
||||
assign D_times_7_msb_to_lsb_flag[36] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[37] = ~divisor_sign ? |(D_times_7[66:38]) : ~(&(D_times_7[65:38]));
|
||||
assign D_times_7_msb_to_lsb_flag[38] = ~divisor_sign ? |(D_times_7[66:39]) : ~(&(D_times_7[65:39]));
|
||||
assign D_times_7_msb_to_lsb_flag[39] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[40] = ~divisor_sign ? |(D_times_7[66:41]) : ~(&(D_times_7[65:41]));
|
||||
assign D_times_7_msb_to_lsb_flag[41] = ~divisor_sign ? |(D_times_7[66:42]) : ~(&(D_times_7[65:42]));
|
||||
assign D_times_7_msb_to_lsb_flag[42] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[43] = ~divisor_sign ? |(D_times_7[66:44]) : ~(&(D_times_7[65:44]));
|
||||
assign D_times_7_msb_to_lsb_flag[44] = ~divisor_sign ? |(D_times_7[66:45]) : ~(&(D_times_7[65:45]));
|
||||
assign D_times_7_msb_to_lsb_flag[45] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[46] = ~divisor_sign ? |(D_times_7[66:47]) : ~(&(D_times_7[65:47]));
|
||||
assign D_times_7_msb_to_lsb_flag[47] = ~divisor_sign ? |(D_times_7[66:48]) : ~(&(D_times_7[65:48]));
|
||||
assign D_times_7_msb_to_lsb_flag[48] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[49] = ~divisor_sign ? |(D_times_7[66:50]) : ~(&(D_times_7[65:50]));
|
||||
assign D_times_7_msb_to_lsb_flag[50] = ~divisor_sign ? |(D_times_7[66:51]) : ~(&(D_times_7[65:51]));
|
||||
assign D_times_7_msb_to_lsb_flag[51] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[52] = ~divisor_sign ? |(D_times_7[66:53]) : ~(&(D_times_7[65:53]));
|
||||
assign D_times_7_msb_to_lsb_flag[53] = ~divisor_sign ? |(D_times_7[66:54]) : ~(&(D_times_7[65:54]));
|
||||
assign D_times_7_msb_to_lsb_flag[54] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[55] = ~divisor_sign ? |(D_times_7[66:56]) : ~(&(D_times_7[65:56]));
|
||||
assign D_times_7_msb_to_lsb_flag[56] = ~divisor_sign ? |(D_times_7[66:57]) : ~(&(D_times_7[65:57]));
|
||||
assign D_times_7_msb_to_lsb_flag[57] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[58] = ~divisor_sign ? |(D_times_7[66:59]) : ~(&(D_times_7[65:59]));
|
||||
assign D_times_7_msb_to_lsb_flag[59] = ~divisor_sign ? |(D_times_7[66:60]) : ~(&(D_times_7[65:60]));
|
||||
assign D_times_7_msb_to_lsb_flag[60] = 1'b0;
|
||||
assign D_times_7_msb_to_lsb_flag[61] = ~divisor_sign ? |(D_times_7[66:62]) : ~(&(D_times_7[65:62]));
|
||||
assign D_times_7_msb_to_lsb_flag[62] = ~divisor_sign ? |(D_times_7[66:63]) : ~(&(D_times_7[65:63]));
|
||||
assign D_times_7_msb_to_lsb_flag[63] = 1'b0;
|
||||
|
||||
// Only useful in stage[1, 2, 4, 5, 7, 8, ..., 61, 62], when D < 0.
|
||||
assign D_times_7_lsb_to_msb_flag[ 0] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[ 1] = divisor_sign ? ~(|(D_times_7[ 1:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[ 2] = divisor_sign ? ~(|(D_times_7[ 2:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[ 3] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[ 4] = divisor_sign ? ~(|(D_times_7[ 4:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[ 5] = divisor_sign ? ~(|(D_times_7[ 5:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[ 6] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[ 7] = divisor_sign ? ~(|(D_times_7[ 7:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[ 8] = divisor_sign ? ~(|(D_times_7[ 8:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[ 9] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[10] = divisor_sign ? ~(|(D_times_7[10:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[11] = divisor_sign ? ~(|(D_times_7[11:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[12] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[13] = divisor_sign ? ~(|(D_times_7[13:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[14] = divisor_sign ? ~(|(D_times_7[14:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[15] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[16] = divisor_sign ? ~(|(D_times_7[16:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[17] = divisor_sign ? ~(|(D_times_7[17:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[18] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[19] = divisor_sign ? ~(|(D_times_7[19:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[20] = divisor_sign ? ~(|(D_times_7[20:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[21] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[22] = divisor_sign ? ~(|(D_times_7[22:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[23] = divisor_sign ? ~(|(D_times_7[23:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[24] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[25] = divisor_sign ? ~(|(D_times_7[25:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[26] = divisor_sign ? ~(|(D_times_7[26:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[27] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[28] = divisor_sign ? ~(|(D_times_7[28:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[29] = divisor_sign ? ~(|(D_times_7[29:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[30] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[31] = divisor_sign ? ~(|(D_times_7[31:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[32] = divisor_sign ? ~(|(D_times_7[32:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[33] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[34] = divisor_sign ? ~(|(D_times_7[34:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[35] = divisor_sign ? ~(|(D_times_7[35:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[36] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[37] = divisor_sign ? ~(|(D_times_7[37:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[38] = divisor_sign ? ~(|(D_times_7[38:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[39] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[40] = divisor_sign ? ~(|(D_times_7[40:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[41] = divisor_sign ? ~(|(D_times_7[41:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[42] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[43] = divisor_sign ? ~(|(D_times_7[43:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[44] = divisor_sign ? ~(|(D_times_7[44:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[45] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[46] = divisor_sign ? ~(|(D_times_7[46:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[47] = divisor_sign ? ~(|(D_times_7[47:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[48] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[49] = divisor_sign ? ~(|(D_times_7[49:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[50] = divisor_sign ? ~(|(D_times_7[50:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[51] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[52] = divisor_sign ? ~(|(D_times_7[52:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[53] = divisor_sign ? ~(|(D_times_7[53:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[54] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[55] = divisor_sign ? ~(|(D_times_7[55:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[56] = divisor_sign ? ~(|(D_times_7[56:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[57] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[58] = divisor_sign ? ~(|(D_times_7[58:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[59] = divisor_sign ? ~(|(D_times_7[59:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[60] = 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[61] = divisor_sign ? ~(|(D_times_7[61:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[62] = divisor_sign ? ~(|(D_times_7[62:0])) : 1'b0;
|
||||
assign D_times_7_lsb_to_msb_flag[63] = 1'b0;
|
||||
|
||||
// ==================================================================================================================================================
|
||||
// stage[0, 1]
|
||||
// ==================================================================================================================================================
|
||||
|
||||
// stage[0]
|
||||
assign {rem_cout[0], rem_sum[0][0:0]} =
|
||||
{1'b0, dividend_abs[63]}
|
||||
+ {1'b0, {(1){~divisor_sign}} ^ D[0:0]}
|
||||
+ {1'b0, ~divisor_sign};
|
||||
assign force_q_to_zero[0] = D_msb_to_lsb_flag[0] | D_lsb_to_msb_flag[0];
|
||||
assign quo_iter[0] = force_q_to_zero[0] ? 1'b0 : rem_cout[0];
|
||||
// assign rem[0][0:0] = quo_iter[0] ? rem_sum[0][0:0] : dividend_abs[63];
|
||||
|
||||
// stage[1]
|
||||
assign {rem_cout_prev_q_0[1], rem_sum_prev_q_0[1][1:0]} =
|
||||
{1'b0, dividend_abs[63:62]}
|
||||
+ {1'b0, {(2){~divisor_sign}} ^ D[1:0]}
|
||||
+ {2'b0, ~divisor_sign};
|
||||
assign force_q_to_zero_prev_q_0[1] = D_msb_to_lsb_flag[1] | D_lsb_to_msb_flag[1];
|
||||
assign q_prev_q_0[1] = force_q_to_zero_prev_q_0[1] ? 1'b0 : rem_cout_prev_q_0[1];
|
||||
assign rem_prev_q_0[1][1:0] = q_prev_q_0[1] ? rem_sum_prev_q_0[1][1:0] : dividend_abs[63:62];
|
||||
|
||||
assign {rem_cout_prev_q_1[1], rem_sum_prev_q_1[1][1:0]} =
|
||||
{1'b0, dividend_abs[63:62]}
|
||||
+ {1'b0, {(2){~divisor_sign}} ^ D_times_3[1:0]}
|
||||
+ {2'b0, ~divisor_sign};
|
||||
assign force_q_to_zero_prev_q_1[1] = D_times_3_msb_to_lsb_flag[1] | D_times_3_lsb_to_msb_flag[1];
|
||||
assign q_prev_q_1[1] = force_q_to_zero_prev_q_1[1] ? 1'b0 : rem_cout_prev_q_1[1];
|
||||
assign rem_prev_q_1[1][1:0] = q_prev_q_1[1] ? rem_sum_prev_q_1[1][1:0] : {rem_sum[0][0:0], dividend_abs[62]};
|
||||
|
||||
// stage[2]
|
||||
assign {rem_cout_prev_q_00[2], rem_sum_prev_q_00[2][2:0]} =
|
||||
{1'b0, dividend_abs[63:61]}
|
||||
+ {1'b0, {(3){~divisor_sign}} ^ D[2:0]}
|
||||
+ {3'b0, ~divisor_sign};
|
||||
assign force_q_to_zero_prev_q_00[2] = D_msb_to_lsb_flag[2] | D_lsb_to_msb_flag[2];
|
||||
assign q_prev_q_00[2] = force_q_to_zero_prev_q_00[2] ? 1'b0 : rem_cout_prev_q_00[2];
|
||||
assign rem_prev_q_00[2][2:0] = q_prev_q_00[2] ? rem_sum_prev_q_00[2][2:0] : dividend_abs[63:61];
|
||||
|
||||
assign {rem_cout_prev_q_01[2], rem_sum_prev_q_01[2][2:0]} =
|
||||
{1'b0, dividend_abs[63:61]}
|
||||
+ {1'b0, {(3){~divisor_sign}} ^ D_times_3[2:0]}
|
||||
+ {3'b0, ~divisor_sign};
|
||||
assign force_q_to_zero_prev_q_01[2] = D_times_3_msb_to_lsb_flag[2] | D_times_3_lsb_to_msb_flag[2];
|
||||
assign q_prev_q_01[2] = force_q_to_zero_prev_q_01[2] ? 1'b0 : rem_cout_prev_q_01[2];
|
||||
assign rem_prev_q_01[2][2:0] = q_prev_q_01[2] ? rem_sum_prev_q_01[2][2:0] : {rem_sum_prev_q_0[1][1:0], dividend_abs[61]};
|
||||
|
||||
assign {rem_cout_prev_q_10[2], rem_sum_prev_q_10[2][2:0]} =
|
||||
{1'b0, dividend_abs[63:61]}
|
||||
+ {1'b0, {(3){~divisor_sign}} ^ D_times_5[2:0]}
|
||||
+ {3'b0, ~divisor_sign};
|
||||
assign force_q_to_zero_prev_q_10[2] = D_times_5_msb_to_lsb_flag[2] | D_times_5_lsb_to_msb_flag[2];
|
||||
assign q_prev_q_10[2] = force_q_to_zero_prev_q_10[2] ? 1'b0 : rem_cout_prev_q_10[2];
|
||||
assign rem_prev_q_10[2][2:0] = q_prev_q_10[2] ? rem_sum_prev_q_10[2][2:0] : {rem_sum[0][0:0], dividend_abs[62:61]};
|
||||
|
||||
assign {rem_cout_prev_q_11[2], rem_sum_prev_q_11[2][2:0]} =
|
||||
{1'b0, dividend_abs[63:61]}
|
||||
+ {1'b0, {(3){~divisor_sign}} ^ D_times_7[2:0]}
|
||||
+ {3'b0, ~divisor_sign};
|
||||
assign force_q_to_zero_prev_q_11[2] = D_times_7_msb_to_lsb_flag[2] | D_times_7_lsb_to_msb_flag[2];
|
||||
assign q_prev_q_11[2] = force_q_to_zero_prev_q_11[2] ? 1'b0 : rem_cout_prev_q_11[2];
|
||||
assign rem_prev_q_11[2][2:0] = q_prev_q_11[2] ? rem_sum_prev_q_11[2][2:0] : {rem_sum_prev_q_1[1][1:0], dividend_abs[61]};
|
||||
|
||||
assign quo_iter[1] = quo_iter[0] ? q_prev_q_1[1] : q_prev_q_0[1];
|
||||
// assign rem[1][1:0] = quo_iter[0] ? rem_prev_q_1[1][1:0] : rem_prev_q_0[1][1:0];
|
||||
assign quo_iter[2] =
|
||||
({(1){{quo_iter[0], quo_iter[1]} == 2'b00}} & q_prev_q_00[2])
|
||||
| ({(1){{quo_iter[0], quo_iter[1]} == 2'b01}} & q_prev_q_01[2])
|
||||
| ({(1){{quo_iter[0], quo_iter[1]} == 2'b10}} & q_prev_q_10[2])
|
||||
| ({(1){{quo_iter[0], quo_iter[1]} == 2'b11}} & q_prev_q_11[2]);
|
||||
assign rem[2][2:0] =
|
||||
({(3){{quo_iter[0], quo_iter[1]} == 2'b00}} & rem_prev_q_00[2][2:0])
|
||||
| ({(3){{quo_iter[0], quo_iter[1]} == 2'b01}} & rem_prev_q_01[2][2:0])
|
||||
| ({(3){{quo_iter[0], quo_iter[1]} == 2'b10}} & rem_prev_q_10[2][2:0])
|
||||
| ({(3){{quo_iter[0], quo_iter[1]} == 2'b11}} & rem_prev_q_11[2][2:0]);
|
||||
|
||||
for(i = 3; i <= 60; i = i + 3) begin: g_restoring_stage_3_to_62
|
||||
|
||||
always_comb begin
|
||||
|
||||
// stage[3n]
|
||||
{rem_cout[i], rem_sum[i][i:0]} =
|
||||
{1'b0, rem[i-1][i-1:0], dividend_abs[63-i]}
|
||||
+ {1'b0, {(i + 1){~divisor_sign}} ^ D[i:0]}
|
||||
+ {{(i + 1){1'b0}}, ~divisor_sign};
|
||||
force_q_to_zero[i] = D_msb_to_lsb_flag[i] | D_lsb_to_msb_flag[i];
|
||||
quo_iter[i] = force_q_to_zero[i] ? 1'b0 : rem_cout[i];
|
||||
// rem[i][i:0] = quo_iter[i] ? rem_sum[i][i:0] : {rem[i-1][i-1:0], dividend_abs[63-i]};
|
||||
|
||||
// stage[3n + 1], assume previous quo is 0
|
||||
{rem_cout_prev_q_0[i+1], rem_sum_prev_q_0[i+1][i+1:0]} =
|
||||
{1'b0, rem[i-1][i-1:0], dividend_abs[63-i -: 2]}
|
||||
+ {1'b0, {(i + 2){~divisor_sign}} ^ D[i+1:0]}
|
||||
+ {{(i + 2){1'b0}}, ~divisor_sign};
|
||||
force_q_to_zero_prev_q_0[i+1] = D_msb_to_lsb_flag[i+1] | D_lsb_to_msb_flag[i+1];
|
||||
q_prev_q_0[i+1] = force_q_to_zero_prev_q_0[i+1] ? 1'b0 : rem_cout_prev_q_0[i+1];
|
||||
rem_prev_q_0[i+1][i+1:0] = q_prev_q_0[i+1] ? rem_sum_prev_q_0[i+1][i+1:0] : {rem[i-1][i-1:0], dividend_abs[63-i -: 2]};
|
||||
|
||||
// stage[3n + 1], assume previous quo is 1
|
||||
{rem_cout_prev_q_1[i+1], rem_sum_prev_q_1[i+1][i+1:0]} =
|
||||
{1'b0, rem[i-1][i-1:0], dividend_abs[63-i -: 2]}
|
||||
+ {1'b0, {(i + 2){~divisor_sign}} ^ D_times_3[i+1:0]}
|
||||
+ {{(i + 2){1'b0}}, ~divisor_sign};
|
||||
force_q_to_zero_prev_q_1[i+1] = D_times_3_msb_to_lsb_flag[i+1] | D_times_3_lsb_to_msb_flag[i+1];
|
||||
q_prev_q_1[i+1] = force_q_to_zero_prev_q_1[i+1] ? 1'b0 : rem_cout_prev_q_1[i+1];
|
||||
// Since we assume quo of stage[2n] is 1, so the rem of stage[2n] must be rem_sum[i]
|
||||
rem_prev_q_1[i+1][i+1:0] = q_prev_q_1[i+1] ? rem_sum_prev_q_1[i+1][i+1:0] : {rem_sum[i][i:0], dividend_abs[63-1-i]};
|
||||
|
||||
// stage[3n + 2], assume previous quo is 00
|
||||
{rem_cout_prev_q_00[i+2], rem_sum_prev_q_00[i+2][i+2:0]} =
|
||||
{1'b0, rem[i-1][i-1:0], dividend_abs[63-i -: 3]}
|
||||
+ {1'b0, {(i + 3){~divisor_sign}} ^ D[i+2:0]}
|
||||
+ {{(i + 3){1'b0}}, ~divisor_sign};
|
||||
force_q_to_zero_prev_q_00[i+2] = D_msb_to_lsb_flag[i+2] | D_lsb_to_msb_flag[i+2];
|
||||
q_prev_q_00[i+2] = force_q_to_zero_prev_q_00[i+2] ? 1'b0 : rem_cout_prev_q_00[i+2];
|
||||
rem_prev_q_00[i+2][i+2:0] = q_prev_q_00[i+2] ? rem_sum_prev_q_00[i+2][i+2:0] : {rem[i-1][i-1:0], dividend_abs[63-i -: 3]};
|
||||
|
||||
// assume previous quo is 01
|
||||
{rem_cout_prev_q_01[i+2], rem_sum_prev_q_01[i+2][i+2:0]} =
|
||||
{1'b0, rem[i-1][i-1:0], dividend_abs[63-i -: 3]}
|
||||
+ {1'b0, {(i + 3){~divisor_sign}} ^ D_times_3[i+2:0]}
|
||||
+ {{(i + 3){1'b0}}, ~divisor_sign};
|
||||
force_q_to_zero_prev_q_01[i+2] = D_times_3_msb_to_lsb_flag[i+2] | D_times_3_lsb_to_msb_flag[i+2];
|
||||
q_prev_q_01[i+2] = force_q_to_zero_prev_q_01[i+2] ? 1'b0 : rem_cout_prev_q_01[i+2];
|
||||
rem_prev_q_01[i+2][i+2:0] = q_prev_q_01[i+2] ? rem_sum_prev_q_01[i+2][i+2:0] : {rem_sum_prev_q_0[i+1][i+1:0], dividend_abs[63-2-i]};
|
||||
|
||||
// assume previous quo is 10
|
||||
{rem_cout_prev_q_10[i+2], rem_sum_prev_q_10[i+2][i+2:0]} =
|
||||
{1'b0, rem[i-1][i-1:0], dividend_abs[63-i -: 3]}
|
||||
+ {1'b0, {(i + 3){~divisor_sign}} ^ D_times_5[i+2:0]}
|
||||
+ {{(i + 3){1'b0}}, ~divisor_sign};
|
||||
force_q_to_zero_prev_q_10[i+2] = D_times_5_msb_to_lsb_flag[i+2] | D_times_5_lsb_to_msb_flag[i+2];
|
||||
q_prev_q_10[i+2] = force_q_to_zero_prev_q_10[i+2] ? 1'b0 : rem_cout_prev_q_10[i+2];
|
||||
rem_prev_q_10[i+2][i+2:0] = q_prev_q_10[i+2] ? rem_sum_prev_q_10[i+2][i+2:0] : {rem_sum[i][i:0], dividend_abs[63-1-i : 63-2-i]};
|
||||
|
||||
// assume previous quo is 11
|
||||
{rem_cout_prev_q_11[i+2], rem_sum_prev_q_11[i+2][i+2:0]} =
|
||||
{1'b0, rem[i-1][i-1:0], dividend_abs[63-i -: 3]}
|
||||
+ {1'b0, {(i + 3){~divisor_sign}} ^ D_times_7[i+2:0]}
|
||||
+ {{(i + 3){1'b0}}, ~divisor_sign};
|
||||
force_q_to_zero_prev_q_11[i+2] = D_times_7_msb_to_lsb_flag[i+2] | D_times_7_lsb_to_msb_flag[i+2];
|
||||
q_prev_q_11[i+2] = force_q_to_zero_prev_q_11[i+2] ? 1'b0 : rem_cout_prev_q_11[i+2];
|
||||
rem_prev_q_11[i+2][i+2:0] = q_prev_q_11[i+2] ? rem_sum_prev_q_11[i+2][i+2:0] : {rem_sum_prev_q_1[i+1][i+1:0], dividend_abs[63-2-i]};
|
||||
|
||||
quo_iter[i+1] = quo_iter[i] ? q_prev_q_1[i+1] : q_prev_q_0[i+1];
|
||||
// rem[i+1][i+1:0] = quo_iter[i] ? rem_prev_q_1[i+1][i+1:0] : rem_prev_q_0[i+1][i+1:0];
|
||||
quo_iter[i+2] =
|
||||
({(1){{quo_iter[i], quo_iter[i+1]} == 2'b00}} & q_prev_q_00[i+2])
|
||||
| ({(1){{quo_iter[i], quo_iter[i+1]} == 2'b01}} & q_prev_q_01[i+2])
|
||||
| ({(1){{quo_iter[i], quo_iter[i+1]} == 2'b10}} & q_prev_q_10[i+2])
|
||||
| ({(1){{quo_iter[i], quo_iter[i+1]} == 2'b11}} & q_prev_q_11[i+2]);
|
||||
rem[i+2][i+2:0] =
|
||||
({(i + 3){{quo_iter[i], quo_iter[i+1]} == 2'b00}} & rem_prev_q_00[i+2][i+2:0])
|
||||
| ({(i + 3){{quo_iter[i], quo_iter[i+1]} == 2'b01}} & rem_prev_q_01[i+2][i+2:0])
|
||||
| ({(i + 3){{quo_iter[i], quo_iter[i+1]} == 2'b10}} & rem_prev_q_10[i+2][i+2:0])
|
||||
| ({(i + 3){{quo_iter[i], quo_iter[i+1]} == 2'b11}} & rem_prev_q_11[i+2][i+2:0]);
|
||||
end
|
||||
end
|
||||
|
||||
// stage[63]
|
||||
assign {rem_cout[63], rem_sum[63][63:0]} =
|
||||
{1'b0, rem[62][62:0], dividend_abs[0]}
|
||||
+ {1'b0, {(64){~divisor_sign}} ^ D[63:0]}
|
||||
+ {64'b0, ~divisor_sign};
|
||||
assign force_q_to_zero[63] = 1'b0;
|
||||
assign quo_iter[63] = rem_cout[63];
|
||||
assign rem[63][63:0] = quo_iter[63] ? rem_sum[63][63:0] : {rem[62], dividend_abs[0]};
|
||||
|
||||
for(i = 0; i < 64; i = i + 1) begin: g_quo_reverse
|
||||
assign final_quo_pre[i] = quo_iter[63 - i];
|
||||
end
|
||||
|
||||
assign final_quo = quo_sign ? -final_quo_pre : final_quo_pre;
|
||||
assign final_rem = rem_sign ? -rem[63] : rem[63];
|
||||
|
||||
assign divisor_is_zero_o = (divisor_i == '0);
|
||||
assign quotient_o = divisor_is_zero_o ? {(64){1'b1}} : final_quo;
|
||||
assign remainder_o = divisor_is_zero_o ? dividend_i : final_rem;
|
||||
|
||||
|
||||
endmodule
|
||||
|
|
@ -0,0 +1,5 @@
|
|||
+incdir+../rtl
|
||||
|
||||
../rtl/int64_div_cla3.sv
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,32 @@
|
|||
quit -sim
|
||||
|
||||
file mkdir ./lib
|
||||
file mkdir ./lib/work
|
||||
file mkdir ./log
|
||||
file mkdir ./wave
|
||||
|
||||
vlib ./lib
|
||||
vlib ./lib/work
|
||||
|
||||
vmap work ./lib/work
|
||||
|
||||
vlog -work work -incr -f ../tb/tb.lst
|
||||
|
||||
vsim -c -l ./log/tb_top.log -wlf ./wave/tb_top.wlf -voptargs=+acc -sv_seed 38 work.tb_top
|
||||
|
||||
|
||||
# 0: full names
|
||||
# 1: leaf names
|
||||
configure wave -signalnamewidth 1
|
||||
configure wave -timelineunits ns
|
||||
|
||||
# wave files for WIDTH = 64
|
||||
#do wave_64.do
|
||||
|
||||
# wave files for WIDTH = 32
|
||||
#do wave_32.do
|
||||
|
||||
# wave files for WIDTH = 16
|
||||
#do wave_16.do
|
||||
|
||||
run -all
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
add wave -position insertpoint -expand -group CLK_RST sim:/tb_top/clk
|
||||
add wave -position insertpoint -expand -group CLK_RST sim:/tb_top/rst_n
|
||||
|
||||
add wave -position insertpoint -expand -group STATE -radix unsigned sim:/tb_top/acq_count
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/stim_end
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/dut_start_valid
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/dut_start_ready
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/dut_finish_valid
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/dut_finish_ready
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/compare_ok
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/quotient_16
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/remainder_16
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/g_dut_16/u_dut/final_quo
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/g_dut_16/u_dut/final_rem
|
||||
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_16/u_dut/op_sign_i
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_16/u_dut/dividend_i
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_16/u_dut/divisor_i
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_16/u_dut/dividend_sign
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_16/u_dut/divisor_sign
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_16/u_dut/quo_sign
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_16/u_dut/rem_sign
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_16/u_dut/dividend_abs
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_16/u_dut/dividend_adjusted
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_16/u_dut/divisor_adjusted
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_16/u_dut/D_times_3
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_16/u_dut/D_times_5
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_16/u_dut/D_times_7
|
||||
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/D_msb_to_lsb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/D_lsb_to_msb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/D_times_3_msb_to_lsb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/D_times_3_lsb_to_msb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/D_times_5_msb_to_lsb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/D_times_5_lsb_to_msb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/D_times_7_msb_to_lsb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/D_times_7_lsb_to_msb_flag
|
||||
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/force_q_to_zero
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/force_q_to_zero_prev_q_0
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/force_q_to_zero_prev_q_1
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/force_q_to_zero_prev_q_00
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/force_q_to_zero_prev_q_01
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/force_q_to_zero_prev_q_10
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/force_q_to_zero_prev_q_11
|
||||
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/rem
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/rem_sum
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/rem_sum_prev_q_0
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/rem_sum_prev_q_1
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/rem_sum_prev_q_00
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/rem_sum_prev_q_01
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/rem_sum_prev_q_10
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/rem_sum_prev_q_11
|
||||
|
||||
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/rem_cout
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/rem_cout_prev_q_0
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/rem_cout_prev_q_1
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/rem_cout_prev_q_00
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/rem_cout_prev_q_01
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/rem_cout_prev_q_10
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/rem_cout_prev_q_11
|
||||
|
||||
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/quo_iter
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/q_prev_q_0
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/q_prev_q_1
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/q_prev_q_00
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/q_prev_q_01
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/q_prev_q_10
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_16/u_dut/q_prev_q_11
|
||||
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
add wave -position insertpoint -expand -group CLK_RST sim:/tb_top/clk
|
||||
add wave -position insertpoint -expand -group CLK_RST sim:/tb_top/rst_n
|
||||
|
||||
add wave -position insertpoint -expand -group STATE -radix unsigned sim:/tb_top/acq_count
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/stim_end
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/dut_start_valid
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/dut_start_ready
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/dut_finish_valid
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/dut_finish_ready
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/compare_ok
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/quotient_32
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/remainder_32
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/g_dut_32/u_dut/final_quo
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/g_dut_32/u_dut/final_rem
|
||||
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_32/u_dut/op_sign_i
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_32/u_dut/dividend_i
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_32/u_dut/divisor_i
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_32/u_dut/dividend_sign
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_32/u_dut/divisor_sign
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_32/u_dut/quo_sign
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_32/u_dut/rem_sign
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_32/u_dut/dividend_abs
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_32/u_dut/dividend_adjusted
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_32/u_dut/divisor_adjusted
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_32/u_dut/D_times_3
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_32/u_dut/D_times_5
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_32/u_dut/D_times_7
|
||||
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/D_msb_to_lsb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/D_lsb_to_msb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/D_times_3_msb_to_lsb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/D_times_3_lsb_to_msb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/D_times_5_msb_to_lsb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/D_times_5_lsb_to_msb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/D_times_7_msb_to_lsb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/D_times_7_lsb_to_msb_flag
|
||||
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/force_q_to_zero
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/force_q_to_zero_prev_q_0
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/force_q_to_zero_prev_q_1
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/force_q_to_zero_prev_q_00
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/force_q_to_zero_prev_q_01
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/force_q_to_zero_prev_q_10
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/force_q_to_zero_prev_q_11
|
||||
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/rem
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/rem_sum
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/rem_sum_prev_q_0
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/rem_sum_prev_q_1
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/rem_sum_prev_q_00
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/rem_sum_prev_q_01
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/rem_sum_prev_q_10
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/rem_sum_prev_q_11
|
||||
|
||||
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/rem_cout
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/rem_cout_prev_q_0
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/rem_cout_prev_q_1
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/rem_cout_prev_q_00
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/rem_cout_prev_q_01
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/rem_cout_prev_q_10
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/rem_cout_prev_q_11
|
||||
|
||||
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/quo_iter
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/q_prev_q_0
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/q_prev_q_1
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/q_prev_q_00
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/q_prev_q_01
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/q_prev_q_10
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_32/u_dut/q_prev_q_11
|
||||
|
||||
|
|
@ -0,0 +1,73 @@
|
|||
add wave -position insertpoint -expand -group CLK_RST sim:/tb_top/clk
|
||||
add wave -position insertpoint -expand -group CLK_RST sim:/tb_top/rst_n
|
||||
|
||||
add wave -position insertpoint -expand -group STATE -radix unsigned sim:/tb_top/acq_count
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/stim_end
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/dut_start_valid
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/dut_start_ready
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/dut_finish_valid
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/dut_finish_ready
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/compare_ok
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/quotient_64
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/remainder_64
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/g_dut_64/u_dut/final_quo
|
||||
add wave -position insertpoint -expand -group STATE sim:/tb_top/g_dut_64/u_dut/final_rem
|
||||
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_64/u_dut/op_sign_i
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_64/u_dut/dividend_i
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_64/u_dut/divisor_i
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_64/u_dut/dividend_sign
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_64/u_dut/divisor_sign
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_64/u_dut/quo_sign
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_64/u_dut/rem_sign
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_64/u_dut/dividend_abs
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_64/u_dut/dividend_adjusted
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_64/u_dut/divisor_adjusted
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_64/u_dut/D_times_3
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_64/u_dut/D_times_5
|
||||
add wave -position insertpoint -expand -group MAIN_SIGNALS sim:/tb_top/g_dut_64/u_dut/D_times_7
|
||||
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/D_msb_to_lsb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/D_lsb_to_msb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/D_times_3_msb_to_lsb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/D_times_3_lsb_to_msb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/D_times_5_msb_to_lsb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/D_times_5_lsb_to_msb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/D_times_7_msb_to_lsb_flag
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/D_times_7_lsb_to_msb_flag
|
||||
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/force_q_to_zero
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/force_q_to_zero_prev_q_0
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/force_q_to_zero_prev_q_1
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/force_q_to_zero_prev_q_00
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/force_q_to_zero_prev_q_01
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/force_q_to_zero_prev_q_10
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/force_q_to_zero_prev_q_11
|
||||
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/rem
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/rem_sum
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/rem_sum_prev_q_0
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/rem_sum_prev_q_1
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/rem_sum_prev_q_00
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/rem_sum_prev_q_01
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/rem_sum_prev_q_10
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/rem_sum_prev_q_11
|
||||
|
||||
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/rem_cout
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/rem_cout_prev_q_0
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/rem_cout_prev_q_1
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/rem_cout_prev_q_00
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/rem_cout_prev_q_01
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/rem_cout_prev_q_10
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/rem_cout_prev_q_11
|
||||
|
||||
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/quo_iter
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/q_prev_q_0
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/q_prev_q_1
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/q_prev_q_00
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/q_prev_q_01
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/q_prev_q_10
|
||||
add wave -position insertpoint -expand -group DATA_PATH sim:/tb_top/g_dut_64/u_dut/q_prev_q_11
|
||||
|
||||
|
|
@ -0,0 +1,9 @@
|
|||
+incdir+../tb
|
||||
|
||||
# RTL
|
||||
-f ../rtl/rtl.lst
|
||||
|
||||
|
||||
# TB file
|
||||
../tb/tb_top.sv
|
||||
|
||||
|
|
@ -0,0 +1,115 @@
|
|||
// ========================================================================================================
|
||||
// File Name : tb_defines.svh
|
||||
// Author : HYF
|
||||
// How to Contact : hyf_sysu@qq.com
|
||||
// Created Time : 2021-07-23 10:08:49
|
||||
// Last Modified Time : 2021-09-20 10:17:55
|
||||
// ========================================================================================================
|
||||
// Description :
|
||||
// Some common definitions for Testbench.
|
||||
// ========================================================================================================
|
||||
// ========================================================================================================
|
||||
// Copyright (C) 2021, HYF. All Rights Reserved.
|
||||
// ========================================================================================================
|
||||
// This file is licensed under BSD 3-Clause License.
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
//
|
||||
// 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
// conditions and the following disclaimer.
|
||||
//
|
||||
// 2. Redistributions in binary form must reproduce the above copyright notice, this list of
|
||||
// conditions and the following disclaimer in the documentation and/or other materials provided
|
||||
// with the distribution.
|
||||
//
|
||||
// 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
// to endorse or promote products derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
|
||||
// THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ========================================================================================================
|
||||
|
||||
|
||||
`timescale 1ns/100ps
|
||||
|
||||
`define CLK_HI 5
|
||||
`define CLK_LO 5
|
||||
`define CLK_PERIOD (`CLK_HI + `CLK_LO)
|
||||
// set stimuli application delay
|
||||
`define APPL_DELAY 3
|
||||
// set response aquisition delay
|
||||
`define RESP_DELAY 7
|
||||
|
||||
`define SHORT_DELAY 3
|
||||
`define MIDDLE_DELAY 7
|
||||
`define LONG_DELAY 15
|
||||
|
||||
`ifdef USE_LONG_DELAY
|
||||
`define VALID_READY_DELAY `LONG_DELAY
|
||||
`elsif USE_MIDDLE_DELAY
|
||||
`define VALID_READY_DELAY `MIDDLE_DELAY
|
||||
`elsif USE_SHORT_DELAY
|
||||
`define VALID_READY_DELAY `SHORT_DELAY
|
||||
`else
|
||||
`define VALID_READY_DELAY 1
|
||||
`endif
|
||||
|
||||
|
||||
|
||||
`define WAIT_CYC(CLK, N) \
|
||||
repeat(N) @(posedge CLK);
|
||||
|
||||
`define APPL_WAIT_CYC(CLK, N) \
|
||||
repeat(N) @(posedge CLK); \
|
||||
#(`APPL_DELAY);
|
||||
|
||||
`define RESP_WAIT_CYC(CLK, N) \
|
||||
repeat(N) @(posedge CLK); \
|
||||
#(`RESP_DELAY);
|
||||
|
||||
`define WAIT_SIG(CLK, SIG) \
|
||||
do begin \
|
||||
@(posedge CLK); \
|
||||
end while(SIG == 1'b0);
|
||||
|
||||
`define WAIT_COMB_SIG(CLK, SIG) \
|
||||
while(SIG == 1'b0) begin \
|
||||
@(posedge CLK); \
|
||||
end
|
||||
|
||||
`define APPL_WAIT_COMB_SIG(CLK, SIG) \
|
||||
#(`APPL_DELAY); \
|
||||
while(SIG == 1'b0) begin \
|
||||
@(posedge CLK); \
|
||||
#(`APPL_DELAY); \
|
||||
end
|
||||
|
||||
`define APPL_WAIT_SIG(CLK, SIG) \
|
||||
do begin \
|
||||
@(posedge CLK); \
|
||||
#(`APPL_DELAY); \
|
||||
end while(SIG == 1'b0);
|
||||
|
||||
`define RESP_WAIT_COMB_SIG(CLK, SIG) \
|
||||
#(`RESP_DELAY); \
|
||||
while(SIG == 1'b0) begin \
|
||||
@(posedge CLK); \
|
||||
#(`RESP_DELAY); \
|
||||
end
|
||||
|
||||
`define RESP_WAIT_SIG(CLK, SIG) \
|
||||
do begin \
|
||||
@(posedge CLK); \
|
||||
#(`RESP_DELAY); \
|
||||
end while(SIG == 1'b0);
|
||||
|
||||
|
||||
|
|
@ -0,0 +1,146 @@
|
|||
// ========================================================================================================
|
||||
// File Name : tb_stim_signed.svh
|
||||
// Author : HYF
|
||||
// How to Contact : hyf_sysu@qq.com
|
||||
// Created Time : 2021-07-23 10:08:49
|
||||
// Last Modified Time : 2021-10-30 16:18:31
|
||||
// ========================================================================================================
|
||||
// Description :
|
||||
// Stim for signed op.
|
||||
// ========================================================================================================
|
||||
// ========================================================================================================
|
||||
// Copyright (C) 2021, HYF. All Rights Reserved.
|
||||
// ========================================================================================================
|
||||
// This file is licensed under BSD 3-Clause License.
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
//
|
||||
// 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
// conditions and the following disclaimer.
|
||||
//
|
||||
// 2. Redistributions in binary form must reproduce the above copyright notice, this list of
|
||||
// conditions and the following disclaimer in the documentation and/or other materials provided
|
||||
// with the distribution.
|
||||
//
|
||||
// 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
// to endorse or promote products derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
|
||||
// THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ========================================================================================================
|
||||
|
||||
|
||||
opcode = OPCODE_SIGNED;
|
||||
|
||||
dividend_64 = 64'hb338_d6e1_4a76_0a6d;
|
||||
divisor_64 = 64'hffd8_09e6_11a0_22a9;
|
||||
dividend_32 = dividend_64[32-1:0];
|
||||
divisor_32 = divisor_64[32-1:0];
|
||||
dividend_16 = dividend_64[16-1:0];
|
||||
divisor_16 = divisor_64[16-1:0];
|
||||
`SINGLE_STIM
|
||||
|
||||
dividend_64 = 32'h8d201e54;
|
||||
divisor_64 = 32'hfff10513;
|
||||
dividend_32 = dividend_64[32-1:0];
|
||||
divisor_32 = divisor_64[32-1:0];
|
||||
dividend_16 = dividend_64[16-1:0];
|
||||
divisor_16 = divisor_64[16-1:0];
|
||||
`SINGLE_STIM
|
||||
|
||||
dividend_64 = 579274702;
|
||||
divisor_64 = 621799622;
|
||||
dividend_32 = dividend_64[32-1:0];
|
||||
divisor_32 = divisor_64[32-1:0];
|
||||
dividend_16 = dividend_64[16-1:0];
|
||||
divisor_16 = divisor_64[16-1:0];
|
||||
`SINGLE_STIM
|
||||
|
||||
dividend_64 = 995101285;
|
||||
divisor_64 = 822573882;
|
||||
dividend_32 = dividend_64[32-1:0];
|
||||
divisor_32 = divisor_64[32-1:0];
|
||||
dividend_16 = dividend_64[16-1:0];
|
||||
divisor_16 = divisor_64[16-1:0];
|
||||
`SINGLE_STIM
|
||||
|
||||
dividend_64 = -100;
|
||||
divisor_64 = 0;
|
||||
dividend_32 = dividend_64[32-1:0];
|
||||
divisor_32 = divisor_64[32-1:0];
|
||||
dividend_16 = dividend_64[16-1:0];
|
||||
divisor_16 = divisor_64[16-1:0];
|
||||
`SINGLE_STIM
|
||||
|
||||
dividend_64 = -2090966090;
|
||||
divisor_64 = 0;
|
||||
dividend_32 = dividend_64[32-1:0];
|
||||
divisor_32 = divisor_64[32-1:0];
|
||||
dividend_16 = dividend_64[16-1:0];
|
||||
divisor_16 = divisor_64[16-1:0];
|
||||
`SINGLE_STIM
|
||||
|
||||
dividend_64 = INT64_NEG_MIN;
|
||||
divisor_64 = 1;
|
||||
dividend_32 = INT32_NEG_MIN;
|
||||
divisor_32 = 1;
|
||||
dividend_16 = INT16_NEG_MIN;
|
||||
divisor_16 = 1;
|
||||
`SINGLE_STIM
|
||||
|
||||
dividend_64 = INT64_NEG_MIN;
|
||||
divisor_64 = -1;
|
||||
dividend_32 = INT32_NEG_MIN;
|
||||
divisor_32 = -1;
|
||||
dividend_16 = INT16_NEG_MIN;
|
||||
divisor_16 = -1;
|
||||
`SINGLE_STIM
|
||||
|
||||
for(i = 0; i < SIGNED_RANDOM_TEST_NUM; i++) begin
|
||||
// Make sure divisor_lzc >= dividend_lzc, so "ITER" is always needed.
|
||||
dividend_64_lzc = $urandom() % 64;
|
||||
dividend_32_lzc = $urandom() % 32;
|
||||
dividend_16_lzc = $urandom() % 16;
|
||||
divisor_64_lzc = ($urandom() % (64 - dividend_64_lzc)) + dividend_64_lzc;
|
||||
divisor_32_lzc = ($urandom() % (32 - dividend_32_lzc)) + dividend_32_lzc;
|
||||
divisor_16_lzc = ($urandom() % (16 - dividend_16_lzc)) + dividend_16_lzc;
|
||||
|
||||
std::randomize(dividend_64);
|
||||
dividend_64[63] = 1'b1;
|
||||
dividend_64 = dividend_64 >> dividend_64_lzc;
|
||||
// sign of dividend is random
|
||||
dividend_64[63] = dividend_64[0];
|
||||
std::randomize(divisor_64);
|
||||
divisor_64[63] = 1'b1;
|
||||
divisor_64 = divisor_64 >> divisor_64_lzc;
|
||||
// sign of divisor is random
|
||||
divisor_64[63] = divisor_64[0];
|
||||
|
||||
std::randomize(dividend_32);
|
||||
dividend_32[31] = 1'b1;
|
||||
dividend_32 = dividend_32 >> dividend_32_lzc;
|
||||
dividend_32[31] = dividend_32[0];
|
||||
std::randomize(divisor_32);
|
||||
divisor_32[31] = 1'b1;
|
||||
divisor_32 = divisor_32 >> divisor_32_lzc;
|
||||
divisor_32[31] = divisor_32[0];
|
||||
|
||||
std::randomize(dividend_16);
|
||||
dividend_16[15] = 1'b1;
|
||||
dividend_16 = dividend_16 >> dividend_16_lzc;
|
||||
dividend_16[15] = dividend_16[0];
|
||||
std::randomize(divisor_16);
|
||||
divisor_16[15] = 1'b1;
|
||||
divisor_16 = divisor_16 >> divisor_16_lzc;
|
||||
divisor_16[15] = divisor_16[0];
|
||||
`SINGLE_STIM
|
||||
end
|
||||
|
|
@ -0,0 +1,146 @@
|
|||
// ========================================================================================================
|
||||
// File Name : tb_stim_unsigned.svh
|
||||
// Author : HYF
|
||||
// How to Contact : hyf_sysu@qq.com
|
||||
// Created Time : 2021-07-23 10:08:49
|
||||
// Last Modified Time : 2021-11-01 15:41:50
|
||||
// ========================================================================================================
|
||||
// Description :
|
||||
// Stim for unsigned op.
|
||||
// ========================================================================================================
|
||||
// ========================================================================================================
|
||||
// Copyright (C) 2021, HYF. All Rights Reserved.
|
||||
// ========================================================================================================
|
||||
// This file is licensed under BSD 3-Clause License.
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
//
|
||||
// 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
// conditions and the following disclaimer.
|
||||
//
|
||||
// 2. Redistributions in binary form must reproduce the above copyright notice, this list of
|
||||
// conditions and the following disclaimer in the documentation and/or other materials provided
|
||||
// with the distribution.
|
||||
//
|
||||
// 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
// to endorse or promote products derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
|
||||
// THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ========================================================================================================
|
||||
|
||||
|
||||
opcode = OPCODE_UNSIGNED;
|
||||
|
||||
dividend_64 = 4252788467;
|
||||
divisor_64 = 9801;
|
||||
dividend_32 = dividend_64[32-1:0];
|
||||
divisor_32 = divisor_64[32-1:0];
|
||||
dividend_16 = dividend_64[16-1:0];
|
||||
divisor_16 = divisor_64[16-1:0];
|
||||
`SINGLE_STIM
|
||||
|
||||
dividend_64 = 2371643017;
|
||||
divisor_64 = 3;
|
||||
dividend_32 = dividend_64[32-1:0];
|
||||
divisor_32 = divisor_64[32-1:0];
|
||||
dividend_16 = dividend_64[16-1:0];
|
||||
divisor_16 = divisor_64[16-1:0];
|
||||
`SINGLE_STIM
|
||||
|
||||
dividend_64 = 4252788467;
|
||||
divisor_64 = 9801;
|
||||
dividend_32 = dividend_64[32-1:0];
|
||||
divisor_32 = divisor_64[32-1:0];
|
||||
dividend_16 = dividend_64[16-1:0];
|
||||
divisor_16 = divisor_64[16-1:0];
|
||||
`SINGLE_STIM
|
||||
|
||||
dividend_64 = 32'h1e6ab018;
|
||||
divisor_64 = 32'h0000067f;
|
||||
dividend_32 = dividend_64[32-1:0];
|
||||
divisor_32 = divisor_64[32-1:0];
|
||||
dividend_16 = dividend_64[16-1:0];
|
||||
divisor_16 = divisor_64[16-1:0];
|
||||
`SINGLE_STIM
|
||||
|
||||
dividend_64 = 32'h3b92b337;
|
||||
divisor_64 = 32'h0000067f;
|
||||
dividend_32 = dividend_64[32-1:0];
|
||||
divisor_32 = divisor_64[32-1:0];
|
||||
dividend_16 = dividend_64[16-1:0];
|
||||
divisor_16 = divisor_64[16-1:0];
|
||||
`SINGLE_STIM
|
||||
|
||||
dividend_64 = UINT64_POS_MAX;
|
||||
divisor_64 = 10;
|
||||
dividend_32 = UINT32_POS_MAX;
|
||||
divisor_32 = 9090;
|
||||
dividend_16 = UINT16_POS_MAX;
|
||||
divisor_16 = 60012;
|
||||
`SINGLE_STIM
|
||||
|
||||
dividend_64 = 100;
|
||||
divisor_64 = 0;
|
||||
dividend_32 = dividend_64[32-1:0];
|
||||
divisor_32 = divisor_64[32-1:0];
|
||||
dividend_16 = dividend_64[16-1:0];
|
||||
divisor_16 = divisor_64[16-1:0];
|
||||
`SINGLE_STIM
|
||||
|
||||
dividend_64 = 1;
|
||||
divisor_64 = UINT64_POS_MAX;
|
||||
dividend_32 = 1;
|
||||
divisor_32 = UINT32_POS_MAX;
|
||||
dividend_16 = 1;
|
||||
divisor_16 = UINT16_POS_MAX;
|
||||
`SINGLE_STIM
|
||||
|
||||
dividend_64 = 0;
|
||||
divisor_64 = 0;
|
||||
dividend_32 = 0;
|
||||
divisor_32 = 0;
|
||||
dividend_16 = 0;
|
||||
divisor_16 = 0;
|
||||
`SINGLE_STIM
|
||||
|
||||
for(i = 0; i < UNSIGNED_RANDOM_TEST_NUM; i++) begin
|
||||
// Make sure divisor_lzc >= dividend_lzc, so "ITER" is always needed.
|
||||
dividend_64_lzc = $urandom() % 64;
|
||||
dividend_32_lzc = $urandom() % 32;
|
||||
dividend_16_lzc = $urandom() % 16;
|
||||
divisor_64_lzc = ($urandom() % (64 - dividend_64_lzc)) + dividend_64_lzc;
|
||||
divisor_32_lzc = ($urandom() % (32 - dividend_32_lzc)) + dividend_32_lzc;
|
||||
divisor_16_lzc = ($urandom() % (16 - dividend_16_lzc)) + dividend_16_lzc;
|
||||
|
||||
std::randomize(dividend_64);
|
||||
dividend_64[63] = 1'b1;
|
||||
dividend_64 = dividend_64 >> dividend_64_lzc;
|
||||
std::randomize(divisor_64);
|
||||
divisor_64[63] = 1'b1;
|
||||
divisor_64 = divisor_64 >> divisor_64_lzc;
|
||||
|
||||
std::randomize(dividend_32);
|
||||
dividend_32[31] = 1'b1;
|
||||
dividend_32 = dividend_32 >> dividend_32_lzc;
|
||||
std::randomize(divisor_32);
|
||||
divisor_32[31] = 1'b1;
|
||||
divisor_32 = divisor_32 >> divisor_32_lzc;
|
||||
|
||||
std::randomize(dividend_16);
|
||||
dividend_16[15] = 1'b1;
|
||||
dividend_16 = dividend_16 >> dividend_16_lzc;
|
||||
std::randomize(divisor_16);
|
||||
divisor_16[15] = 1'b1;
|
||||
divisor_16 = divisor_16 >> divisor_16_lzc;
|
||||
`SINGLE_STIM
|
||||
end
|
||||
|
|
@ -0,0 +1,496 @@
|
|||
// ========================================================================================================
|
||||
// File Name : tb_top.sv
|
||||
// Author : HYF
|
||||
// How to Contact : hyf_sysu@qq.com
|
||||
// Created Time : 2021-07-23 10:08:49
|
||||
// Last Modified Time : 2021-11-01 17:33:26
|
||||
// ========================================================================================================
|
||||
// Description :
|
||||
// TB for Radix-8 restoring interger division algorithm.
|
||||
// ========================================================================================================
|
||||
// ========================================================================================================
|
||||
// Copyright (C) 2021, HYF. All Rights Reserved.
|
||||
// ========================================================================================================
|
||||
// This file is licensed under BSD 3-Clause License.
|
||||
// Redistribution and use in source and binary forms, with or without
|
||||
// modification, are permitted provided that the following conditions are met:
|
||||
// Redistribution and use in source and binary forms, with or without modification,
|
||||
// are permitted provided that the following conditions are met:
|
||||
//
|
||||
// 1. Redistributions of source code must retain the above copyright notice, this list of
|
||||
// conditions and the following disclaimer.
|
||||
//
|
||||
// 2. Redistributions in binary form must reproduce the above copyright notice, this list of
|
||||
// conditions and the following disclaimer in the documentation and/or other materials provided
|
||||
// with the distribution.
|
||||
//
|
||||
// 3. Neither the name of the copyright holder nor the names of its contributors may be used
|
||||
// to endorse or promote products derived from this software without specific prior written permission.
|
||||
//
|
||||
// THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS" AND
|
||||
// ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES
|
||||
// OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE DISCLAIMED. IN NO EVENT SHALL
|
||||
// THE COPYRIGHT HOLDER OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL,
|
||||
// EXEMPLARY, OR CONSEQUENTIAL DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE
|
||||
// GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER CAUSED AND
|
||||
// ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT
|
||||
// (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE USE OF THIS SOFTWARE,
|
||||
// EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
|
||||
// ========================================================================================================
|
||||
|
||||
// include some definitions here
|
||||
`define MAX_ERR_COUNT 5
|
||||
// `define USE_SHORT_DELAY
|
||||
`include "tb_defines.svh"
|
||||
// If DUT doesn't have valid-ready control logic itself, don't use this definition.
|
||||
// `define DUT_HAS_VALID_READY
|
||||
|
||||
`define SINGLE_STIM \
|
||||
dut_start_valid = 1; \
|
||||
`WAIT_COMB_SIG(clk, (dut_start_valid & dut_start_ready)) \
|
||||
`APPL_WAIT_CYC(clk, 1) \
|
||||
dut_start_valid = 0; \
|
||||
\
|
||||
`WAIT_SIG(clk, (dut_finish_valid & dut_finish_ready)) \
|
||||
dut_start_valid_after_finish_handshake_delay = $urandom() % `VALID_READY_DELAY; \
|
||||
`APPL_WAIT_CYC(clk, dut_start_valid_after_finish_handshake_delay)
|
||||
|
||||
|
||||
module tb_top #(
|
||||
// Put some parameters here, which can be changed by other modules
|
||||
|
||||
)(
|
||||
);
|
||||
|
||||
// ==================================================================================================================================================
|
||||
// (local) params
|
||||
// ==================================================================================================================================================
|
||||
|
||||
localparam DUT_WIDTH = 32;
|
||||
|
||||
localparam OPCODE_SIGNED = 1'b1;
|
||||
localparam OPCODE_UNSIGNED = 1'b0;
|
||||
|
||||
localparam SIGNED_SINGLE_TEST_NUM = 8;
|
||||
localparam SIGNED_RANDOM_TEST_NUM = 2 ** 24;
|
||||
localparam SIGNED_TEST_NUM = SIGNED_SINGLE_TEST_NUM + SIGNED_RANDOM_TEST_NUM;
|
||||
localparam UNSIGNED_SINGLE_TEST_NUM = 9;
|
||||
localparam UNSIGNED_RANDOM_TEST_NUM = 2 ** 24;
|
||||
localparam UNSIGNED_TEST_NUM = UNSIGNED_SINGLE_TEST_NUM + UNSIGNED_RANDOM_TEST_NUM;
|
||||
|
||||
localparam TEST_NUM = SIGNED_TEST_NUM + UNSIGNED_TEST_NUM;
|
||||
|
||||
localparam UINT64_POS_MAX = {(64){1'b1}};
|
||||
localparam INT64_POS_MAX = {1'b0, {(63){1'b1}}};
|
||||
localparam INT64_NEG_MIN = {1'b1, {(63){1'b0}}};
|
||||
localparam INT64_NEG_ONE = {(64){1'b1}};
|
||||
|
||||
localparam UINT32_POS_MAX = {(32){1'b1}};
|
||||
localparam INT32_POS_MAX = {1'b0, {(31){1'b1}}};
|
||||
localparam INT32_NEG_MIN = {1'b1, {(31){1'b0}}};
|
||||
localparam INT32_NEG_ONE = {(32){1'b1}};
|
||||
|
||||
localparam UINT16_POS_MAX = {(16){1'b1}};
|
||||
localparam INT16_POS_MAX = {1'b0, {(15){1'b1}}};
|
||||
localparam INT16_NEG_MIN = {1'b1, {(15){1'b0}}};
|
||||
localparam INT16_NEG_ONE = {(16){1'b1}};
|
||||
|
||||
// ==================================================================================================================================================
|
||||
// functions
|
||||
// ==================================================================================================================================================
|
||||
|
||||
|
||||
|
||||
// ==================================================================================================================================================
|
||||
// signals
|
||||
// ==================================================================================================================================================
|
||||
|
||||
// common signals
|
||||
logic clk;
|
||||
logic rst_n;
|
||||
int i;
|
||||
logic simulation_start;
|
||||
logic stim_end;
|
||||
logic acq_trig;
|
||||
logic [31:0] acq_count;
|
||||
logic [31:0] err_count;
|
||||
int fptr;
|
||||
|
||||
logic compare_ok;
|
||||
logic dut_start_valid;
|
||||
logic dut_start_ready;
|
||||
logic dut_finish_valid;
|
||||
logic dut_finish_ready;
|
||||
// tb向dut发送的后一个start_valid和前一个finish_handshake之间的延迟
|
||||
logic [31:0] dut_start_valid_after_finish_handshake_delay;
|
||||
// tb向dut发送了start_valid之后，dut向tb发送start_ready之间的延迟
|
||||
logic [31:0] dut_start_ready_after_start_valid_delay;
|
||||
// tb发送到dut的finish_ready和dut发送到tb中的finish_valid之间的延迟
|
||||
logic [31:0] dut_finish_ready_after_finish_valid_delay;
|
||||
// start_valid = 1之后，dut向tb发送的finish_valid之间的延迟
|
||||
logic [31:0] dut_finish_valid_after_start_handshake_delay;
|
||||
|
||||
|
||||
// signals related with DUT.
|
||||
logic [1-1:0] opcode;
|
||||
logic [64-1:0] dividend_64;
|
||||
logic [64-1:0] dividend_abs_64;
|
||||
logic [64-1:0] divisor_64;
|
||||
logic [64-1:0] divisor_abs_64;
|
||||
|
||||
logic [32-1:0] dividend_32;
|
||||
logic [32-1:0] dividend_abs_32;
|
||||
logic [32-1:0] divisor_32;
|
||||
logic [32-1:0] divisor_abs_32;
|
||||
|
||||
logic [16-1:0] dividend_16;
|
||||
logic [16-1:0] dividend_abs_16;
|
||||
logic [16-1:0] divisor_16;
|
||||
logic [16-1:0] divisor_abs_16;
|
||||
|
||||
logic [5:0] dividend_64_lzc;
|
||||
logic [4:0] dividend_32_lzc;
|
||||
logic [3:0] dividend_16_lzc;
|
||||
|
||||
logic [5:0] divisor_64_lzc;
|
||||
logic [4:0] divisor_32_lzc;
|
||||
logic [3:0] divisor_16_lzc;
|
||||
|
||||
logic neg_quotient_64;
|
||||
logic neg_remainder_64;
|
||||
logic neg_quotient_32;
|
||||
logic neg_remainder_32;
|
||||
logic neg_quotient_16;
|
||||
logic neg_remainder_16;
|
||||
logic [64-1:0] quotient_64;
|
||||
logic [64-1:0] remainder_64;
|
||||
logic [32-1:0] quotient_32;
|
||||
logic [32-1:0] remainder_32;
|
||||
logic [16-1:0] quotient_16;
|
||||
logic [16-1:0] remainder_16;
|
||||
logic divisor_is_zero_64;
|
||||
logic divisor_is_zero_32;
|
||||
logic divisor_is_zero_16;
|
||||
|
||||
logic [64-1:0] dut_quotient_64;
|
||||
logic [64-1:0] dut_remainder_64;
|
||||
logic [32-1:0] dut_quotient_32;
|
||||
logic [32-1:0] dut_remainder_32;
|
||||
logic [16-1:0] dut_quotient_16;
|
||||
logic [16-1:0] dut_remainder_16;
|
||||
logic dut_divisor_is_zero_64;
|
||||
logic dut_divisor_is_zero_32;
|
||||
logic dut_divisor_is_zero_16;
|
||||
logic [96-1:0] unused_bits;
|
||||
|
||||
// ==================================================================================================================================================
|
||||
// main codes
|
||||
// ==================================================================================================================================================
|
||||
|
||||
|
||||
|
||||
// ================================================================================================================================================
|
||||
// application process
|
||||
|
||||
initial begin
|
||||
dividend_64 = 0;
|
||||
divisor_64 = 0;
|
||||
dividend_32 = 0;
|
||||
divisor_32 = 0;
|
||||
dividend_32 = 0;
|
||||
divisor_32 = 0;
|
||||
opcode = OPCODE_SIGNED;
|
||||
dut_start_valid = 0;
|
||||
acq_trig = 0;
|
||||
stim_end = 0;
|
||||
|
||||
`APPL_WAIT_SIG(clk, simulation_start)
|
||||
$display("TB: stimuli application starts!");
|
||||
|
||||
acq_trig = 1;
|
||||
`APPL_WAIT_CYC(clk, 2)
|
||||
acq_trig = 0;
|
||||
|
||||
`include "tb_stim_unsigned.svh"
|
||||
`include "tb_stim_signed.svh"
|
||||
|
||||
|
||||
`WAIT_CYC(clk, 20)
|
||||
stim_end = 1;
|
||||
end
|
||||
|
||||
// ================================================================================================================================================
|
||||
|
||||
// ================================================================================================================================================
|
||||
// acquisition process
|
||||
|
||||
initial begin
|
||||
dut_finish_ready = 0;
|
||||
fptr = $fopen("result.txt", "w+");
|
||||
$display("TB: response acquisition starts!");
|
||||
|
||||
// wait for acquisition trigger
|
||||
do begin
|
||||
`RESP_WAIT_CYC(clk, 1)
|
||||
if(stim_end == 1)
|
||||
begin
|
||||
$display("response acquisition finishes!");
|
||||
$display("TB finishes!");
|
||||
$fclose(fptr);
|
||||
$stop();
|
||||
end
|
||||
end while(acq_trig == 1'b0);
|
||||
|
||||
acq_count = 0;
|
||||
err_count = 0;
|
||||
|
||||
do begin
|
||||
`WAIT_COMB_SIG(clk, dut_start_valid)
|
||||
`WAIT_COMB_SIG(clk, dut_finish_valid)
|
||||
dut_finish_ready_after_finish_valid_delay = $urandom() % `VALID_READY_DELAY;
|
||||
`RESP_WAIT_CYC(clk, dut_finish_ready_after_finish_valid_delay)
|
||||
dut_finish_ready = 1;
|
||||
|
||||
if((compare_ok == 0) | (compare_ok == 1'bX)) begin
|
||||
$display("ERROR FOUND:");
|
||||
if(DUT_WIDTH == 64) begin
|
||||
$fdisplay(fptr, "------------------------------------------------------------------------------------");
|
||||
$fdisplay(fptr, "ERROR FOUND:");
|
||||
$fdisplay(fptr, "dividend = %h, divisor = %h", dividend_64, divisor_64);
|
||||
$fdisplay(fptr, "opcode = %b", opcode);
|
||||
$fdisplay(fptr, "exp_quotient = %h, exp_remainder = %h, act_quotient = %h, act_remainder = %h", quotient_64, remainder_64, dut_quotient_64, dut_remainder_64);
|
||||
$fdisplay(fptr, "exp_divisor_is_zero = %b, dut_divisor_is_zero = %b", divisor_is_zero_64, dut_divisor_is_zero_64);
|
||||
end
|
||||
else if(DUT_WIDTH == 32) begin
|
||||
$fdisplay(fptr, "------------------------------------------------------------------------------------");
|
||||
$fdisplay(fptr, "ERROR FOUND:");
|
||||
$fdisplay(fptr, "dividend = %h, divisor = %h", dividend_32, divisor_32);
|
||||
$fdisplay(fptr, "opcode = %b", opcode);
|
||||
$fdisplay(fptr, "exp_quotient = %h, exp_remainder = %h, act_quotient = %h, act_remainder = %h", quotient_32, remainder_32, dut_quotient_32, dut_remainder_32);
|
||||
$fdisplay(fptr, "exp_divisor_is_zero = %b, dut_divisor_is_zero = %b", divisor_is_zero_32, dut_divisor_is_zero_32);
|
||||
end
|
||||
else begin
|
||||
$fdisplay(fptr, "------------------------------------------------------------------------------------");
|
||||
$fdisplay(fptr, "ERROR FOUND:");
|
||||
$fdisplay(fptr, "dividend = %h, divisor = %h", dividend_16, divisor_16);
|
||||
$fdisplay(fptr, "opcode = %b", opcode);
|
||||
$fdisplay(fptr, "exp_quotient = %h, exp_remainder = %h, act_quotient = %h, act_remainder = %h", quotient_16, remainder_16, dut_quotient_16, dut_remainder_16);
|
||||
$fdisplay(fptr, "exp_divisor_is_zero = %b, dut_divisor_is_zero = %b", divisor_is_zero_16, dut_divisor_is_zero_16);
|
||||
end
|
||||
|
||||
err_count++;
|
||||
end
|
||||
|
||||
if(err_count == `MAX_ERR_COUNT) begin
|
||||
$fdisplay(fptr, "finished_test_num = %d, error_test_num = %d", acq_count, err_count);
|
||||
$display("Too many ERRORs, stop simulation!!!");
|
||||
$fclose(fptr);
|
||||
$stop();
|
||||
end
|
||||
|
||||
acq_count++;
|
||||
`RESP_WAIT_SIG(clk, dut_finish_ready)
|
||||
dut_finish_ready = 0;
|
||||
|
||||
if((acq_count != 0) & (acq_count % (2 ** 16) == 0))
|
||||
$display("Simulation is still running !!!");
|
||||
|
||||
end while(acq_count < TEST_NUM);
|
||||
|
||||
`WAIT_SIG(clk, stim_end)
|
||||
`WAIT_CYC(clk, 20)
|
||||
$fdisplay(fptr, "\n");
|
||||
$fdisplay(fptr, "------------------------------------------------------------------------------------");
|
||||
$fdisplay(fptr, "finished_test_num = %d, error_test_num = %d", acq_count, err_count);
|
||||
$display("response acquisition finishes!");
|
||||
$display("TB finishes!");
|
||||
$fclose(fptr);
|
||||
$stop();
|
||||
end
|
||||
|
||||
// ================================================================================================================================================
|
||||
|
||||
// ================================================================================================================================================
|
||||
// calculate expected result
|
||||
|
||||
always_comb begin
|
||||
neg_quotient_64 = (opcode == OPCODE_SIGNED) & (dividend_64[63] ^ divisor_64[63]);
|
||||
neg_remainder_64 = (opcode == OPCODE_SIGNED) & (dividend_64[63]);
|
||||
neg_quotient_32 = (opcode == OPCODE_SIGNED) & (dividend_32[31] ^ divisor_32[31]);
|
||||
neg_remainder_32 = (opcode == OPCODE_SIGNED) & (dividend_32[31]);
|
||||
neg_quotient_16 = (opcode == OPCODE_SIGNED) & (dividend_16[15] ^ divisor_16[15]);
|
||||
neg_remainder_16 = (opcode == OPCODE_SIGNED) & (dividend_16[15]);
|
||||
|
||||
dividend_abs_64 = (dividend_64[63] & (opcode == OPCODE_SIGNED)) ? -dividend_64 : dividend_64;
|
||||
divisor_abs_64 = (divisor_64[63] & (opcode == OPCODE_SIGNED)) ? -divisor_64 : divisor_64;
|
||||
dividend_abs_32 = (dividend_32[31] & (opcode == OPCODE_SIGNED)) ? -dividend_32 : dividend_32;
|
||||
divisor_abs_32 = (divisor_32[31] & (opcode == OPCODE_SIGNED)) ? -divisor_32 : divisor_32;
|
||||
dividend_abs_16 = (dividend_16[15] & (opcode == OPCODE_SIGNED)) ? -dividend_16 : dividend_16;
|
||||
divisor_abs_16 = (divisor_16[15] & (opcode == OPCODE_SIGNED)) ? -divisor_16 : divisor_16;
|
||||
|
||||
quotient_64 = neg_quotient_64 ? -(dividend_abs_64 / divisor_abs_64) : (dividend_abs_64 / divisor_abs_64);
|
||||
remainder_64 = neg_remainder_64 ? -(dividend_abs_64 % divisor_abs_64) : (dividend_abs_64 % divisor_abs_64);
|
||||
quotient_32 = neg_quotient_32 ? -(dividend_abs_32 / divisor_abs_32) : (dividend_abs_32 / divisor_abs_32);
|
||||
remainder_32 = neg_remainder_32 ? -(dividend_abs_32 % divisor_abs_32) : (dividend_abs_32 % divisor_abs_32);
|
||||
quotient_16 = neg_quotient_16 ? -(dividend_abs_16 / divisor_abs_16) : (dividend_abs_16 / divisor_abs_16);
|
||||
remainder_16 = neg_remainder_16 ? -(dividend_abs_16 % divisor_abs_16) : (dividend_abs_16 % divisor_abs_16);
|
||||
|
||||
divisor_is_zero_64 = (divisor_64 == 0);
|
||||
divisor_is_zero_32 = (divisor_32 == 0);
|
||||
divisor_is_zero_16 = (divisor_16 == 0);
|
||||
|
||||
if(opcode == OPCODE_SIGNED) begin
|
||||
if(divisor_64 == 0) begin
|
||||
quotient_64 = UINT64_POS_MAX;
|
||||
remainder_64 = dividend_64;
|
||||
end
|
||||
else if((dividend_64 == INT64_NEG_MIN) & (divisor_64 == INT64_NEG_ONE)) begin
|
||||
quotient_64 = INT64_NEG_MIN;
|
||||
remainder_64 = 0;
|
||||
end
|
||||
|
||||
if(divisor_32 == 0) begin
|
||||
quotient_32 = UINT32_POS_MAX;
|
||||
remainder_32 = dividend_32;
|
||||
end
|
||||
else if((dividend_32 == INT32_NEG_MIN) & (divisor_32 == INT32_NEG_ONE)) begin
|
||||
quotient_32 = INT32_NEG_MIN;
|
||||
remainder_32 = 0;
|
||||
end
|
||||
|
||||
if(divisor_16 == 0) begin
|
||||
quotient_16 = UINT16_POS_MAX;
|
||||
remainder_16 = dividend_16;
|
||||
end
|
||||
else if((dividend_16 == INT16_NEG_MIN) & (divisor_16 == INT16_NEG_ONE)) begin
|
||||
quotient_16 = INT16_NEG_MIN;
|
||||
remainder_16 = 0;
|
||||
end
|
||||
end
|
||||
else begin
|
||||
if(divisor_64 == 0) begin
|
||||
quotient_64 = UINT64_POS_MAX;
|
||||
remainder_64 = dividend_64;
|
||||
end
|
||||
|
||||
if(divisor_32 == 0) begin
|
||||
quotient_32 = UINT32_POS_MAX;
|
||||
remainder_32 = dividend_32;
|
||||
end
|
||||
|
||||
if(divisor_16 == 0) begin
|
||||
quotient_16 = UINT16_POS_MAX;
|
||||
remainder_16 = dividend_16;
|
||||
end
|
||||
end
|
||||
|
||||
if(DUT_WIDTH == 64)
|
||||
compare_ok = (quotient_64 == dut_quotient_64) & (remainder_64 == dut_remainder_64) & (divisor_is_zero_64 == dut_divisor_is_zero_64);
|
||||
else if(DUT_WIDTH == 32)
|
||||
compare_ok = (quotient_32 == dut_quotient_32) & (remainder_32 == dut_remainder_32) & (divisor_is_zero_32 == dut_divisor_is_zero_32);
|
||||
else
|
||||
compare_ok = (quotient_16 == dut_quotient_16) & (remainder_16 == dut_remainder_16) & (divisor_is_zero_16 == dut_divisor_is_zero_16);
|
||||
end
|
||||
|
||||
// ================================================================================================================================================
|
||||
// Instantiate DUT here.
|
||||
|
||||
generate
|
||||
if(DUT_WIDTH == 64) begin: g_dut_64
|
||||
int64_div_cla3
|
||||
u_dut (
|
||||
.op_format_i(2'b10),
|
||||
.op_sign_i(opcode),
|
||||
.dividend_i(dividend_64),
|
||||
.divisor_i(divisor_64),
|
||||
.quotient_o(dut_quotient_64),
|
||||
.remainder_o(dut_remainder_64),
|
||||
.divisor_is_zero_o(dut_divisor_is_zero_64)
|
||||
);
|
||||
end
|
||||
else if(DUT_WIDTH == 32) begin: g_dut_32
|
||||
int64_div_cla3
|
||||
u_dut (
|
||||
.op_format_i(2'b01),
|
||||
.op_sign_i(opcode),
|
||||
.dividend_i({32'b0, dividend_32}),
|
||||
.divisor_i({32'b0, divisor_32}),
|
||||
.quotient_o({unused_bits[31:0], dut_quotient_32}),
|
||||
.remainder_o({unused_bits[63:32], dut_remainder_32}),
|
||||
.divisor_is_zero_o(dut_divisor_is_zero_32)
|
||||
);
|
||||
end
|
||||
else begin: g_dut_16
|
||||
int64_div_cla3
|
||||
u_dut (
|
||||
.op_format_i(2'b00),
|
||||
.op_sign_i(opcode),
|
||||
.dividend_i({48'b0, dividend_16}),
|
||||
.divisor_i({48'b0, divisor_16}),
|
||||
.quotient_o({unused_bits[47:0], dut_quotient_16}),
|
||||
.remainder_o({unused_bits[95:48], dut_remainder_16}),
|
||||
.divisor_is_zero_o(dut_divisor_is_zero_16)
|
||||
);
|
||||
end
|
||||
endgenerate
|
||||
|
||||
|
||||
|
||||
// ================================================================================================================================================
|
||||
// Simulate valid-ready signals of dut
|
||||
|
||||
`ifndef DUT_HAS_VALID_READY
|
||||
initial begin
|
||||
do begin
|
||||
dut_start_ready = 0;
|
||||
`RESP_WAIT_COMB_SIG(clk, dut_start_valid)
|
||||
dut_start_ready_after_start_valid_delay = $urandom() % `VALID_READY_DELAY;
|
||||
`RESP_WAIT_CYC(clk, dut_start_ready_after_start_valid_delay)
|
||||
dut_start_ready = 1;
|
||||
`RESP_WAIT_SIG(clk, dut_start_ready)
|
||||
end while(1);
|
||||
// end while(acq_count < TEST_NUM);
|
||||
end
|
||||
|
||||
initial begin
|
||||
do begin
|
||||
dut_finish_valid = 0;
|
||||
`WAIT_COMB_SIG(clk, (dut_start_valid & dut_start_ready))
|
||||
dut_finish_valid_after_start_handshake_delay = $urandom() % `VALID_READY_DELAY;
|
||||
`APPL_WAIT_CYC(clk, dut_finish_valid_after_start_handshake_delay)
|
||||
dut_finish_valid = 1;
|
||||
`APPL_WAIT_SIG(clk, (dut_finish_valid & dut_finish_ready))
|
||||
end while(1);
|
||||
end
|
||||
`else
|
||||
|
||||
`endif
|
||||
|
||||
// ================================================================================================================================================
|
||||
|
||||
|
||||
// ================================================================================================================================================
|
||||
// clk generator
|
||||
initial begin
|
||||
clk = 0;
|
||||
while(1) begin
|
||||
clk = 0;
|
||||
#(`CLK_LO);
|
||||
clk = 1;
|
||||
#(`CLK_HI);
|
||||
end
|
||||
end
|
||||
// reset and start signal generator
|
||||
initial begin
|
||||
rst_n = 0;
|
||||
simulation_start = 0;
|
||||
`APPL_WAIT_CYC(clk, 5)
|
||||
rst_n = 1;
|
||||
`APPL_WAIT_CYC(clk, 5)
|
||||
$display("TB: simulation starts!");
|
||||
simulation_start <= 1;
|
||||
end
|
||||
// ================================================================================================================================================
|
||||
|
||||
|
||||
endmodule
|
||||
Loading…
Reference in New Issue