1257 lines
123 KiB
Systemverilog
1257 lines
123 KiB
Systemverilog
// Generated by CIRCT firtool-1.61.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module ITTage( // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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input clock,
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input reset,
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input [38:0] io_in_bits_s0_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [7:0] io_in_bits_folded_hist_3_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [8:0] io_in_bits_folded_hist_3_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_folded_hist_3_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [8:0] io_in_bits_folded_hist_3_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [8:0] io_in_bits_folded_hist_3_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [7:0] io_in_bits_folded_hist_3_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [7:0] io_in_bits_folded_hist_3_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [7:0] io_in_bits_folded_hist_3_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [11:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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|
input [19:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
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input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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|
input io_in_bits_resp_in_0_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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|
input io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
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output [38:0] io_out_s2_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
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output [38:0] io_out_s2_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s2_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s2_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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|
output [38:0] io_out_s2_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s2_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s2_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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|
output [38:0] io_out_s2_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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|
output [38:0] io_out_s2_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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|
output [38:0] io_out_s2_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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|
output [3:0] io_out_s2_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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|
output [3:0] io_out_s2_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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|
output [38:0] io_out_s2_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_2_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_0_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_1_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_2_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [218:0] io_out_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s0_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s1_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s2_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s2_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s2_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s2_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [38:0] io_update_bits_pc, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [7:0] io_update_bits_spec_info_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [8:0] io_update_bits_spec_info_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [3:0] io_update_bits_spec_info_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [8:0] io_update_bits_spec_info_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [8:0] io_update_bits_spec_info_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [7:0] io_update_bits_spec_info_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [7:0] io_update_bits_spec_info_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [7:0] io_update_bits_spec_info_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_cfi_idx_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [3:0] io_update_bits_cfi_idx_bits, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_jmp_taken, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_mispred_mask_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [218:0] io_update_bits_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [38:0] io_update_bits_full_target // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
);
|
|
|
|
reg [2:0] resp_meta_allocate_bits_r; // src/main/scala/xiangshan/frontend/ITTAGE.scala:516:40
|
|
reg resp_meta_allocate_valid_r; // src/main/scala/xiangshan/frontend/ITTAGE.scala:515:40
|
|
wire resp_meta_altDiffers; // src/main/scala/xiangshan/frontend/ITTAGE.scala:498:50
|
|
wire _tables_4_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire [1:0] _tables_4_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire [1:0] _tables_4_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire [38:0] _tables_4_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire _tables_3_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire [1:0] _tables_3_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire [1:0] _tables_3_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire [38:0] _tables_3_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire _tables_2_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire [1:0] _tables_2_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire [1:0] _tables_2_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire [38:0] _tables_2_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire _tables_1_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire [1:0] _tables_1_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire [1:0] _tables_1_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire [38:0] _tables_1_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire _tables_0_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire [1:0] _tables_0_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire [1:0] _tables_0_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
wire [38:0] _tables_0_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
reg [7:0] tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24
|
|
reg s2_resps_0_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg [1:0] s2_resps_0_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg [1:0] s2_resps_0_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg [38:0] s2_resps_0_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg s2_resps_1_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg [1:0] s2_resps_1_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg [1:0] s2_resps_1_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg [38:0] s2_resps_1_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg s2_resps_2_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg [1:0] s2_resps_2_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg [1:0] s2_resps_2_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg [38:0] s2_resps_2_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg s2_resps_3_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg [1:0] s2_resps_3_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg [1:0] s2_resps_3_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg [38:0] s2_resps_3_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg s2_resps_4_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg [1:0] s2_resps_4_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg [1:0] s2_resps_4_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg [38:0] s2_resps_4_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27
|
|
reg s3_tageTaken_dup_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59
|
|
reg s3_tageTaken_dup_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59
|
|
reg s3_tageTaken_dup_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59
|
|
reg s3_tageTaken_dup_3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59
|
|
reg [38:0] s3_tageTarget_dup_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59
|
|
reg [38:0] s3_tageTarget_dup_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59
|
|
reg [38:0] s3_tageTarget_dup_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59
|
|
reg [38:0] s3_tageTarget_dup_3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59
|
|
reg [38:0] s3_providerTarget; // src/main/scala/xiangshan/frontend/ITTAGE.scala:396:39
|
|
reg [38:0] s3_altProviderTarget; // src/main/scala/xiangshan/frontend/ITTAGE.scala:397:39
|
|
reg s3_provided; // src/main/scala/xiangshan/frontend/ITTAGE.scala:398:39
|
|
reg [2:0] s3_provider; // src/main/scala/xiangshan/frontend/ITTAGE.scala:399:39
|
|
reg s3_altProvided; // src/main/scala/xiangshan/frontend/ITTAGE.scala:400:39
|
|
reg [2:0] s3_altProvider; // src/main/scala/xiangshan/frontend/ITTAGE.scala:401:39
|
|
reg s3_finalAltPred; // src/main/scala/xiangshan/frontend/ITTAGE.scala:402:39
|
|
reg s3_providerU; // src/main/scala/xiangshan/frontend/ITTAGE.scala:403:39
|
|
reg [1:0] s3_providerCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:404:39
|
|
reg [1:0] s3_altProviderCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:405:39
|
|
wire updateValid =
|
|
io_update_bits_ftb_entry_tailSlot_valid & io_update_bits_ftb_entry_isJalr
|
|
& ~(io_update_bits_ftb_entry_tailSlot_valid & io_update_bits_ftb_entry_isRet)
|
|
& io_update_valid & ~io_update_bits_ftb_entry_tailSlot_sharing
|
|
& io_update_bits_jmp_taken & io_update_bits_cfi_idx_valid
|
|
& io_update_bits_cfi_idx_bits == io_update_bits_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FTB.scala:217:23, src/main/scala/xiangshan/frontend/FrontendBundle.scala:655:41, src/main/scala/xiangshan/frontend/ITTAGE.scala:416:23, :417:{46,69}
|
|
assign resp_meta_altDiffers = s3_finalAltPred != s3_tageTaken_dup_3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59, :402:39, :498:50
|
|
reg [63:0] s2_allocLFSR_lfsr; // utility/src/main/scala/utility/LFSR64.scala:27:33
|
|
wire _GEN =
|
|
updateValid & io_update_bits_mispred_mask_2
|
|
& ~(io_update_bits_meta[96] & io_update_bits_meta[77:39] == io_update_bits_full_target
|
|
& io_update_bits_meta[86:85] == 2'h0); // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :417:46, :421:40, :553:80, :554:47, :555:{38,41,59}
|
|
reg tables_0_io_update_valid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41
|
|
reg tables_0_io_update_correct_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43
|
|
reg [38:0] tables_0_io_update_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42
|
|
reg [38:0] tables_0_io_update_old_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46
|
|
reg tables_0_io_update_alloc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41
|
|
reg [1:0] tables_0_io_update_oldCtr_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42
|
|
reg tables_0_io_update_reset_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43
|
|
reg tables_0_io_update_uValid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42
|
|
reg tables_0_io_update_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37
|
|
reg [38:0] tables_0_io_update_pc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38
|
|
reg [3:0] tables_0_io_update_folded_hist_REG_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
reg tables_1_io_update_valid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41
|
|
reg tables_1_io_update_correct_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43
|
|
reg [38:0] tables_1_io_update_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42
|
|
reg [38:0] tables_1_io_update_old_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46
|
|
reg tables_1_io_update_alloc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41
|
|
reg [1:0] tables_1_io_update_oldCtr_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42
|
|
reg tables_1_io_update_reset_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43
|
|
reg tables_1_io_update_uValid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42
|
|
reg tables_1_io_update_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37
|
|
reg [38:0] tables_1_io_update_pc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38
|
|
reg [7:0] tables_1_io_update_folded_hist_REG_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
reg tables_2_io_update_valid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41
|
|
reg tables_2_io_update_correct_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43
|
|
reg [38:0] tables_2_io_update_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42
|
|
reg [38:0] tables_2_io_update_old_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46
|
|
reg tables_2_io_update_alloc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41
|
|
reg [1:0] tables_2_io_update_oldCtr_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42
|
|
reg tables_2_io_update_reset_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43
|
|
reg tables_2_io_update_uValid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42
|
|
reg tables_2_io_update_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37
|
|
reg [38:0] tables_2_io_update_pc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38
|
|
reg [8:0] tables_2_io_update_folded_hist_REG_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
reg [7:0] tables_2_io_update_folded_hist_REG_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
reg tables_3_io_update_valid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41
|
|
reg tables_3_io_update_correct_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43
|
|
reg [38:0] tables_3_io_update_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42
|
|
reg [38:0] tables_3_io_update_old_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46
|
|
reg tables_3_io_update_alloc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41
|
|
reg [1:0] tables_3_io_update_oldCtr_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42
|
|
reg tables_3_io_update_reset_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43
|
|
reg tables_3_io_update_uValid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42
|
|
reg tables_3_io_update_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37
|
|
reg [38:0] tables_3_io_update_pc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38
|
|
reg [8:0] tables_3_io_update_folded_hist_REG_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
reg [7:0] tables_3_io_update_folded_hist_REG_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
reg tables_4_io_update_valid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41
|
|
reg tables_4_io_update_correct_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43
|
|
reg [38:0] tables_4_io_update_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42
|
|
reg [38:0] tables_4_io_update_old_target_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46
|
|
reg tables_4_io_update_alloc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41
|
|
reg [1:0] tables_4_io_update_oldCtr_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42
|
|
reg tables_4_io_update_reset_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43
|
|
reg tables_4_io_update_uValid_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42
|
|
reg tables_4_io_update_u_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37
|
|
reg [38:0] tables_4_io_update_pc_REG; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38
|
|
reg [8:0] tables_4_io_update_folded_hist_REG_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
reg [7:0] tables_4_io_update_folded_hist_REG_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
tickCtr <= 8'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24
|
|
s2_allocLFSR_lfsr <= 64'h1234567887654321; // utility/src/main/scala/utility/LFSR64.scala:27:33
|
|
end
|
|
else begin
|
|
if (&tickCtr) // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17
|
|
tickCtr <= 8'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24
|
|
else if (_GEN) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:555:38
|
|
if ((&tickCtr) & ~(io_update_bits_meta[82])) // src/main/scala/xiangshan/frontend/BPU.scala:94:27, :96:21, src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :421:40, :557:46
|
|
tickCtr <= 8'hFF; // src/main/scala/xiangshan/frontend/BPU.scala:94:27, src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24
|
|
else if (tickCtr == 8'h0 & io_update_bits_meta[82]) // src/main/scala/xiangshan/frontend/BPU.scala:95:30, :97:26, src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :421:40
|
|
tickCtr <= 8'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24
|
|
else if (io_update_bits_meta[82]) // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40
|
|
tickCtr <= 8'(tickCtr - 8'h1); // src/main/scala/xiangshan/frontend/BPU.scala:98:35, src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24
|
|
else // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40
|
|
tickCtr <= 8'(tickCtr + 8'h1); // src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/BPU.scala:98:24, src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24
|
|
end
|
|
if (s2_allocLFSR_lfsr == 64'h0) // utility/src/main/scala/utility/LFSR64.scala:27:33, :31:24
|
|
s2_allocLFSR_lfsr <= 64'h1; // utility/src/main/scala/utility/LFSR64.scala:27:33, :31:18
|
|
else // utility/src/main/scala/utility/LFSR64.scala:31:24
|
|
s2_allocLFSR_lfsr <=
|
|
{s2_allocLFSR_lfsr[0] ^ s2_allocLFSR_lfsr[1] ^ s2_allocLFSR_lfsr[3]
|
|
^ s2_allocLFSR_lfsr[4],
|
|
s2_allocLFSR_lfsr[63:1]}; // utility/src/main/scala/utility/LFSR64.scala:27:33, :29:{19,29,39,43,49}, :31:{41,51}
|
|
end
|
|
end // always @(posedge, posedge)
|
|
wire [2:0] selectedInfo_res_1_first_tableIdx = {2'h0, s2_resps_1_valid}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :375:27, utility/src/main/scala/utility/ParallelMux.scala:147:10
|
|
wire [2:0] selectedInfo_res_2_first_tableIdx =
|
|
s2_resps_2_valid ? 3'h2 : selectedInfo_res_1_first_tableIdx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, :450:24, utility/src/main/scala/utility/ParallelMux.scala:147:10
|
|
wire selectedInfo_res_hasOne = s2_resps_4_valid | s2_resps_3_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16
|
|
wire selectedInfo_res_hasTwo = s2_resps_4_valid & s2_resps_3_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:146:40
|
|
wire selectedInfo_res_1_hasOne = s2_resps_1_valid | s2_resps_0_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16
|
|
wire [1:0] selectedInfo_res_1_first_ctr =
|
|
s2_resps_1_valid ? s2_resps_1_bits_ctr : s2_resps_0_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:147:10
|
|
wire [38:0] selectedInfo_res_1_first_target =
|
|
s2_resps_1_valid ? s2_resps_1_bits_target : s2_resps_0_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:147:10
|
|
wire selectedInfo_res_2_hasOne = s2_resps_2_valid | selectedInfo_res_1_hasOne; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16
|
|
wire [1:0] selectedInfo_res_2_first_ctr =
|
|
s2_resps_2_valid ? s2_resps_2_bits_ctr : selectedInfo_res_1_first_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:147:10
|
|
wire [38:0] selectedInfo_res_2_first_target =
|
|
s2_resps_2_valid ? s2_resps_2_bits_target : selectedInfo_res_1_first_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:147:10
|
|
wire selectedInfo_hasOne = selectedInfo_res_hasOne | selectedInfo_res_2_hasOne; // utility/src/main/scala/utility/ParallelMux.scala:145:16
|
|
wire selectedInfo_hasTwo =
|
|
selectedInfo_res_hasTwo | s2_resps_1_valid & s2_resps_0_valid | s2_resps_2_valid
|
|
& selectedInfo_res_1_hasOne | selectedInfo_res_hasOne & selectedInfo_res_2_hasOne; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:{28,40}
|
|
wire [1:0] selectedInfo_first_ctr =
|
|
selectedInfo_res_hasOne
|
|
? (s2_resps_4_valid ? s2_resps_4_bits_ctr : s2_resps_3_bits_ctr)
|
|
: selectedInfo_res_2_first_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10
|
|
wire [38:0] selectedInfo_first_target =
|
|
selectedInfo_res_hasOne
|
|
? (s2_resps_4_valid ? s2_resps_4_bits_target : s2_resps_3_bits_target)
|
|
: selectedInfo_res_2_first_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10
|
|
wire _selectedInfo_T_91 = selectedInfo_res_hasOne & ~selectedInfo_res_hasTwo; // utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :150:{19,22}
|
|
wire [38:0] selectedInfo_second_target =
|
|
(selectedInfo_res_hasOne
|
|
? 39'h0
|
|
: (s2_resps_2_valid
|
|
? 39'h0
|
|
: (s2_resps_1_valid ? 39'h0 : s2_resps_0_bits_target)
|
|
| (s2_resps_1_valid ? s2_resps_0_bits_target : 39'h0))
|
|
| (s2_resps_2_valid ? selectedInfo_res_1_first_target : 39'h0))
|
|
| (_selectedInfo_T_91 ? selectedInfo_res_2_first_target : 39'h0)
|
|
| (selectedInfo_res_hasTwo
|
|
? (s2_resps_4_valid ? 39'h0 : s2_resps_3_bits_target)
|
|
| (s2_resps_4_valid ? s2_resps_3_bits_target : 39'h0)
|
|
: 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :147:10, :150:19
|
|
wire providerNull = selectedInfo_first_ctr == 2'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :459:39, utility/src/main/scala/utility/ParallelMux.scala:147:10
|
|
wire _s2_tageTarget_T = providerNull & selectedInfo_hasTwo; // src/main/scala/xiangshan/frontend/ITTAGE.scala:459:39, :465:33, utility/src/main/scala/utility/ParallelMux.scala:146:28
|
|
wire _s2_tageTarget_T_3 = selectedInfo_hasTwo & providerNull; // src/main/scala/xiangshan/frontend/ITTAGE.scala:459:39, :466:18, utility/src/main/scala/utility/ParallelMux.scala:146:28
|
|
wire _s2_tageTaken_WIRE =
|
|
selectedInfo_hasOne & ~_s2_tageTarget_T | _s2_tageTarget_T_3 | ~selectedInfo_hasOne; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:465:{15,18,33}, :466:18, :467:6, utility/src/main/scala/utility/ParallelMux.scala:145:16
|
|
wire [38:0] _s2_tageTarget_WIRE =
|
|
(selectedInfo_hasOne & ~_s2_tageTarget_T ? selectedInfo_first_target : 39'h0)
|
|
| (_s2_tageTarget_T_3 ? selectedInfo_second_target : 39'h0)
|
|
| (~selectedInfo_hasOne | providerNull & ~selectedInfo_hasTwo
|
|
? io_in_bits_resp_in_0_s2_full_pred_3_jalr_target
|
|
: 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :459:39, :465:33, :466:18, :467:6, :470:{15,18}, :472:{16,32,35}, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:28, :147:10
|
|
wire _GEN_0 =
|
|
io_update_bits_meta[92] & io_update_bits_meta[86:85] == 2'h0
|
|
& io_update_bits_mispred_mask_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :421:40, :525:80, :526:25
|
|
wire _GEN_1 = io_update_bits_meta[95:93] == 3'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :421:40, :539:30
|
|
wire _GEN_2 = updateValid & io_update_bits_meta[96]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:417:46, :421:40, :423:33, :520:22, :521:38, :539:30
|
|
wire _GEN_3 = io_update_bits_meta[95:93] == 3'h1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :539:30
|
|
wire _GEN_4 = io_update_bits_meta[95:93] == 3'h2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :539:30
|
|
wire _GEN_5 = io_update_bits_meta[95:93] == 3'h3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :539:30
|
|
wire _GEN_6 = io_update_bits_meta[95:93] == 3'h4; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :539:30
|
|
wire _updateU_T_2 =
|
|
io_update_bits_meta[88] ? ~io_update_bits_mispred_mask_2 : io_update_bits_meta[87]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :542:{31,78}
|
|
wire _updateCorrect_T = io_update_bits_meta[77:39] == io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :543:61
|
|
wire _GEN_7 = io_update_bits_meta[81:79] == 3'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :421:40, :560:34
|
|
wire _GEN_8 = _GEN & io_update_bits_meta[82] & _GEN_7; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :560:34
|
|
wire _GEN_9 = io_update_bits_meta[81:79] == 3'h1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :560:34
|
|
wire _GEN_10 = _GEN & io_update_bits_meta[82] & _GEN_9; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :560:34
|
|
wire _GEN_11 = io_update_bits_meta[81:79] == 3'h2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :560:34
|
|
wire _GEN_12 = _GEN & io_update_bits_meta[82] & _GEN_11; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :560:34
|
|
wire _GEN_13 = io_update_bits_meta[81:79] == 3'h3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :560:34
|
|
wire _GEN_14 = _GEN & io_update_bits_meta[82] & _GEN_13; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :560:34
|
|
wire _GEN_15 = io_update_bits_meta[81:79] == 3'h4; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :450:24, :560:34
|
|
wire _GEN_16 = _GEN & io_update_bits_meta[82] & _GEN_15; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :560:34
|
|
wire _GEN_17 = _GEN & io_update_bits_meta[82]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :520:22, :555:{38,79}, :558:27, :563:34
|
|
wire [2:0] selectedInfo_first_tableIdx =
|
|
selectedInfo_res_hasOne
|
|
? (s2_resps_4_valid ? 3'h4 : 3'h3)
|
|
: selectedInfo_res_2_first_tableIdx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, :450:24, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10
|
|
wire [1:0] selectedInfo_second_ctr =
|
|
(selectedInfo_res_hasOne
|
|
? 2'h0
|
|
: (s2_resps_2_valid
|
|
? 2'h0
|
|
: (s2_resps_1_valid ? 2'h0 : s2_resps_0_bits_ctr)
|
|
| (s2_resps_1_valid ? s2_resps_0_bits_ctr : 2'h0))
|
|
| (s2_resps_2_valid ? selectedInfo_res_1_first_ctr : 2'h0))
|
|
| (_selectedInfo_T_91 ? selectedInfo_res_2_first_ctr : 2'h0)
|
|
| (selectedInfo_res_hasTwo
|
|
? (s2_resps_4_valid ? 2'h0 : s2_resps_3_bits_ctr)
|
|
| (s2_resps_4_valid ? s2_resps_3_bits_ctr : 2'h0)
|
|
: 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :375:27, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :147:10, :150:19
|
|
wire [7:0] _s2_allocatableSlots_T_17 = 8'h1 << selectedInfo_first_tableIdx; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/ParallelMux.scala:147:10
|
|
wire [4:0] _GEN_18 = _s2_allocatableSlots_T_17[4:0] | _s2_allocatableSlots_T_17[5:1]; // src/main/scala/chisel3/util/OneHot.scala:58:35, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53
|
|
wire [4:0] _GEN_19 =
|
|
~({_GEN_18[4] | selectedInfo_first_tableIdx == 3'h6 | (&selectedInfo_first_tableIdx),
|
|
_GEN_18[3:0] | _s2_allocatableSlots_T_17[5:2] | _s2_allocatableSlots_T_17[6:3]
|
|
| _s2_allocatableSlots_T_17[7:4]} & {5{selectedInfo_hasOne}})
|
|
& {~s2_resps_4_valid & s2_resps_4_bits_u == 2'h0,
|
|
~s2_resps_3_valid & s2_resps_3_bits_u == 2'h0,
|
|
~s2_resps_2_valid & s2_resps_2_bits_u == 2'h0,
|
|
~s2_resps_1_valid & s2_resps_1_bits_u == 2'h0,
|
|
~s2_resps_0_valid & s2_resps_0_bits_u == 2'h0}; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:58:35, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :375:27, :509:{55,64,67,79,86}, :510:{5,55,61}, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53, :145:16, :147:10
|
|
wire [4:0] _GEN_20 = _GEN_19 & s2_allocLFSR_lfsr[4:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:509:86, :511:32, :513:60, utility/src/main/scala/utility/LFSR64.scala:27:33
|
|
wire [2:0] s2_maskedEntry =
|
|
_GEN_20[0]
|
|
? 3'h0
|
|
: _GEN_20[1]
|
|
? 3'h1
|
|
: _GEN_20[2] ? 3'h2 : _GEN_20[3] ? 3'h3 : _GEN_20[4] ? 3'h4 : 3'h7; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :450:24, :513:60
|
|
wire [7:0] _s2_allocEntry_T = {3'h0, _GEN_19} >> s2_maskedEntry; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :509:86, :514:47
|
|
always @(posedge clock) begin
|
|
if (io_s1_fire_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s2_resps_0_valid <= _tables_0_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_0_bits_ctr <= _tables_0_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_0_bits_u <= _tables_0_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_0_bits_target <= _tables_0_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_1_valid <= _tables_1_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_1_bits_ctr <= _tables_1_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_1_bits_u <= _tables_1_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_1_bits_target <= _tables_1_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_2_valid <= _tables_2_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_2_bits_ctr <= _tables_2_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_2_bits_u <= _tables_2_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_2_bits_target <= _tables_2_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_3_valid <= _tables_3_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_3_bits_ctr <= _tables_3_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_3_bits_u <= _tables_3_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_3_bits_target <= _tables_3_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_4_valid <= _tables_4_io_resp_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_4_bits_ctr <= _tables_4_io_resp_bits_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_4_bits_u <= _tables_4_io_resp_bits_u; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
s2_resps_4_bits_target <= _tables_4_io_resp_bits_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21, :375:27
|
|
end
|
|
if (io_s2_fire_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s3_tageTaken_dup_0 <= _s2_tageTaken_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59
|
|
s3_tageTarget_dup_0 <= _s2_tageTarget_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59
|
|
end
|
|
if (io_s2_fire_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s3_tageTaken_dup_1 <= _s2_tageTaken_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59
|
|
s3_tageTarget_dup_1 <= _s2_tageTarget_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59
|
|
end
|
|
if (io_s2_fire_2) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s3_tageTaken_dup_2 <= _s2_tageTaken_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59
|
|
s3_tageTarget_dup_2 <= _s2_tageTarget_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59
|
|
end
|
|
if (io_s2_fire_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s3_tageTaken_dup_3 <= _s2_tageTaken_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:394:59
|
|
s3_tageTarget_dup_3 <= _s2_tageTarget_WIRE; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:395:59
|
|
s3_providerTarget <= selectedInfo_first_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:396:39, utility/src/main/scala/utility/ParallelMux.scala:147:10
|
|
s3_altProviderTarget <= selectedInfo_second_target; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:397:39
|
|
s3_provided <= selectedInfo_hasOne; // src/main/scala/xiangshan/frontend/ITTAGE.scala:398:39, utility/src/main/scala/utility/ParallelMux.scala:145:16
|
|
s3_provider <= selectedInfo_first_tableIdx; // src/main/scala/xiangshan/frontend/ITTAGE.scala:399:39, utility/src/main/scala/utility/ParallelMux.scala:147:10
|
|
s3_altProvided <= selectedInfo_hasTwo; // src/main/scala/xiangshan/frontend/ITTAGE.scala:400:39, utility/src/main/scala/utility/ParallelMux.scala:146:28
|
|
s3_altProvider <=
|
|
(selectedInfo_res_hasOne | ~s2_resps_2_valid
|
|
? 3'h0
|
|
: selectedInfo_res_1_first_tableIdx)
|
|
| (_selectedInfo_T_91 ? selectedInfo_res_2_first_tableIdx : 3'h0)
|
|
| (selectedInfo_res_hasTwo
|
|
? (s2_resps_4_valid ? 3'h0 : 3'h3) | (s2_resps_4_valid ? 3'h3 : 3'h0)
|
|
: 3'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :375:27, :401:39, :450:24, utility/src/main/scala/utility/ParallelMux.scala:145:16, :146:40, :147:10, :150:19
|
|
s3_finalAltPred <= ~selectedInfo_hasTwo | selectedInfo_second_ctr[1]; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:402:39, :474:{25,58}, utility/src/main/scala/utility/ParallelMux.scala:146:28
|
|
s3_providerU <=
|
|
selectedInfo_res_hasOne
|
|
? (s2_resps_4_valid ? s2_resps_4_bits_u[0] : s2_resps_3_bits_u[0])
|
|
: s2_resps_2_valid
|
|
? s2_resps_2_bits_u[0]
|
|
: s2_resps_1_valid ? s2_resps_1_bits_u[0] : s2_resps_0_bits_u[0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:375:27, :403:39, utility/src/main/scala/utility/ParallelMux.scala:145:16, :147:10
|
|
s3_providerCtr <= selectedInfo_first_ctr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:404:39, utility/src/main/scala/utility/ParallelMux.scala:147:10
|
|
s3_altProviderCtr <= selectedInfo_second_ctr; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/ITTAGE.scala:405:39
|
|
resp_meta_allocate_valid_r <= |_GEN_19; // src/main/scala/xiangshan/frontend/ITTAGE.scala:509:86, :515:{40,61}
|
|
resp_meta_allocate_bits_r <=
|
|
_s2_allocEntry_T[0]
|
|
? s2_maskedEntry
|
|
: _GEN_19[0]
|
|
? 3'h0
|
|
: _GEN_19[1]
|
|
? 3'h1
|
|
: _GEN_19[2] ? 3'h2 : _GEN_19[3] ? 3'h3 : _GEN_19[4] ? 3'h4 : 3'h7; // src/main/scala/chisel3/util/Mux.scala:50:70, src/main/scala/chisel3/util/OneHot.scala:48:45, src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :450:24, :509:86, :514:{27,47}, :516:40
|
|
end
|
|
tables_0_io_update_valid_REG <=
|
|
_GEN_8 | _GEN_2 & (_GEN_1 | _GEN_0 & io_update_bits_meta[91:89] == 3'h0); // src/main/scala/xiangshan/frontend/ITTAGE.scala:355:40, :421:40, :423:33, :520:22, :521:38, :526:{25,43}, :529:36, :539:30, :555:79, :558:27, :560:34, :579:41
|
|
tables_0_io_update_correct_REG <= _GEN_8 | _GEN_1 & _updateCorrect_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :526:43, :539:30, :543:{32,61}, :555:79, :558:27, :560:34, :561:36, :580:43
|
|
tables_0_io_update_target_REG <= io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42
|
|
tables_0_io_update_old_target_REG <=
|
|
_GEN_1 ? io_update_bits_meta[77:39] : io_update_bits_meta[38:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :545:33, :582:46
|
|
tables_0_io_update_alloc_REG <= _GEN_17 & _GEN_7; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :555:79, :558:27, :560:34, :563:34, :583:41
|
|
tables_0_io_update_oldCtr_REG <=
|
|
_GEN_1 ? io_update_bits_meta[86:85] : io_update_bits_meta[84:83]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :546:30, :584:42
|
|
tables_0_io_update_reset_u_REG <= &tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17, :586:43
|
|
tables_0_io_update_uValid_REG <= _GEN_8 | _GEN_2 & _GEN_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:423:33, :424:33, :520:22, :521:38, :539:30, :540:30, :555:79, :558:27, :560:34, :564:34, :587:42
|
|
tables_0_io_update_u_REG <= ~_GEN_8 & _updateU_T_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :542:31, :555:79, :558:27, :560:34, :565:30, :588:37
|
|
tables_0_io_update_pc_REG <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38
|
|
tables_0_io_update_folded_hist_REG_hist_12_folded_hist <=
|
|
io_update_bits_spec_info_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
tables_1_io_update_valid_REG <=
|
|
_GEN_10 | _GEN_2 & (_GEN_3 | _GEN_0 & io_update_bits_meta[91:89] == 3'h1); // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :423:33, :450:24, :520:22, :521:38, :526:{25,43}, :529:36, :539:30, :555:79, :558:27, :560:34, :579:41
|
|
tables_1_io_update_correct_REG <= _GEN_10 | _GEN_3 & _updateCorrect_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :526:43, :539:30, :543:{32,61}, :555:79, :558:27, :560:34, :561:36, :580:43
|
|
tables_1_io_update_target_REG <= io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42
|
|
tables_1_io_update_old_target_REG <=
|
|
_GEN_3 ? io_update_bits_meta[77:39] : io_update_bits_meta[38:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :545:33, :582:46
|
|
tables_1_io_update_alloc_REG <= _GEN_17 & _GEN_9; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :555:79, :558:27, :560:34, :563:34, :583:41
|
|
tables_1_io_update_oldCtr_REG <=
|
|
_GEN_3 ? io_update_bits_meta[86:85] : io_update_bits_meta[84:83]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :546:30, :584:42
|
|
tables_1_io_update_reset_u_REG <= &tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17, :586:43
|
|
tables_1_io_update_uValid_REG <= _GEN_10 | _GEN_2 & _GEN_3; // src/main/scala/xiangshan/frontend/ITTAGE.scala:423:33, :424:33, :520:22, :521:38, :539:30, :540:30, :555:79, :558:27, :560:34, :564:34, :587:42
|
|
tables_1_io_update_u_REG <= ~_GEN_10 & _updateU_T_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :542:31, :555:79, :558:27, :560:34, :565:30, :588:37
|
|
tables_1_io_update_pc_REG <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38
|
|
tables_1_io_update_folded_hist_REG_hist_14_folded_hist <=
|
|
io_update_bits_spec_info_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
tables_2_io_update_valid_REG <=
|
|
_GEN_12 | _GEN_2 & (_GEN_4 | _GEN_0 & io_update_bits_meta[91:89] == 3'h2); // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :423:33, :450:24, :520:22, :521:38, :526:{25,43}, :529:36, :539:30, :555:79, :558:27, :560:34, :579:41
|
|
tables_2_io_update_correct_REG <= _GEN_12 | _GEN_4 & _updateCorrect_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :526:43, :539:30, :543:{32,61}, :555:79, :558:27, :560:34, :561:36, :580:43
|
|
tables_2_io_update_target_REG <= io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42
|
|
tables_2_io_update_old_target_REG <=
|
|
_GEN_4 ? io_update_bits_meta[77:39] : io_update_bits_meta[38:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :545:33, :582:46
|
|
tables_2_io_update_alloc_REG <= _GEN_17 & _GEN_11; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :555:79, :558:27, :560:34, :563:34, :583:41
|
|
tables_2_io_update_oldCtr_REG <=
|
|
_GEN_4 ? io_update_bits_meta[86:85] : io_update_bits_meta[84:83]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :546:30, :584:42
|
|
tables_2_io_update_reset_u_REG <= &tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17, :586:43
|
|
tables_2_io_update_uValid_REG <= _GEN_12 | _GEN_2 & _GEN_4; // src/main/scala/xiangshan/frontend/ITTAGE.scala:423:33, :424:33, :520:22, :521:38, :539:30, :540:30, :555:79, :558:27, :560:34, :564:34, :587:42
|
|
tables_2_io_update_u_REG <= ~_GEN_12 & _updateU_T_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :542:31, :555:79, :558:27, :560:34, :565:30, :588:37
|
|
tables_2_io_update_pc_REG <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38
|
|
tables_2_io_update_folded_hist_REG_hist_13_folded_hist <=
|
|
io_update_bits_spec_info_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
tables_2_io_update_folded_hist_REG_hist_4_folded_hist <=
|
|
io_update_bits_spec_info_folded_hist_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
tables_3_io_update_valid_REG <=
|
|
_GEN_14 | _GEN_2 & (_GEN_5 | _GEN_0 & io_update_bits_meta[91:89] == 3'h3); // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :423:33, :450:24, :520:22, :521:38, :526:{25,43}, :529:36, :539:30, :555:79, :558:27, :560:34, :579:41
|
|
tables_3_io_update_correct_REG <= _GEN_14 | _GEN_5 & _updateCorrect_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :526:43, :539:30, :543:{32,61}, :555:79, :558:27, :560:34, :561:36, :580:43
|
|
tables_3_io_update_target_REG <= io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42
|
|
tables_3_io_update_old_target_REG <=
|
|
_GEN_5 ? io_update_bits_meta[77:39] : io_update_bits_meta[38:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :545:33, :582:46
|
|
tables_3_io_update_alloc_REG <= _GEN_17 & _GEN_13; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :555:79, :558:27, :560:34, :563:34, :583:41
|
|
tables_3_io_update_oldCtr_REG <=
|
|
_GEN_5 ? io_update_bits_meta[86:85] : io_update_bits_meta[84:83]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :546:30, :584:42
|
|
tables_3_io_update_reset_u_REG <= &tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17, :586:43
|
|
tables_3_io_update_uValid_REG <= _GEN_14 | _GEN_2 & _GEN_5; // src/main/scala/xiangshan/frontend/ITTAGE.scala:423:33, :424:33, :520:22, :521:38, :539:30, :540:30, :555:79, :558:27, :560:34, :564:34, :587:42
|
|
tables_3_io_update_u_REG <= ~_GEN_14 & _updateU_T_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :542:31, :555:79, :558:27, :560:34, :565:30, :588:37
|
|
tables_3_io_update_pc_REG <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38
|
|
tables_3_io_update_folded_hist_REG_hist_6_folded_hist <=
|
|
io_update_bits_spec_info_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
tables_3_io_update_folded_hist_REG_hist_2_folded_hist <=
|
|
io_update_bits_spec_info_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
tables_4_io_update_valid_REG <=
|
|
_GEN_16 | _GEN_2 & (_GEN_6 | _GEN_0 & io_update_bits_meta[91:89] == 3'h4); // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :423:33, :450:24, :520:22, :521:38, :526:{25,43}, :529:36, :539:30, :555:79, :558:27, :560:34, :579:41
|
|
tables_4_io_update_correct_REG <= _GEN_16 | _GEN_6 & _updateCorrect_T; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :526:43, :539:30, :543:{32,61}, :555:79, :558:27, :560:34, :561:36, :580:43
|
|
tables_4_io_update_target_REG <= io_update_bits_full_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42
|
|
tables_4_io_update_old_target_REG <=
|
|
_GEN_6 ? io_update_bits_meta[77:39] : io_update_bits_meta[38:0]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :545:33, :582:46
|
|
tables_4_io_update_alloc_REG <= _GEN_17 & _GEN_15; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :555:79, :558:27, :560:34, :563:34, :583:41
|
|
tables_4_io_update_oldCtr_REG <=
|
|
_GEN_6 ? io_update_bits_meta[86:85] : io_update_bits_meta[84:83]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:421:40, :526:43, :539:30, :546:30, :584:42
|
|
tables_4_io_update_reset_u_REG <= &tickCtr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24, :569:17, :586:43
|
|
tables_4_io_update_uValid_REG <= _GEN_16 | _GEN_2 & _GEN_6; // src/main/scala/xiangshan/frontend/ITTAGE.scala:423:33, :424:33, :520:22, :521:38, :539:30, :540:30, :555:79, :558:27, :560:34, :564:34, :587:42
|
|
tables_4_io_update_u_REG <= ~_GEN_16 & _updateU_T_2; // src/main/scala/xiangshan/frontend/ITTAGE.scala:520:22, :542:31, :555:79, :558:27, :560:34, :565:30, :588:37
|
|
tables_4_io_update_pc_REG <= io_update_bits_pc; // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38
|
|
tables_4_io_update_folded_hist_REG_hist_10_folded_hist <=
|
|
io_update_bits_spec_info_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
tables_4_io_update_folded_hist_REG_hist_3_folded_hist <=
|
|
io_update_bits_spec_info_folded_hist_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
end // always @(posedge)
|
|
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
`endif // FIRRTL_BEFORE_INITIAL
|
|
logic [31:0] _RANDOM[0:77]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
initial begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
`endif // INIT_RANDOM_PROLOG_
|
|
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
for (logic [6:0] i = 7'h0; i < 7'h4E; i += 7'h1) begin
|
|
_RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
end // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
tickCtr = {_RANDOM[7'hE][31:26], _RANDOM[7'hF][1:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :370:24
|
|
s2_resps_0_valid = _RANDOM[7'hF][2]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :370:24, :375:27
|
|
s2_resps_0_bits_ctr = _RANDOM[7'hF][4:3]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :370:24, :375:27
|
|
s2_resps_0_bits_u = _RANDOM[7'hF][6:5]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :370:24, :375:27
|
|
s2_resps_0_bits_target = {_RANDOM[7'hF][31:7], _RANDOM[7'h10][13:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :370:24, :375:27
|
|
s2_resps_1_valid = _RANDOM[7'h10][14]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27
|
|
s2_resps_1_bits_ctr = _RANDOM[7'h10][16:15]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27
|
|
s2_resps_1_bits_u = _RANDOM[7'h10][18:17]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27
|
|
s2_resps_1_bits_target = {_RANDOM[7'h10][31:19], _RANDOM[7'h11][25:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27
|
|
s2_resps_2_valid = _RANDOM[7'h11][26]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27
|
|
s2_resps_2_bits_ctr = _RANDOM[7'h11][28:27]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27
|
|
s2_resps_2_bits_u = _RANDOM[7'h11][30:29]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27
|
|
s2_resps_2_bits_target =
|
|
{_RANDOM[7'h11][31], _RANDOM[7'h12], _RANDOM[7'h13][5:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27
|
|
s2_resps_3_valid = _RANDOM[7'h13][6]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27
|
|
s2_resps_3_bits_ctr = _RANDOM[7'h13][8:7]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27
|
|
s2_resps_3_bits_u = _RANDOM[7'h13][10:9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27
|
|
s2_resps_3_bits_target = {_RANDOM[7'h13][31:11], _RANDOM[7'h14][17:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27
|
|
s2_resps_4_valid = _RANDOM[7'h14][18]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27
|
|
s2_resps_4_bits_ctr = _RANDOM[7'h14][20:19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27
|
|
s2_resps_4_bits_u = _RANDOM[7'h14][22:21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27
|
|
s2_resps_4_bits_target = {_RANDOM[7'h14][31:23], _RANDOM[7'h15][29:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :375:27
|
|
s3_tageTaken_dup_0 = _RANDOM[7'h19][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59
|
|
s3_tageTaken_dup_1 = _RANDOM[7'h19][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59
|
|
s3_tageTaken_dup_2 = _RANDOM[7'h19][21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59
|
|
s3_tageTaken_dup_3 = _RANDOM[7'h19][22]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59
|
|
s3_tageTarget_dup_0 = {_RANDOM[7'h19][31:23], _RANDOM[7'h1A][29:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :395:59
|
|
s3_tageTarget_dup_1 =
|
|
{_RANDOM[7'h1A][31:30], _RANDOM[7'h1B], _RANDOM[7'h1C][4:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :395:59
|
|
s3_tageTarget_dup_2 = {_RANDOM[7'h1C][31:5], _RANDOM[7'h1D][11:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :395:59
|
|
s3_tageTarget_dup_3 = {_RANDOM[7'h1D][31:12], _RANDOM[7'h1E][18:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :395:59
|
|
s3_providerTarget = {_RANDOM[7'h1E][31:19], _RANDOM[7'h1F][25:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :395:59, :396:39
|
|
s3_altProviderTarget = {_RANDOM[7'h1F][31:26], _RANDOM[7'h20], _RANDOM[7'h21][0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :396:39, :397:39
|
|
s3_provided = _RANDOM[7'h21][1]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :398:39
|
|
s3_provider = _RANDOM[7'h21][4:2]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :399:39
|
|
s3_altProvided = _RANDOM[7'h21][5]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :400:39
|
|
s3_altProvider = _RANDOM[7'h21][8:6]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :401:39
|
|
s3_finalAltPred = _RANDOM[7'h21][9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :402:39
|
|
s3_providerU = _RANDOM[7'h21][10]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :403:39
|
|
s3_providerCtr = _RANDOM[7'h21][12:11]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :404:39
|
|
s3_altProviderCtr = _RANDOM[7'h21][14:13]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, :405:39
|
|
s2_allocLFSR_lfsr = {_RANDOM[7'h21][31:15], _RANDOM[7'h22], _RANDOM[7'h23][14:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :397:39, utility/src/main/scala/utility/LFSR64.scala:27:33
|
|
resp_meta_allocate_valid_r = _RANDOM[7'h23][15]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :515:40, utility/src/main/scala/utility/LFSR64.scala:27:33
|
|
resp_meta_allocate_bits_r = _RANDOM[7'h23][18:16]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :516:40, utility/src/main/scala/utility/LFSR64.scala:27:33
|
|
tables_0_io_update_valid_REG = _RANDOM[7'h23][19]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, utility/src/main/scala/utility/LFSR64.scala:27:33
|
|
tables_0_io_update_correct_REG = _RANDOM[7'h23][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :580:43, utility/src/main/scala/utility/LFSR64.scala:27:33
|
|
tables_0_io_update_target_REG = {_RANDOM[7'h23][31:21], _RANDOM[7'h24][27:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, utility/src/main/scala/utility/LFSR64.scala:27:33
|
|
tables_0_io_update_old_target_REG =
|
|
{_RANDOM[7'h24][31:28], _RANDOM[7'h25], _RANDOM[7'h26][2:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, :582:46
|
|
tables_0_io_update_alloc_REG = _RANDOM[7'h26][3]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :583:41
|
|
tables_0_io_update_oldCtr_REG = _RANDOM[7'h26][5:4]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :584:42
|
|
tables_0_io_update_reset_u_REG = _RANDOM[7'h26][6]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :586:43
|
|
tables_0_io_update_uValid_REG = _RANDOM[7'h26][7]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :587:42
|
|
tables_0_io_update_u_REG = _RANDOM[7'h26][8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :588:37
|
|
tables_0_io_update_pc_REG = {_RANDOM[7'h26][31:9], _RANDOM[7'h27][15:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :589:38
|
|
tables_0_io_update_folded_hist_REG_hist_12_folded_hist =
|
|
{_RANDOM[7'h28][31:30], _RANDOM[7'h29][1:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47
|
|
tables_1_io_update_valid_REG = _RANDOM[7'h2C][4]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41
|
|
tables_1_io_update_correct_REG = _RANDOM[7'h2C][5]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :580:43
|
|
tables_1_io_update_target_REG = {_RANDOM[7'h2C][31:6], _RANDOM[7'h2D][12:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :581:42
|
|
tables_1_io_update_old_target_REG = {_RANDOM[7'h2D][31:13], _RANDOM[7'h2E][19:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, :582:46
|
|
tables_1_io_update_alloc_REG = _RANDOM[7'h2E][20]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :583:41
|
|
tables_1_io_update_oldCtr_REG = _RANDOM[7'h2E][22:21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :584:42
|
|
tables_1_io_update_reset_u_REG = _RANDOM[7'h2E][23]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :586:43
|
|
tables_1_io_update_uValid_REG = _RANDOM[7'h2E][24]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :587:42
|
|
tables_1_io_update_u_REG = _RANDOM[7'h2E][25]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :588:37
|
|
tables_1_io_update_pc_REG =
|
|
{_RANDOM[7'h2E][31:26], _RANDOM[7'h2F], _RANDOM[7'h30][0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :589:38
|
|
tables_1_io_update_folded_hist_REG_hist_14_folded_hist =
|
|
{_RANDOM[7'h30][31:30], _RANDOM[7'h31][5:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :589:38, :591:47
|
|
tables_2_io_update_valid_REG = _RANDOM[7'h34][21]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41
|
|
tables_2_io_update_correct_REG = _RANDOM[7'h34][22]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :580:43
|
|
tables_2_io_update_target_REG = {_RANDOM[7'h34][31:23], _RANDOM[7'h35][29:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :581:42
|
|
tables_2_io_update_old_target_REG =
|
|
{_RANDOM[7'h35][31:30], _RANDOM[7'h36], _RANDOM[7'h37][4:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, :582:46
|
|
tables_2_io_update_alloc_REG = _RANDOM[7'h37][5]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :583:41
|
|
tables_2_io_update_oldCtr_REG = _RANDOM[7'h37][7:6]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :584:42
|
|
tables_2_io_update_reset_u_REG = _RANDOM[7'h37][8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :586:43
|
|
tables_2_io_update_uValid_REG = _RANDOM[7'h37][9]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :587:42
|
|
tables_2_io_update_u_REG = _RANDOM[7'h37][10]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :588:37
|
|
tables_2_io_update_pc_REG = {_RANDOM[7'h37][31:11], _RANDOM[7'h38][17:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :589:38
|
|
tables_2_io_update_folded_hist_REG_hist_13_folded_hist = _RANDOM[7'h39][31:23]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47
|
|
tables_2_io_update_folded_hist_REG_hist_4_folded_hist =
|
|
{_RANDOM[7'h3B][31:27], _RANDOM[7'h3C][2:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47
|
|
tables_3_io_update_valid_REG = _RANDOM[7'h3D][6]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41
|
|
tables_3_io_update_correct_REG = _RANDOM[7'h3D][7]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :580:43
|
|
tables_3_io_update_target_REG = {_RANDOM[7'h3D][31:8], _RANDOM[7'h3E][14:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :581:42
|
|
tables_3_io_update_old_target_REG = {_RANDOM[7'h3E][31:15], _RANDOM[7'h3F][21:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, :582:46
|
|
tables_3_io_update_alloc_REG = _RANDOM[7'h3F][22]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :583:41
|
|
tables_3_io_update_oldCtr_REG = _RANDOM[7'h3F][24:23]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :584:42
|
|
tables_3_io_update_reset_u_REG = _RANDOM[7'h3F][25]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :586:43
|
|
tables_3_io_update_uValid_REG = _RANDOM[7'h3F][26]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :587:42
|
|
tables_3_io_update_u_REG = _RANDOM[7'h3F][27]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :588:37
|
|
tables_3_io_update_pc_REG =
|
|
{_RANDOM[7'h3F][31:28], _RANDOM[7'h40], _RANDOM[7'h41][2:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :589:38
|
|
tables_3_io_update_folded_hist_REG_hist_6_folded_hist =
|
|
{_RANDOM[7'h43][31:28], _RANDOM[7'h44][4:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47
|
|
tables_3_io_update_folded_hist_REG_hist_2_folded_hist =
|
|
{_RANDOM[7'h44][31:28], _RANDOM[7'h45][3:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47
|
|
tables_4_io_update_valid_REG = _RANDOM[7'h45][23]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :579:41, :591:47
|
|
tables_4_io_update_correct_REG = _RANDOM[7'h45][24]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :580:43, :591:47
|
|
tables_4_io_update_target_REG = {_RANDOM[7'h45][31:25], _RANDOM[7'h46]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :581:42, :591:47
|
|
tables_4_io_update_old_target_REG = {_RANDOM[7'h47], _RANDOM[7'h48][6:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46
|
|
tables_4_io_update_alloc_REG = _RANDOM[7'h48][7]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :583:41
|
|
tables_4_io_update_oldCtr_REG = _RANDOM[7'h48][9:8]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :584:42
|
|
tables_4_io_update_reset_u_REG = _RANDOM[7'h48][10]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :586:43
|
|
tables_4_io_update_uValid_REG = _RANDOM[7'h48][11]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :587:42
|
|
tables_4_io_update_u_REG = _RANDOM[7'h48][12]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :588:37
|
|
tables_4_io_update_pc_REG = {_RANDOM[7'h48][31:13], _RANDOM[7'h49][19:0]}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :582:46, :589:38
|
|
tables_4_io_update_folded_hist_REG_hist_10_folded_hist = _RANDOM[7'h4B][22:14]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47
|
|
tables_4_io_update_folded_hist_REG_hist_3_folded_hist = _RANDOM[7'h4D][12:5]; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :591:47
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
tickCtr = 8'h0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:370:24
|
|
s2_allocLFSR_lfsr = 64'h1234567887654321; // utility/src/main/scala/utility/LFSR64.scala:27:33
|
|
end
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
`endif // FIRRTL_AFTER_INITIAL
|
|
`endif // ENABLE_INITIAL_REG_
|
|
ITTageTable tables_0 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_req_valid (io_s0_fire_3),
|
|
.io_req_bits_pc (io_in_bits_s0_pc_3),
|
|
.io_req_bits_folded_hist_hist_12_folded_hist
|
|
(io_in_bits_folded_hist_3_hist_12_folded_hist),
|
|
.io_resp_valid (_tables_0_io_resp_valid),
|
|
.io_resp_bits_ctr (_tables_0_io_resp_bits_ctr),
|
|
.io_resp_bits_u (_tables_0_io_resp_bits_u),
|
|
.io_resp_bits_target (_tables_0_io_resp_bits_target),
|
|
.io_update_pc (tables_0_io_update_pc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38
|
|
.io_update_folded_hist_hist_12_folded_hist
|
|
(tables_0_io_update_folded_hist_REG_hist_12_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
.io_update_valid (tables_0_io_update_valid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41
|
|
.io_update_correct (tables_0_io_update_correct_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43
|
|
.io_update_alloc (tables_0_io_update_alloc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41
|
|
.io_update_oldCtr (tables_0_io_update_oldCtr_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42
|
|
.io_update_uValid (tables_0_io_update_uValid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42
|
|
.io_update_u (tables_0_io_update_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37
|
|
.io_update_reset_u (tables_0_io_update_reset_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43
|
|
.io_update_target (tables_0_io_update_target_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42
|
|
.io_update_old_target (tables_0_io_update_old_target_REG) // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46
|
|
);
|
|
ITTageTable_1 tables_1 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_req_valid (io_s0_fire_3),
|
|
.io_req_bits_pc (io_in_bits_s0_pc_3),
|
|
.io_req_bits_folded_hist_hist_14_folded_hist
|
|
(io_in_bits_folded_hist_3_hist_14_folded_hist),
|
|
.io_resp_valid (_tables_1_io_resp_valid),
|
|
.io_resp_bits_ctr (_tables_1_io_resp_bits_ctr),
|
|
.io_resp_bits_u (_tables_1_io_resp_bits_u),
|
|
.io_resp_bits_target (_tables_1_io_resp_bits_target),
|
|
.io_update_pc (tables_1_io_update_pc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38
|
|
.io_update_folded_hist_hist_14_folded_hist
|
|
(tables_1_io_update_folded_hist_REG_hist_14_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
.io_update_valid (tables_1_io_update_valid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41
|
|
.io_update_correct (tables_1_io_update_correct_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43
|
|
.io_update_alloc (tables_1_io_update_alloc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41
|
|
.io_update_oldCtr (tables_1_io_update_oldCtr_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42
|
|
.io_update_uValid (tables_1_io_update_uValid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42
|
|
.io_update_u (tables_1_io_update_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37
|
|
.io_update_reset_u (tables_1_io_update_reset_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43
|
|
.io_update_target (tables_1_io_update_target_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42
|
|
.io_update_old_target (tables_1_io_update_old_target_REG) // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46
|
|
);
|
|
ITTageTable_2 tables_2 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_req_valid (io_s0_fire_3),
|
|
.io_req_bits_pc (io_in_bits_s0_pc_3),
|
|
.io_req_bits_folded_hist_hist_13_folded_hist
|
|
(io_in_bits_folded_hist_3_hist_13_folded_hist),
|
|
.io_req_bits_folded_hist_hist_4_folded_hist
|
|
(io_in_bits_folded_hist_3_hist_4_folded_hist),
|
|
.io_resp_valid (_tables_2_io_resp_valid),
|
|
.io_resp_bits_ctr (_tables_2_io_resp_bits_ctr),
|
|
.io_resp_bits_u (_tables_2_io_resp_bits_u),
|
|
.io_resp_bits_target (_tables_2_io_resp_bits_target),
|
|
.io_update_pc (tables_2_io_update_pc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38
|
|
.io_update_folded_hist_hist_13_folded_hist
|
|
(tables_2_io_update_folded_hist_REG_hist_13_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
.io_update_folded_hist_hist_4_folded_hist
|
|
(tables_2_io_update_folded_hist_REG_hist_4_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
.io_update_valid (tables_2_io_update_valid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41
|
|
.io_update_correct (tables_2_io_update_correct_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43
|
|
.io_update_alloc (tables_2_io_update_alloc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41
|
|
.io_update_oldCtr (tables_2_io_update_oldCtr_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42
|
|
.io_update_uValid (tables_2_io_update_uValid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42
|
|
.io_update_u (tables_2_io_update_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37
|
|
.io_update_reset_u (tables_2_io_update_reset_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43
|
|
.io_update_target (tables_2_io_update_target_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42
|
|
.io_update_old_target (tables_2_io_update_old_target_REG) // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46
|
|
);
|
|
ITTageTable_3 tables_3 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_req_valid (io_s0_fire_3),
|
|
.io_req_bits_pc (io_in_bits_s0_pc_3),
|
|
.io_req_bits_folded_hist_hist_6_folded_hist
|
|
(io_in_bits_folded_hist_3_hist_6_folded_hist),
|
|
.io_req_bits_folded_hist_hist_2_folded_hist
|
|
(io_in_bits_folded_hist_3_hist_2_folded_hist),
|
|
.io_resp_valid (_tables_3_io_resp_valid),
|
|
.io_resp_bits_ctr (_tables_3_io_resp_bits_ctr),
|
|
.io_resp_bits_u (_tables_3_io_resp_bits_u),
|
|
.io_resp_bits_target (_tables_3_io_resp_bits_target),
|
|
.io_update_pc (tables_3_io_update_pc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38
|
|
.io_update_folded_hist_hist_6_folded_hist
|
|
(tables_3_io_update_folded_hist_REG_hist_6_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
.io_update_folded_hist_hist_2_folded_hist
|
|
(tables_3_io_update_folded_hist_REG_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
.io_update_valid (tables_3_io_update_valid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41
|
|
.io_update_correct (tables_3_io_update_correct_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43
|
|
.io_update_alloc (tables_3_io_update_alloc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41
|
|
.io_update_oldCtr (tables_3_io_update_oldCtr_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42
|
|
.io_update_uValid (tables_3_io_update_uValid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42
|
|
.io_update_u (tables_3_io_update_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37
|
|
.io_update_reset_u (tables_3_io_update_reset_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43
|
|
.io_update_target (tables_3_io_update_target_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42
|
|
.io_update_old_target (tables_3_io_update_old_target_REG) // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46
|
|
);
|
|
ITTageTable_4 tables_4 ( // src/main/scala/xiangshan/frontend/ITTAGE.scala:360:21
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_req_valid (io_s0_fire_3),
|
|
.io_req_bits_pc (io_in_bits_s0_pc_3),
|
|
.io_req_bits_folded_hist_hist_10_folded_hist
|
|
(io_in_bits_folded_hist_3_hist_10_folded_hist),
|
|
.io_req_bits_folded_hist_hist_3_folded_hist
|
|
(io_in_bits_folded_hist_3_hist_3_folded_hist),
|
|
.io_resp_valid (_tables_4_io_resp_valid),
|
|
.io_resp_bits_ctr (_tables_4_io_resp_bits_ctr),
|
|
.io_resp_bits_u (_tables_4_io_resp_bits_u),
|
|
.io_resp_bits_target (_tables_4_io_resp_bits_target),
|
|
.io_update_pc (tables_4_io_update_pc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:589:38
|
|
.io_update_folded_hist_hist_10_folded_hist
|
|
(tables_4_io_update_folded_hist_REG_hist_10_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
.io_update_folded_hist_hist_3_folded_hist
|
|
(tables_4_io_update_folded_hist_REG_hist_3_folded_hist), // src/main/scala/xiangshan/frontend/ITTAGE.scala:591:47
|
|
.io_update_valid (tables_4_io_update_valid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:579:41
|
|
.io_update_correct (tables_4_io_update_correct_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:580:43
|
|
.io_update_alloc (tables_4_io_update_alloc_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:583:41
|
|
.io_update_oldCtr (tables_4_io_update_oldCtr_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:584:42
|
|
.io_update_uValid (tables_4_io_update_uValid_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:587:42
|
|
.io_update_u (tables_4_io_update_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:588:37
|
|
.io_update_reset_u (tables_4_io_update_reset_u_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:586:43
|
|
.io_update_target (tables_4_io_update_target_REG), // src/main/scala/xiangshan/frontend/ITTAGE.scala:581:42
|
|
.io_update_old_target (tables_4_io_update_old_target_REG) // src/main/scala/xiangshan/frontend/ITTAGE.scala:582:46
|
|
);
|
|
assign io_out_s2_full_pred_0_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_0_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_0_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_0_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_0_targets_0 = io_in_bits_resp_in_0_s2_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_0_targets_1 = io_in_bits_resp_in_0_s2_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_0_jalr_target =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_jalr_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_0_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_0_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_0_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_0_is_br_sharing =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_0_hit = io_in_bits_resp_in_0_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_1_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_1_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_1_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_1_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_1_targets_0 = io_in_bits_resp_in_0_s2_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_1_targets_1 = io_in_bits_resp_in_0_s2_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_1_jalr_target =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_jalr_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_1_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_1_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_1_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_1_is_br_sharing =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_1_hit = io_in_bits_resp_in_0_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_2_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_2_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_2_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_2_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_2_targets_0 = io_in_bits_resp_in_0_s2_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_2_targets_1 = io_in_bits_resp_in_0_s2_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_2_jalr_target =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_jalr_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_2_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_2_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_2_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_2_is_jalr = io_in_bits_resp_in_0_s2_full_pred_2_is_jalr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_2_is_call = io_in_bits_resp_in_0_s2_full_pred_2_is_call; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_2_is_ret = io_in_bits_resp_in_0_s2_full_pred_2_is_ret; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_2_last_may_be_rvi_call =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_2_is_br_sharing =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_2_hit = io_in_bits_resp_in_0_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_3_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_3_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_3_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_3_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_3_targets_0 = io_in_bits_resp_in_0_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_3_targets_1 = io_in_bits_resp_in_0_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_3_jalr_target =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_jalr_target; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_3_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_3_fallThroughErr =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_3_is_br_sharing =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s2_full_pred_3_hit = io_in_bits_resp_in_0_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s3_full_pred_0_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s3_full_pred_0_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s3_full_pred_0_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s3_full_pred_0_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s3_full_pred_0_targets_0 = io_in_bits_resp_in_0_s3_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s3_full_pred_0_targets_1 = io_in_bits_resp_in_0_s3_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s3_full_pred_0_jalr_target =
|
|
s3_tageTaken_dup_0
|
|
? s3_tageTarget_dup_0
|
|
: io_in_bits_resp_in_0_s3_full_pred_0_jalr_target; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :395:59, :490:26, :491:24
|
|
assign io_out_s3_full_pred_0_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s3_full_pred_0_fallThroughErr =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s3_full_pred_0_is_br_sharing =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s3_full_pred_0_hit = io_in_bits_resp_in_0_s3_full_pred_0_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s3_full_pred_1_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s3_full_pred_1_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_s3_full_pred_1_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_1_slot_valids_1 =
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io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_1_targets_0 = io_in_bits_resp_in_0_s3_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_1_targets_1 = io_in_bits_resp_in_0_s3_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_1_jalr_target =
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s3_tageTaken_dup_1
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? s3_tageTarget_dup_1
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: io_in_bits_resp_in_0_s3_full_pred_1_jalr_target; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :395:59, :490:26, :491:24
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assign io_out_s3_full_pred_1_fallThroughAddr =
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io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_1_fallThroughErr =
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io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_1_is_br_sharing =
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io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_1_hit = io_in_bits_resp_in_0_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_2_br_taken_mask_0 =
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io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_2_br_taken_mask_1 =
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io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_2_slot_valids_0 =
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io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_2_slot_valids_1 =
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io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_2_targets_0 = io_in_bits_resp_in_0_s3_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_2_targets_1 = io_in_bits_resp_in_0_s3_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_2_jalr_target =
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s3_tageTaken_dup_2
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? s3_tageTarget_dup_2
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: io_in_bits_resp_in_0_s3_full_pred_2_jalr_target; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :395:59, :490:26, :491:24
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assign io_out_s3_full_pred_2_fallThroughAddr =
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io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_2_fallThroughErr =
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io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_2_is_jalr = io_in_bits_resp_in_0_s3_full_pred_2_is_jalr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_2_is_call = io_in_bits_resp_in_0_s3_full_pred_2_is_call; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_2_is_ret = io_in_bits_resp_in_0_s3_full_pred_2_is_ret; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_2_is_br_sharing =
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io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_2_hit = io_in_bits_resp_in_0_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_3_br_taken_mask_0 =
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io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_3_br_taken_mask_1 =
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io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_3_slot_valids_0 =
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io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_3_slot_valids_1 =
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io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_3_targets_0 = io_in_bits_resp_in_0_s3_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_3_targets_1 = io_in_bits_resp_in_0_s3_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_3_jalr_target =
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s3_tageTaken_dup_3
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? s3_tageTarget_dup_3
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: io_in_bits_resp_in_0_s3_full_pred_3_jalr_target; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :395:59, :490:26, :491:24
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assign io_out_s3_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_3_fallThroughAddr =
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io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_3_fallThroughErr =
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io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_3_is_br_sharing =
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io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_s3_full_pred_3_hit = io_in_bits_resp_in_0_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_last_stage_meta =
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{122'h0,
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s3_provided,
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s3_provider,
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s3_altProvided,
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s3_altProvider,
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resp_meta_altDiffers,
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s3_providerU,
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s3_providerCtr,
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s3_altProviderCtr,
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resp_meta_allocate_valid_r,
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resp_meta_allocate_bits_r,
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s3_tageTaken_dup_3,
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s3_providerTarget,
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s3_altProviderTarget}; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7, :394:59, :396:39, :397:39, :398:39, :399:39, :400:39, :401:39, :403:39, :404:39, :405:39, :410:26, :498:50, :515:40, :516:40
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assign io_out_last_stage_ftb_entry_valid =
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io_in_bits_resp_in_0_last_stage_ftb_entry_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_last_stage_ftb_entry_brSlots_0_offset =
|
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io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_last_stage_ftb_entry_brSlots_0_lower =
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io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_last_stage_ftb_entry_brSlots_0_tarStat =
|
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io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
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assign io_out_last_stage_ftb_entry_brSlots_0_sharing =
|
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io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
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assign io_out_last_stage_ftb_entry_brSlots_0_valid =
|
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io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
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assign io_out_last_stage_ftb_entry_tailSlot_offset =
|
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io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
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assign io_out_last_stage_ftb_entry_tailSlot_lower =
|
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io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
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assign io_out_last_stage_ftb_entry_tailSlot_tarStat =
|
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io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
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assign io_out_last_stage_ftb_entry_tailSlot_sharing =
|
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io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_last_stage_ftb_entry_tailSlot_valid =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_last_stage_ftb_entry_pftAddr =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_last_stage_ftb_entry_carry =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_carry; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_last_stage_ftb_entry_isCall =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_isCall; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_last_stage_ftb_entry_isRet =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_isRet; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_last_stage_ftb_entry_isJalr =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_last_stage_ftb_entry_last_may_be_rvi_call =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_last_stage_ftb_entry_always_taken_0 =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
assign io_out_last_stage_ftb_entry_always_taken_1 =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1; // src/main/scala/xiangshan/frontend/ITTAGE.scala:354:7
|
|
endmodule
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