32778 lines
2.9 MiB
32778 lines
2.9 MiB
// Generated by CIRCT firtool-1.61.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module Predictor( // src/main/scala/xiangshan/frontend/BPU.scala:221:7
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input clock,
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input reset,
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input io_bpu_to_ftq_resp_ready, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [38:0] io_bpu_to_ftq_resp_bits_s1_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [38:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [38:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [3:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [3:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [38:0] io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s1_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s1_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [38:0] io_bpu_to_ftq_resp_bits_s2_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s2_valid_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s2_hasRedirect_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s2_ftq_idx_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [5:0] io_bpu_to_ftq_resp_bits_s2_ftq_idx_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [38:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [38:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [3:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [3:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [38:0] io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [38:0] io_bpu_to_ftq_resp_bits_s3_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s3_valid_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s3_hasRedirect_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s3_ftq_idx_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [5:0] io_bpu_to_ftq_resp_bits_s3_ftq_idx_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [38:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [38:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [3:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [3:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [38:0] io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [218:0] io_bpu_to_ftq_resp_bits_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [10:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [10:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [8:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [3:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [8:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [8:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [6:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [10:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_0_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [2:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_lastBrNumOH, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [7:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [3:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_ssp, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [1:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_sctr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [4:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [4:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [4:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [38:0] io_bpu_to_ftq_resp_bits_last_stage_spec_info_topAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [3:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [11:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [1:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [3:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [19:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [1:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output [3:0] io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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output io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_level, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [38:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_pc, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [3:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [1:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [4:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [4:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [4:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [10:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [10:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [8:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [3:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [8:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [8:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [6:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [10:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [2:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [7:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [38:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_target, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_taken, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [1:0] io_ftq_to_bpu_redirect_bits_cfiUpdate_shift, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [38:0] io_ftq_to_bpu_update_bits_pc, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [10:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [10:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [8:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [3:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [8:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [8:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [6:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [7:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [10:0] io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [3:0] io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [11:0] io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [1:0] io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [3:0] io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [19:0] io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [1:0] io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [3:0] io_ftq_to_bpu_update_bits_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_cfi_idx_valid, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [3:0] io_ftq_to_bpu_update_bits_cfi_idx_bits, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_jmp_taken, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_mispred_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_mispred_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_mispred_mask_2, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_update_bits_old_entry, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [218:0] io_ftq_to_bpu_update_bits_meta, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [38:0] io_ftq_to_bpu_update_bits_full_target, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ftq_to_bpu_enq_ptr_flag, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [5:0] io_ftq_to_bpu_enq_ptr_value, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ctrl_ubtb_enable, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ctrl_btb_enable, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ctrl_tage_enable, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ctrl_sc_enable, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input io_ctrl_ras_enable, // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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input [35:0] io_reset_vector // src/main/scala/xiangshan/frontend/BPU.scala:222:14
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);
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wire s3_redirect_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:684:28
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wire s3_redirect_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:684:28
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wire s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:684:28
|
|
wire s2_redirect_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:605:28
|
|
wire s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:605:28
|
|
wire s1_fire_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:374:60
|
|
wire s1_fire_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:374:60
|
|
wire s1_fire_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:374:60
|
|
wire s1_fire_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:374:60
|
|
wire _ghv_write_datas_255_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_254_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_253_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_252_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_251_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_250_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_249_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_248_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_247_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_246_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_245_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_244_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_243_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_242_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_241_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_240_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_239_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_238_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_237_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_236_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_235_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_234_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_233_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_232_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_231_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_230_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_229_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_228_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_227_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_226_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_225_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_224_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_223_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_222_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_221_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_220_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_219_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_218_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_217_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_216_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_215_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_214_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_213_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_212_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_211_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_210_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_209_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_208_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_207_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_206_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_205_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_204_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_203_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_202_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_201_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_200_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_199_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_198_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_197_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_196_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_195_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_194_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_193_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_192_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_191_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_190_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_189_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_188_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_187_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_186_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_185_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_184_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_183_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_182_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_181_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_180_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_179_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_178_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_177_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_176_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_175_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_174_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_173_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_172_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_171_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_170_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_169_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_168_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_167_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_166_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_165_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_164_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_163_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_162_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_161_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_160_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_159_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_158_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_157_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_156_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_155_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_154_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_153_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_152_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_151_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_150_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_149_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_148_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_147_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_146_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_145_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_144_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_143_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_142_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_141_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_140_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_139_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_138_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_137_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_136_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_135_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_134_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_133_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_132_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_131_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_130_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_129_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_128_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_127_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_126_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_125_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_124_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_123_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_122_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_121_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_120_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_119_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_118_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_117_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_116_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_115_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_114_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_113_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_112_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_111_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_110_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_109_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_108_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_107_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_106_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_105_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_104_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_103_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_102_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_101_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_100_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_99_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_98_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_97_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_96_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_95_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_94_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_93_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_92_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_91_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_90_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_89_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_88_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_87_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_86_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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wire _ghv_write_datas_85_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _ghv_write_datas_84_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _ghv_write_datas_83_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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wire _ghv_write_datas_82_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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wire _ghv_write_datas_81_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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wire _ghv_write_datas_80_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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wire _ghv_write_datas_79_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _ghv_write_datas_78_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _ghv_write_datas_77_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _ghv_write_datas_76_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _ghv_write_datas_75_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _ghv_write_datas_74_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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wire _ghv_write_datas_73_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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wire _ghv_write_datas_72_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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wire _ghv_write_datas_71_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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wire _ghv_write_datas_70_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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wire _ghv_write_datas_69_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _ghv_write_datas_68_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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wire _ghv_write_datas_67_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _ghv_write_datas_66_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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wire _ghv_write_datas_65_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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wire _ghv_write_datas_64_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _ghv_write_datas_63_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _ghv_write_datas_62_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _ghv_write_datas_61_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _ghv_write_datas_60_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _ghv_write_datas_59_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _ghv_write_datas_58_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_57_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _ghv_write_datas_56_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_55_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_54_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_53_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_52_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_51_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _ghv_write_datas_50_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_49_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_48_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_47_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_46_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_45_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_44_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_43_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_42_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_41_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_40_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_39_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_38_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_37_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_36_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_35_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_34_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_33_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_32_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_31_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_30_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_29_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_28_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_27_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_26_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_25_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_24_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_23_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_22_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_21_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_20_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_19_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_18_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_17_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_16_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_15_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_14_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_13_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_12_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_11_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_10_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_9_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_8_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_7_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_6_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_5_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_4_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_3_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_2_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_1_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _ghv_write_datas_0_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [2:0] _s0_last_br_num_oh_dup_3_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [2:0] _s0_last_br_num_oh_dup_2_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [2:0] _s0_last_br_num_oh_dup_1_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire _s0_ghist_ptr_dup_3_ppm_out_res_flag; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire [7:0] _s0_ghist_ptr_dup_3_ppm_out_res_value; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _s0_ghist_ptr_dup_2_ppm_out_res_flag; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_ghist_ptr_dup_2_ppm_out_res_value; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _s0_ghist_ptr_dup_1_ppm_out_res_flag; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire [7:0] _s0_ghist_ptr_dup_1_ppm_out_res_value; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire _s0_ghist_ptr_dup_0_ppm_out_res_flag; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
wire [7:0] _s0_ghist_ptr_dup_0_ppm_out_res_value; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [10:0] _s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [10:0] _s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [8:0] _s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [3:0] _s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [8:0] _s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [8:0] _s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [6:0] _s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [10:0] _s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [10:0] _s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [10:0] _s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [8:0] _s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [3:0] _s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [8:0] _s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [8:0] _s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [6:0] _s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [10:0] _s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [10:0] _s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [10:0] _s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [8:0] _s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [3:0] _s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [8:0] _s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [8:0] _s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [6:0] _s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [10:0] _s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [7:0] _s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [38:0] _s0_pc_dup_3_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [38:0] _s0_pc_dup_2_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [38:0] _s0_pc_dup_1_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [38:0] _s0_pc_dup_0_ppm_out_res; // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
wire [35:0] _reset_vector_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire [38:0] _predictors_io_out_s1_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s1_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s1_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s1_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s1_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s1_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [3:0] _predictors_io_out_s1_full_pred_0_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [3:0] _predictors_io_out_s1_full_pred_0_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s1_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s1_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s1_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [3:0] _predictors_io_out_s1_full_pred_1_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [3:0] _predictors_io_out_s1_full_pred_1_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s1_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s1_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s1_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [3:0] _predictors_io_out_s1_full_pred_2_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [3:0] _predictors_io_out_s1_full_pred_2_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s1_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s1_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s1_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [3:0] _predictors_io_out_s1_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [3:0] _predictors_io_out_s1_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s1_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s2_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s2_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s2_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s2_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s2_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s2_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s2_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [3:0] _predictors_io_out_s2_full_pred_0_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [3:0] _predictors_io_out_s2_full_pred_0_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [38:0] _predictors_io_out_s2_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire _predictors_io_out_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire _predictors_io_out_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire _predictors_io_out_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire _predictors_io_out_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire _predictors_io_out_s2_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire _predictors_io_out_s2_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [38:0] _predictors_io_out_s2_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [38:0] _predictors_io_out_s2_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [3:0] _predictors_io_out_s2_full_pred_1_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [3:0] _predictors_io_out_s2_full_pred_1_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [38:0] _predictors_io_out_s2_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire _predictors_io_out_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire _predictors_io_out_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire _predictors_io_out_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire _predictors_io_out_s2_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire _predictors_io_out_s2_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [38:0] _predictors_io_out_s2_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [38:0] _predictors_io_out_s2_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [3:0] _predictors_io_out_s2_full_pred_2_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [3:0] _predictors_io_out_s2_full_pred_2_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [38:0] _predictors_io_out_s2_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire _predictors_io_out_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire _predictors_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [38:0] _predictors_io_out_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire [38:0] _predictors_io_out_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire [3:0] _predictors_io_out_s2_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire [3:0] _predictors_io_out_s2_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [38:0] _predictors_io_out_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [38:0] _predictors_io_out_s3_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire [38:0] _predictors_io_out_s3_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [38:0] _predictors_io_out_s3_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [38:0] _predictors_io_out_s3_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s3_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s3_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s3_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s3_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s3_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s3_full_pred_0_fallThroughErr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s3_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s3_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s3_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s3_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s3_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s3_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s3_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s3_full_pred_1_fallThroughErr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s3_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s3_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire _predictors_io_out_s3_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire [38:0] _predictors_io_out_s3_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
wire [38:0] _predictors_io_out_s3_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [38:0] _predictors_io_out_s3_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s3_full_pred_2_fallThroughErr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s3_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s3_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s3_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire [38:0] _predictors_io_out_s3_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire [38:0] _predictors_io_out_s3_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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wire [38:0] _predictors_io_out_s3_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s3_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _predictors_io_s1_ready; // src/main/scala/xiangshan/frontend/BPU.scala:225:26
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|
wire _ctrl_delay_io_out_ubtb_enable; // utility/src/main/scala/utility/Hold.scala:97:23
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|
wire _ctrl_delay_io_out_btb_enable; // utility/src/main/scala/utility/Hold.scala:97:23
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|
wire _ctrl_delay_io_out_tage_enable; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
wire _ctrl_delay_io_out_sc_enable; // utility/src/main/scala/utility/Hold.scala:97:23
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|
wire _ctrl_delay_io_out_ras_enable; // utility/src/main/scala/utility/Hold.scala:97:23
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|
reg s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:271:65
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|
reg s2_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:271:65
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|
reg s3_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:271:65
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|
reg [38:0] s0_pc_reg_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:276:49
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|
reg [38:0] s0_pc_reg_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:276:49
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|
reg [38:0] s0_pc_reg_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:276:49
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|
reg [38:0] s0_pc_reg_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:276:49
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|
reg REG; // src/main/scala/xiangshan/frontend/BPU.scala:277:24
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|
reg REG_1; // src/main/scala/xiangshan/frontend/BPU.scala:277:16
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|
reg [10:0] s0_folded_gh_reg_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
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|
reg [10:0] s0_folded_gh_reg_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [6:0] s0_folded_gh_reg_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
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|
reg [7:0] s0_folded_gh_reg_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [8:0] s0_folded_gh_reg_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [3:0] s0_folded_gh_reg_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [7:0] s0_folded_gh_reg_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [8:0] s0_folded_gh_reg_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [6:0] s0_folded_gh_reg_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [7:0] s0_folded_gh_reg_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [6:0] s0_folded_gh_reg_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [8:0] s0_folded_gh_reg_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [6:0] s0_folded_gh_reg_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [7:0] s0_folded_gh_reg_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [7:0] s0_folded_gh_reg_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [7:0] s0_folded_gh_reg_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [10:0] s0_folded_gh_reg_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [7:0] s0_folded_gh_reg_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [10:0] s0_folded_gh_reg_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [10:0] s0_folded_gh_reg_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [6:0] s0_folded_gh_reg_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [7:0] s0_folded_gh_reg_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [8:0] s0_folded_gh_reg_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [3:0] s0_folded_gh_reg_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [7:0] s0_folded_gh_reg_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [8:0] s0_folded_gh_reg_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [6:0] s0_folded_gh_reg_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [7:0] s0_folded_gh_reg_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [6:0] s0_folded_gh_reg_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [8:0] s0_folded_gh_reg_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [6:0] s0_folded_gh_reg_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [7:0] s0_folded_gh_reg_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [7:0] s0_folded_gh_reg_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [7:0] s0_folded_gh_reg_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [10:0] s0_folded_gh_reg_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [7:0] s0_folded_gh_reg_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [10:0] s0_folded_gh_reg_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [10:0] s0_folded_gh_reg_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [6:0] s0_folded_gh_reg_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [7:0] s0_folded_gh_reg_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [8:0] s0_folded_gh_reg_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [3:0] s0_folded_gh_reg_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [7:0] s0_folded_gh_reg_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [8:0] s0_folded_gh_reg_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [6:0] s0_folded_gh_reg_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [7:0] s0_folded_gh_reg_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [6:0] s0_folded_gh_reg_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [8:0] s0_folded_gh_reg_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [6:0] s0_folded_gh_reg_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
reg [7:0] s0_folded_gh_reg_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
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reg [7:0] s0_folded_gh_reg_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
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reg [7:0] s0_folded_gh_reg_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
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reg [10:0] s0_folded_gh_reg_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
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reg [7:0] s0_folded_gh_reg_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63
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reg [10:0] s1_folded_gh_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
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reg [10:0] s1_folded_gh_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [6:0] s1_folded_gh_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
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reg [8:0] s1_folded_gh_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
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reg [3:0] s1_folded_gh_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
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reg [7:0] s1_folded_gh_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
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reg [8:0] s1_folded_gh_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
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reg [6:0] s1_folded_gh_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [6:0] s1_folded_gh_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [8:0] s1_folded_gh_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [6:0] s1_folded_gh_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [10:0] s1_folded_gh_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [10:0] s1_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [10:0] s1_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [6:0] s1_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [8:0] s1_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [3:0] s1_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [8:0] s1_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [6:0] s1_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [6:0] s1_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [8:0] s1_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [6:0] s1_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [10:0] s1_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [10:0] s1_folded_gh_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [10:0] s1_folded_gh_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [6:0] s1_folded_gh_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [8:0] s1_folded_gh_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [3:0] s1_folded_gh_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [8:0] s1_folded_gh_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [6:0] s1_folded_gh_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [6:0] s1_folded_gh_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [8:0] s1_folded_gh_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [6:0] s1_folded_gh_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [10:0] s1_folded_gh_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [7:0] s1_folded_gh_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35
|
|
reg [10:0] s2_folded_gh_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [10:0] s2_folded_gh_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [6:0] s2_folded_gh_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [8:0] s2_folded_gh_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [3:0] s2_folded_gh_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [8:0] s2_folded_gh_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [6:0] s2_folded_gh_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [6:0] s2_folded_gh_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [8:0] s2_folded_gh_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [6:0] s2_folded_gh_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [10:0] s2_folded_gh_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [10:0] s2_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [10:0] s2_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [6:0] s2_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [8:0] s2_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [3:0] s2_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [8:0] s2_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [6:0] s2_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [6:0] s2_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [8:0] s2_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [6:0] s2_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [10:0] s2_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [10:0] s2_folded_gh_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [10:0] s2_folded_gh_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [6:0] s2_folded_gh_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [8:0] s2_folded_gh_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [3:0] s2_folded_gh_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [8:0] s2_folded_gh_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [6:0] s2_folded_gh_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [6:0] s2_folded_gh_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [8:0] s2_folded_gh_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [6:0] s2_folded_gh_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [10:0] s2_folded_gh_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [7:0] s2_folded_gh_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35
|
|
reg [10:0] s3_folded_gh_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [10:0] s3_folded_gh_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [6:0] s3_folded_gh_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [7:0] s3_folded_gh_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [8:0] s3_folded_gh_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [3:0] s3_folded_gh_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [7:0] s3_folded_gh_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [8:0] s3_folded_gh_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [6:0] s3_folded_gh_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [7:0] s3_folded_gh_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [6:0] s3_folded_gh_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [8:0] s3_folded_gh_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [6:0] s3_folded_gh_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [7:0] s3_folded_gh_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [7:0] s3_folded_gh_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [7:0] s3_folded_gh_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [10:0] s3_folded_gh_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [7:0] s3_folded_gh_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [10:0] s3_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [10:0] s3_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [6:0] s3_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [7:0] s3_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [8:0] s3_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [3:0] s3_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [7:0] s3_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [8:0] s3_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [6:0] s3_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
|
|
reg [7:0] s3_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [6:0] s3_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [8:0] s3_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [6:0] s3_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [7:0] s3_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [7:0] s3_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [7:0] s3_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [10:0] s3_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [7:0] s3_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [10:0] s3_folded_gh_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [10:0] s3_folded_gh_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [6:0] s3_folded_gh_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [7:0] s3_folded_gh_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [8:0] s3_folded_gh_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [3:0] s3_folded_gh_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [7:0] s3_folded_gh_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [8:0] s3_folded_gh_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [6:0] s3_folded_gh_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [7:0] s3_folded_gh_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [6:0] s3_folded_gh_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [8:0] s3_folded_gh_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [6:0] s3_folded_gh_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [7:0] s3_folded_gh_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [7:0] s3_folded_gh_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [7:0] s3_folded_gh_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [10:0] s3_folded_gh_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [7:0] s3_folded_gh_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:288:35
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reg [2:0] s0_last_br_num_oh_reg_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:291:73
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reg [2:0] s0_last_br_num_oh_reg_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:291:73
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reg [2:0] s0_last_br_num_oh_reg_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:291:73
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reg [2:0] s1_last_br_num_oh_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:292:40
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reg [2:0] s1_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:292:40
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reg [2:0] s1_last_br_num_oh_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:292:40
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reg [2:0] s2_last_br_num_oh_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:293:40
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reg [2:0] s2_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:293:40
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reg [2:0] s2_last_br_num_oh_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:293:40
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reg [2:0] s3_last_br_num_oh_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:294:40
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reg [2:0] s3_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:294:40
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reg [2:0] s3_last_br_num_oh_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:294:40
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reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
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reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
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reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
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reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
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|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
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reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
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reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
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|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
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|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
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|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
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|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
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|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
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|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
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|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
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|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
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|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
|
|
reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46
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reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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reg s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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reg s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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reg s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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reg s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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reg s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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|
reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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|
reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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reg s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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|
reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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|
reg s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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|
reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
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|
reg s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:300:46
|
|
reg ghv_0; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_1; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_2; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_3; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_4; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_5; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_6; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_7; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_8; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_9; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_10; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_11; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_12; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_13; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_14; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_15; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_16; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_17; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_18; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_19; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_20; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_21; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_22; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_23; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_24; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_25; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_26; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_27; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_28; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_29; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_30; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_31; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_32; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_33; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_34; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_35; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_36; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_37; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_38; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_39; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_40; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_41; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_42; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_43; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_44; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_45; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_46; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_47; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_48; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_49; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_50; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_51; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_52; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_53; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_54; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_55; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_56; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_57; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_58; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_59; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_60; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_61; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_62; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_63; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_64; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_65; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_66; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_67; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_68; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_69; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_70; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_71; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_72; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_73; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_74; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_75; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_76; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_77; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_78; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_79; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_80; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_81; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_82; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_83; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_84; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_85; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_86; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_87; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_88; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_89; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_90; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_91; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_92; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_93; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_94; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_95; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_96; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_97; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_98; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_99; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_100; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_101; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_102; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_103; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_104; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_105; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_106; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_107; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_108; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_109; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_110; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_111; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_112; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_113; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_114; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_115; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_116; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_117; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_118; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_119; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_120; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_121; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_122; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_123; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_124; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_125; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_126; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_127; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_128; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_129; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_130; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_131; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_132; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_133; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_134; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_135; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_136; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_137; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_138; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_139; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_140; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_141; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_142; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_143; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_144; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_145; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_146; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_147; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_148; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_149; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_150; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_151; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_152; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_153; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_154; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_155; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
|
reg ghv_156; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
|
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reg ghv_157; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_158; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_159; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_160; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_161; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_162; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_163; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_164; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_165; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_166; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_167; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_168; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_169; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_170; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_171; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_172; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_173; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_174; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_175; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_176; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_177; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_178; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_179; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_180; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_181; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_182; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_183; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_184; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_185; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_186; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_187; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_188; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_189; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_190; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_191; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_192; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_193; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_194; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_195; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_196; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_197; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_198; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_199; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_200; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_201; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_202; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_203; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_204; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_205; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_206; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_207; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_208; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_209; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_210; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_211; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_212; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_213; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_214; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_215; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_216; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_217; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_218; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_219; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_220; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_221; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_222; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_223; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_224; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_225; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_226; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_227; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_228; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_229; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_230; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_231; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_232; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_233; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_234; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_235; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_236; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_237; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_238; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_239; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_240; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_241; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_242; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_243; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_244; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_245; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_246; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_247; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_248; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_249; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_250; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_251; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_252; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_253; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_254; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg ghv_255; // src/main/scala/xiangshan/frontend/BPU.scala:311:20
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reg s0_ghist_ptr_reg_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63
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reg [7:0] s0_ghist_ptr_reg_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63
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reg s0_ghist_ptr_reg_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63
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reg [7:0] s0_ghist_ptr_reg_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63
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reg s0_ghist_ptr_reg_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63
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reg [7:0] s0_ghist_ptr_reg_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63
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reg s0_ghist_ptr_reg_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63
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reg [7:0] s0_ghist_ptr_reg_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63
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reg s1_ghist_ptr_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35
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reg [7:0] s1_ghist_ptr_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35
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reg s1_ghist_ptr_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35
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reg [7:0] s1_ghist_ptr_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35
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reg s1_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35
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reg [7:0] s1_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35
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reg s1_ghist_ptr_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35
|
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reg [7:0] s1_ghist_ptr_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35
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reg s2_ghist_ptr_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35
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reg [7:0] s2_ghist_ptr_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35
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reg s2_ghist_ptr_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35
|
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reg [7:0] s2_ghist_ptr_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35
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reg s2_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35
|
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reg [7:0] s2_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35
|
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reg s2_ghist_ptr_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35
|
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reg [7:0] s2_ghist_ptr_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35
|
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reg s3_ghist_ptr_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:325:35
|
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reg [7:0] s3_ghist_ptr_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:325:35
|
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reg s3_ghist_ptr_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:325:35
|
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reg [7:0] s3_ghist_ptr_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:325:35
|
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reg s3_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:325:35
|
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reg [7:0] s3_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:325:35
|
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reg s3_ghist_ptr_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:325:35
|
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reg [7:0] s3_ghist_ptr_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:325:35
|
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reg do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg do_redirect_dup_3_bits_level; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [38:0] do_redirect_dup_3_bits_cfiUpdate_pc; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg do_redirect_dup_3_bits_cfiUpdate_pd_isRVC; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg do_redirect_dup_3_bits_cfiUpdate_pd_isCall; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg do_redirect_dup_3_bits_cfiUpdate_pd_isRet; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [3:0] do_redirect_dup_3_bits_cfiUpdate_ssp; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [1:0] do_redirect_dup_3_bits_cfiUpdate_sctr; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg do_redirect_dup_3_bits_cfiUpdate_TOSW_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [4:0] do_redirect_dup_3_bits_cfiUpdate_TOSW_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg do_redirect_dup_3_bits_cfiUpdate_TOSR_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [4:0] do_redirect_dup_3_bits_cfiUpdate_TOSR_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg do_redirect_dup_3_bits_cfiUpdate_NOS_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [4:0] do_redirect_dup_3_bits_cfiUpdate_NOS_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [10:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [10:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [6:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [8:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [3:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [8:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [6:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [6:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [8:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [6:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
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reg [10:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg [7:0] do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
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reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
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reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
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reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
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reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
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reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
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reg do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
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reg [2:0] do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
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reg do_redirect_dup_3_bits_cfiUpdate_histPtr_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
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reg [7:0] do_redirect_dup_3_bits_cfiUpdate_histPtr_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
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reg [38:0] do_redirect_dup_3_bits_cfiUpdate_target; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
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reg do_redirect_dup_3_bits_cfiUpdate_taken; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
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reg [1:0] thisBrNumOH_dup_shiftAmount; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
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reg do_redirect_dup_3_bits_cfiUpdate_addIntoHist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
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wire s2_flush_dup_3 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :684:28
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wire s0_fire_dup_0 =
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_predictors_io_s1_ready & (s1_fire_dup_0 | ~s1_valid_dup_3); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :365:{25,28}, :367:36, :374:60
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wire s0_fire_dup_1 =
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_predictors_io_s1_ready & (s1_fire_dup_1 | ~s1_valid_dup_3); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :365:{25,28}, :367:36, :374:60
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wire s0_fire_dup_2 =
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_predictors_io_s1_ready & (s1_fire_dup_2 | ~s1_valid_dup_3); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :365:{25,28}, :367:36, :374:60
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wire s0_fire_dup_3 =
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_predictors_io_s1_ready & (s1_fire_dup_3 | ~s1_valid_dup_3); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :365:{25,28}, :367:36, :374:60
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assign s1_fire_dup_0 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :374:60
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assign s1_fire_dup_1 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :374:60
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assign s1_fire_dup_2 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :374:60
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assign s1_fire_dup_3 = s1_valid_dup_3 & io_bpu_to_ftq_resp_ready; // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :374:60
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wire [8:0] _GEN = {s1_ghist_ptr_dup_0_flag, s1_ghist_ptr_dup_0_value}; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1 =
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9'(_GEN - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3 =
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9'(_GEN + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5 =
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9'(_GEN + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire [8:0] _GEN_0 = {s1_ghist_ptr_dup_1_flag, s1_ghist_ptr_dup_1_value}; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7 =
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9'(_GEN_0 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9 =
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|
9'(_GEN_0 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11 =
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9'(_GEN_0 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire [8:0] _GEN_1 = {s1_ghist_ptr_dup_2_flag, s1_ghist_ptr_dup_2_value}; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13 =
|
|
9'(_GEN_1 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15 =
|
|
9'(_GEN_1 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17 =
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|
9'(_GEN_1 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire [8:0] _GEN_2 = {s1_ghist_ptr_dup_3_flag, s1_ghist_ptr_dup_3_value}; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19 =
|
|
9'(_GEN_2 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21 =
|
|
9'(_GEN_2 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
wire [8:0] _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23 =
|
|
9'(_GEN_2 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
wire _s1_ghv_wdatas_WIRE_44494_1 =
|
|
_predictors_io_out_s1_full_pred_0_slot_valids_1
|
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& _predictors_io_out_s1_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48
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wire _s1_predicted_ghist_ptr_dup_WIRE_56_0_0 =
|
|
~_predictors_io_out_s1_full_pred_0_hit
|
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| ~(_predictors_io_out_s1_full_pred_0_slot_valids_0 | _s1_ghv_wdatas_WIRE_44494_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
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wire _cfiIndex_bits_WIRE_18_0 =
|
|
_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
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|
wire _cfiIndex_bits_T_94 =
|
|
_predictors_io_out_s1_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25
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|
wire _s1_predicted_ghist_ptr_dup_WIRE_56_0_1 =
|
|
_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
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|
wire _s1_predicted_ghist_ptr_dup_WIRE_56_0_2 =
|
|
_s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
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|
wire _s1_predicted_fh_dup_WIRE_21_1 =
|
|
_predictors_io_out_s1_full_pred_1_slot_valids_1
|
|
& _predictors_io_out_s1_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48
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|
wire _s1_predicted_ghist_ptr_dup_WIRE_56_1_0 =
|
|
~_predictors_io_out_s1_full_pred_1_hit
|
|
| ~(_predictors_io_out_s1_full_pred_1_slot_valids_0 | _s1_predicted_fh_dup_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
wire _cfiIndex_bits_WIRE_22_0 =
|
|
_predictors_io_out_s1_full_pred_1_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
wire _cfiIndex_bits_T_115 =
|
|
_predictors_io_out_s1_full_pred_1_is_br_sharing
|
|
& _predictors_io_out_s1_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25
|
|
wire _s1_predicted_ghist_ptr_dup_WIRE_56_1_1 =
|
|
_predictors_io_out_s1_full_pred_1_slot_valids_0
|
|
& (_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit
|
|
| ~_s1_predicted_fh_dup_WIRE_21_1) & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
|
|
wire _s1_predicted_ghist_ptr_dup_WIRE_56_1_2 =
|
|
_s1_predicted_fh_dup_WIRE_21_1
|
|
& ~(_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit)
|
|
& _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
|
|
wire _s1_predicted_fh_dup_WIRE_35_1 =
|
|
_predictors_io_out_s1_full_pred_2_slot_valids_1
|
|
& _predictors_io_out_s1_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48
|
|
wire _s1_predicted_ghist_ptr_dup_WIRE_56_2_0 =
|
|
~_predictors_io_out_s1_full_pred_2_hit
|
|
| ~(_predictors_io_out_s1_full_pred_2_slot_valids_0 | _s1_predicted_fh_dup_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
wire _cfiIndex_bits_WIRE_26_0 =
|
|
_predictors_io_out_s1_full_pred_2_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
wire _cfiIndex_bits_T_136 =
|
|
_predictors_io_out_s1_full_pred_2_is_br_sharing
|
|
& _predictors_io_out_s1_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25
|
|
wire _s1_predicted_ghist_ptr_dup_WIRE_56_2_1 =
|
|
_predictors_io_out_s1_full_pred_2_slot_valids_0
|
|
& (_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit
|
|
| ~_s1_predicted_fh_dup_WIRE_35_1) & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
|
|
wire _s1_predicted_ghist_ptr_dup_WIRE_56_2_2 =
|
|
_s1_predicted_fh_dup_WIRE_35_1
|
|
& ~(_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit)
|
|
& _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
|
|
wire _s1_predicted_fh_dup_WIRE_49_1 =
|
|
_predictors_io_out_s1_full_pred_3_slot_valids_1
|
|
& _predictors_io_out_s1_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48
|
|
wire _s1_predicted_ghist_ptr_dup_WIRE_56_3_0 =
|
|
~_predictors_io_out_s1_full_pred_3_hit
|
|
| ~(_predictors_io_out_s1_full_pred_3_slot_valids_0 | _s1_predicted_fh_dup_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
wire _cfiIndex_bits_WIRE_30_0 =
|
|
_predictors_io_out_s1_full_pred_3_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
wire _cfiIndex_bits_T_157 =
|
|
_predictors_io_out_s1_full_pred_3_is_br_sharing
|
|
& _predictors_io_out_s1_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25
|
|
wire _s1_predicted_ghist_ptr_dup_WIRE_56_3_1 =
|
|
_predictors_io_out_s1_full_pred_3_slot_valids_0
|
|
& (_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit
|
|
| ~_s1_predicted_fh_dup_WIRE_49_1) & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
|
|
wire _s1_predicted_ghist_ptr_dup_WIRE_56_3_2 =
|
|
_s1_predicted_fh_dup_WIRE_49_1
|
|
& ~(_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit)
|
|
& _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
|
|
wire _s1_possible_predicted_fhs_dup_WIRE_4_1 =
|
|
_predictors_io_out_s1_full_pred_1_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_1_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_1_hit | _s1_predicted_fh_dup_WIRE_21_1
|
|
& _predictors_io_out_s1_full_pred_1_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :493:{74,90}
|
|
wire _s1_possible_predicted_fhs_dup_WIRE_4_2 =
|
|
_predictors_io_out_s1_full_pred_2_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_2_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_2_hit | _s1_predicted_fh_dup_WIRE_35_1
|
|
& _predictors_io_out_s1_full_pred_2_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :493:{74,90}
|
|
wire _s1_possible_predicted_fhs_dup_WIRE_4_3 =
|
|
_predictors_io_out_s1_full_pred_3_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_3_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_3_hit | _s1_predicted_fh_dup_WIRE_49_1
|
|
& _predictors_io_out_s1_full_pred_3_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :493:{74,90}
|
|
wire _s1_possible_predicted_fhs_dup_T_271 =
|
|
_s1_possible_predicted_fhs_dup_WIRE_4_1
|
|
& (~_predictors_io_out_s1_full_pred_1_hit
|
|
| ~(_predictors_io_out_s1_full_pred_1_slot_valids_0
|
|
| _s1_predicted_fh_dup_WIRE_21_1)); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}, :493:90
|
|
wire
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0
|
|
=
|
|
_s1_possible_predicted_fhs_dup_WIRE_4_1
|
|
& _predictors_io_out_s1_full_pred_1_slot_valids_0
|
|
& (_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit
|
|
| ~_s1_predicted_fh_dup_WIRE_21_1) & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37}, :493:90
|
|
wire
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1
|
|
=
|
|
_s1_possible_predicted_fhs_dup_WIRE_4_1 & _s1_predicted_fh_dup_WIRE_21_1
|
|
& ~(_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit)
|
|
& _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :493:90
|
|
wire _s1_possible_predicted_fhs_dup_T_274 =
|
|
_s1_possible_predicted_fhs_dup_WIRE_4_2
|
|
& (~_predictors_io_out_s1_full_pred_2_hit
|
|
| ~(_predictors_io_out_s1_full_pred_2_slot_valids_0
|
|
| _s1_predicted_fh_dup_WIRE_35_1)); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}, :493:90
|
|
wire
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0
|
|
=
|
|
_s1_possible_predicted_fhs_dup_WIRE_4_2
|
|
& _predictors_io_out_s1_full_pred_2_slot_valids_0
|
|
& (_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit
|
|
| ~_s1_predicted_fh_dup_WIRE_35_1) & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37}, :493:90
|
|
wire
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1
|
|
=
|
|
_s1_possible_predicted_fhs_dup_WIRE_4_2 & _s1_predicted_fh_dup_WIRE_35_1
|
|
& ~(_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit)
|
|
& _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :493:90
|
|
wire _s1_possible_predicted_fhs_dup_T_277 =
|
|
_s1_possible_predicted_fhs_dup_WIRE_4_3
|
|
& (~_predictors_io_out_s1_full_pred_3_hit
|
|
| ~(_predictors_io_out_s1_full_pred_3_slot_valids_0
|
|
| _s1_predicted_fh_dup_WIRE_49_1)); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}, :493:90
|
|
wire
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0
|
|
=
|
|
_s1_possible_predicted_fhs_dup_WIRE_4_3
|
|
& _predictors_io_out_s1_full_pred_3_slot_valids_0
|
|
& (_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit
|
|
| ~_s1_predicted_fh_dup_WIRE_49_1) & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37}, :493:90
|
|
wire
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
=
|
|
_s1_possible_predicted_fhs_dup_WIRE_4_3 & _s1_predicted_fh_dup_WIRE_49_1
|
|
& ~(_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit)
|
|
& _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :493:90
|
|
wire _s1_predicted_fh_dup_WIRE_56_1_0 =
|
|
~_predictors_io_out_s1_full_pred_1_hit
|
|
| ~(_predictors_io_out_s1_full_pred_1_slot_valids_0 | _s1_predicted_fh_dup_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
wire _s1_predicted_fh_dup_WIRE_56_1_1 =
|
|
_predictors_io_out_s1_full_pred_1_slot_valids_0
|
|
& (_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit
|
|
| ~_s1_predicted_fh_dup_WIRE_21_1) & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
|
|
wire _s1_predicted_fh_dup_WIRE_56_1_2 =
|
|
_s1_predicted_fh_dup_WIRE_21_1
|
|
& ~(_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit)
|
|
& _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
|
|
wire _s1_predicted_fh_dup_WIRE_56_2_0 =
|
|
~_predictors_io_out_s1_full_pred_2_hit
|
|
| ~(_predictors_io_out_s1_full_pred_2_slot_valids_0 | _s1_predicted_fh_dup_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
wire _s1_predicted_fh_dup_WIRE_56_2_1 =
|
|
_predictors_io_out_s1_full_pred_2_slot_valids_0
|
|
& (_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit
|
|
| ~_s1_predicted_fh_dup_WIRE_35_1) & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
|
|
wire _s1_predicted_fh_dup_WIRE_56_2_2 =
|
|
_s1_predicted_fh_dup_WIRE_35_1
|
|
& ~(_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit)
|
|
& _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
|
|
wire _s1_predicted_fh_dup_WIRE_56_3_0 =
|
|
~_predictors_io_out_s1_full_pred_3_hit
|
|
| ~(_predictors_io_out_s1_full_pred_3_slot_valids_0 | _s1_predicted_fh_dup_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
wire _s1_predicted_fh_dup_WIRE_56_3_1 =
|
|
_predictors_io_out_s1_full_pred_3_slot_valids_0
|
|
& (_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit
|
|
| ~_s1_predicted_fh_dup_WIRE_49_1) & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
|
|
wire _s1_predicted_fh_dup_WIRE_56_3_2 =
|
|
_s1_predicted_fh_dup_WIRE_49_1
|
|
& ~(_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit)
|
|
& _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
|
|
wire [255:0] _GEN_3 =
|
|
{{ghv_255},
|
|
{ghv_254},
|
|
{ghv_253},
|
|
{ghv_252},
|
|
{ghv_251},
|
|
{ghv_250},
|
|
{ghv_249},
|
|
{ghv_248},
|
|
{ghv_247},
|
|
{ghv_246},
|
|
{ghv_245},
|
|
{ghv_244},
|
|
{ghv_243},
|
|
{ghv_242},
|
|
{ghv_241},
|
|
{ghv_240},
|
|
{ghv_239},
|
|
{ghv_238},
|
|
{ghv_237},
|
|
{ghv_236},
|
|
{ghv_235},
|
|
{ghv_234},
|
|
{ghv_233},
|
|
{ghv_232},
|
|
{ghv_231},
|
|
{ghv_230},
|
|
{ghv_229},
|
|
{ghv_228},
|
|
{ghv_227},
|
|
{ghv_226},
|
|
{ghv_225},
|
|
{ghv_224},
|
|
{ghv_223},
|
|
{ghv_222},
|
|
{ghv_221},
|
|
{ghv_220},
|
|
{ghv_219},
|
|
{ghv_218},
|
|
{ghv_217},
|
|
{ghv_216},
|
|
{ghv_215},
|
|
{ghv_214},
|
|
{ghv_213},
|
|
{ghv_212},
|
|
{ghv_211},
|
|
{ghv_210},
|
|
{ghv_209},
|
|
{ghv_208},
|
|
{ghv_207},
|
|
{ghv_206},
|
|
{ghv_205},
|
|
{ghv_204},
|
|
{ghv_203},
|
|
{ghv_202},
|
|
{ghv_201},
|
|
{ghv_200},
|
|
{ghv_199},
|
|
{ghv_198},
|
|
{ghv_197},
|
|
{ghv_196},
|
|
{ghv_195},
|
|
{ghv_194},
|
|
{ghv_193},
|
|
{ghv_192},
|
|
{ghv_191},
|
|
{ghv_190},
|
|
{ghv_189},
|
|
{ghv_188},
|
|
{ghv_187},
|
|
{ghv_186},
|
|
{ghv_185},
|
|
{ghv_184},
|
|
{ghv_183},
|
|
{ghv_182},
|
|
{ghv_181},
|
|
{ghv_180},
|
|
{ghv_179},
|
|
{ghv_178},
|
|
{ghv_177},
|
|
{ghv_176},
|
|
{ghv_175},
|
|
{ghv_174},
|
|
{ghv_173},
|
|
{ghv_172},
|
|
{ghv_171},
|
|
{ghv_170},
|
|
{ghv_169},
|
|
{ghv_168},
|
|
{ghv_167},
|
|
{ghv_166},
|
|
{ghv_165},
|
|
{ghv_164},
|
|
{ghv_163},
|
|
{ghv_162},
|
|
{ghv_161},
|
|
{ghv_160},
|
|
{ghv_159},
|
|
{ghv_158},
|
|
{ghv_157},
|
|
{ghv_156},
|
|
{ghv_155},
|
|
{ghv_154},
|
|
{ghv_153},
|
|
{ghv_152},
|
|
{ghv_151},
|
|
{ghv_150},
|
|
{ghv_149},
|
|
{ghv_148},
|
|
{ghv_147},
|
|
{ghv_146},
|
|
{ghv_145},
|
|
{ghv_144},
|
|
{ghv_143},
|
|
{ghv_142},
|
|
{ghv_141},
|
|
{ghv_140},
|
|
{ghv_139},
|
|
{ghv_138},
|
|
{ghv_137},
|
|
{ghv_136},
|
|
{ghv_135},
|
|
{ghv_134},
|
|
{ghv_133},
|
|
{ghv_132},
|
|
{ghv_131},
|
|
{ghv_130},
|
|
{ghv_129},
|
|
{ghv_128},
|
|
{ghv_127},
|
|
{ghv_126},
|
|
{ghv_125},
|
|
{ghv_124},
|
|
{ghv_123},
|
|
{ghv_122},
|
|
{ghv_121},
|
|
{ghv_120},
|
|
{ghv_119},
|
|
{ghv_118},
|
|
{ghv_117},
|
|
{ghv_116},
|
|
{ghv_115},
|
|
{ghv_114},
|
|
{ghv_113},
|
|
{ghv_112},
|
|
{ghv_111},
|
|
{ghv_110},
|
|
{ghv_109},
|
|
{ghv_108},
|
|
{ghv_107},
|
|
{ghv_106},
|
|
{ghv_105},
|
|
{ghv_104},
|
|
{ghv_103},
|
|
{ghv_102},
|
|
{ghv_101},
|
|
{ghv_100},
|
|
{ghv_99},
|
|
{ghv_98},
|
|
{ghv_97},
|
|
{ghv_96},
|
|
{ghv_95},
|
|
{ghv_94},
|
|
{ghv_93},
|
|
{ghv_92},
|
|
{ghv_91},
|
|
{ghv_90},
|
|
{ghv_89},
|
|
{ghv_88},
|
|
{ghv_87},
|
|
{ghv_86},
|
|
{ghv_85},
|
|
{ghv_84},
|
|
{ghv_83},
|
|
{ghv_82},
|
|
{ghv_81},
|
|
{ghv_80},
|
|
{ghv_79},
|
|
{ghv_78},
|
|
{ghv_77},
|
|
{ghv_76},
|
|
{ghv_75},
|
|
{ghv_74},
|
|
{ghv_73},
|
|
{ghv_72},
|
|
{ghv_71},
|
|
{ghv_70},
|
|
{ghv_69},
|
|
{ghv_68},
|
|
{ghv_67},
|
|
{ghv_66},
|
|
{ghv_65},
|
|
{ghv_64},
|
|
{ghv_63},
|
|
{ghv_62},
|
|
{ghv_61},
|
|
{ghv_60},
|
|
{ghv_59},
|
|
{ghv_58},
|
|
{ghv_57},
|
|
{ghv_56},
|
|
{ghv_55},
|
|
{ghv_54},
|
|
{ghv_53},
|
|
{ghv_52},
|
|
{ghv_51},
|
|
{ghv_50},
|
|
{ghv_49},
|
|
{ghv_48},
|
|
{ghv_47},
|
|
{ghv_46},
|
|
{ghv_45},
|
|
{ghv_44},
|
|
{ghv_43},
|
|
{ghv_42},
|
|
{ghv_41},
|
|
{ghv_40},
|
|
{ghv_39},
|
|
{ghv_38},
|
|
{ghv_37},
|
|
{ghv_36},
|
|
{ghv_35},
|
|
{ghv_34},
|
|
{ghv_33},
|
|
{ghv_32},
|
|
{ghv_31},
|
|
{ghv_30},
|
|
{ghv_29},
|
|
{ghv_28},
|
|
{ghv_27},
|
|
{ghv_26},
|
|
{ghv_25},
|
|
{ghv_24},
|
|
{ghv_23},
|
|
{ghv_22},
|
|
{ghv_21},
|
|
{ghv_20},
|
|
{ghv_19},
|
|
{ghv_18},
|
|
{ghv_17},
|
|
{ghv_16},
|
|
{ghv_15},
|
|
{ghv_14},
|
|
{ghv_13},
|
|
{ghv_12},
|
|
{ghv_11},
|
|
{ghv_10},
|
|
{ghv_9},
|
|
{ghv_8},
|
|
{ghv_7},
|
|
{ghv_6},
|
|
{ghv_5},
|
|
{ghv_4},
|
|
{ghv_3},
|
|
{ghv_2},
|
|
{ghv_1},
|
|
{ghv_0}}; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
wire s1_ahead_fh_ob_src_dup_1_afhob_0_bits_0 =
|
|
_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s1_ahead_fh_ob_src_dup_1_afhob_0_bits_2 =
|
|
_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s1_ahead_fh_ob_src_dup_1_afhob_0_bits_3 =
|
|
_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s1_ahead_fh_ob_src_dup_1_afhob_1_bits_0 =
|
|
_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s1_ahead_fh_ob_src_dup_2_afhob_0_bits_0 =
|
|
_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s1_ahead_fh_ob_src_dup_2_afhob_0_bits_2 =
|
|
_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s1_ahead_fh_ob_src_dup_2_afhob_0_bits_3 =
|
|
_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s1_ahead_fh_ob_src_dup_2_afhob_1_bits_0 =
|
|
_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s1_ahead_fh_ob_src_dup_3_afhob_0_bits_0 =
|
|
_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s1_ahead_fh_ob_src_dup_3_afhob_0_bits_2 =
|
|
_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s1_ahead_fh_ob_src_dup_3_afhob_0_bits_3 =
|
|
_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s1_ahead_fh_ob_src_dup_3_afhob_1_bits_0 =
|
|
_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s1_pred_info_takenMask_0_1 =
|
|
_predictors_io_out_s1_full_pred_0_slot_valids_1
|
|
& (_cfiIndex_bits_T_94 | ~_predictors_io_out_s1_full_pred_0_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire [38:0] _GEN_4 =
|
|
_predictors_io_out_s1_full_pred_0_hit
|
|
? 39'h0
|
|
: 39'(_predictors_io_out_s1_pc_0 + 39'h20); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47
|
|
wire s1_pred_info_takenMask_1_1 =
|
|
_predictors_io_out_s1_full_pred_1_slot_valids_1
|
|
& (_cfiIndex_bits_T_115 | ~_predictors_io_out_s1_full_pred_1_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire [38:0] _GEN_5 =
|
|
_predictors_io_out_s1_full_pred_1_hit
|
|
? 39'h0
|
|
: 39'(_predictors_io_out_s1_pc_1 + 39'h20); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47
|
|
wire s1_pred_info_takenMask_2_1 =
|
|
_predictors_io_out_s1_full_pred_2_slot_valids_1
|
|
& (_cfiIndex_bits_T_136 | ~_predictors_io_out_s1_full_pred_2_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire [38:0] _GEN_6 =
|
|
_predictors_io_out_s1_full_pred_2_hit
|
|
? 39'h0
|
|
: 39'(_predictors_io_out_s1_pc_2 + 39'h20); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47
|
|
wire s1_pred_info_takenMask_3_1 =
|
|
_predictors_io_out_s1_full_pred_3_slot_valids_1
|
|
& (_cfiIndex_bits_T_157 | ~_predictors_io_out_s1_full_pred_3_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire [38:0] _GEN_7 =
|
|
_predictors_io_out_s1_full_pred_3_hit
|
|
? 39'h0
|
|
: 39'(_predictors_io_out_s1_pc_3 + 39'h20); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47
|
|
wire _GEN_8 =
|
|
_predictors_io_out_s1_full_pred_1_slot_valids_0 | _s1_predicted_fh_dup_WIRE_21_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:41
|
|
wire _GEN_9 =
|
|
_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32
|
|
wire _GEN_10 = _GEN_9 | ~_s1_predicted_fh_dup_WIRE_21_1; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :488:{34,37}
|
|
wire _GEN_11 =
|
|
_predictors_io_out_s1_full_pred_2_slot_valids_0 | _s1_predicted_fh_dup_WIRE_35_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:41
|
|
wire _GEN_12 =
|
|
_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32
|
|
wire _GEN_13 = _GEN_12 | ~_s1_predicted_fh_dup_WIRE_35_1; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :488:{34,37}
|
|
wire _GEN_14 =
|
|
_predictors_io_out_s1_full_pred_3_slot_valids_0 | _s1_predicted_fh_dup_WIRE_49_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:41
|
|
wire _GEN_15 =
|
|
_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32
|
|
wire _GEN_16 = _GEN_15 | ~_s1_predicted_fh_dup_WIRE_49_1; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :488:{34,37}
|
|
wire _ghv_wens_0_T =
|
|
~(|s1_ghist_ptr_dup_0_value) & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_1_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_2_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_3_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_4_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_5_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_6_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_7_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_8_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_9_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_10_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_11_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_12_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_13_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_14_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_15_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h10 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_16_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h11 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_17_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h12 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_18_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h13 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_19_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h14 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_20_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h15 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_21_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h16 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_22_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h17 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_23_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h18 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_24_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h19 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_25_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_26_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1B & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_27_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1C & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_28_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1D & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_29_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1E & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_30_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h1F & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_31_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h20 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_32_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h21 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_33_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h22 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_34_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h23 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_35_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h24 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_36_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h25 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_37_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h26 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_38_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h27 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_39_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h28 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_40_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h29 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_41_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_42_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2B & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_43_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2C & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_44_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2D & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_45_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2E & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_46_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h2F & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_47_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h30 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_48_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h31 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_49_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h32 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_50_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h33 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_51_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h34 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_52_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h35 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_53_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h36 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_54_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h37 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_55_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h38 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_56_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h39 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_57_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_58_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3B & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_59_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3C & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_60_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3D & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_61_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3E & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_62_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h3F & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_63_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h40 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_64_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h41 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_65_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h42 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_66_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h43 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_67_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h44 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_68_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h45 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_69_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h46 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_70_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h47 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_71_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h48 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_72_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h49 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_73_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_74_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4B & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_75_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4C & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_76_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4D & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_77_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4E & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_78_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h4F & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_79_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h50 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_80_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h51 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_81_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h52 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_82_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h53 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_83_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h54 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_84_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h55 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_85_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h56 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_86_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h57 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_87_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h58 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_88_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h59 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_89_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_90_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5B & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_91_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5C & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_92_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5D & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_93_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5E & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_94_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h5F & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_95_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h60 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_96_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h61 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_97_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h62 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_98_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h63 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_99_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h64 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_100_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h65 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_101_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h66 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_102_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h67 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_103_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h68 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_104_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h69 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_105_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_106_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6B & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_107_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6C & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_108_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6D & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_109_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6E & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_110_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h6F & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_111_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h70 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_112_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h71 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_113_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h72 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_114_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h73 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_115_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h74 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_116_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h75 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_117_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h76 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_118_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h77 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_119_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h78 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_120_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h79 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_121_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_122_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7B & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_123_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7C & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_124_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7D & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_125_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7E & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_126_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h7F & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_127_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h80 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_128_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h81 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_129_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h82 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_130_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h83 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_131_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h84 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_132_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h85 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_133_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h86 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_134_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h87 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_135_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h88 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_136_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h89 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_137_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_138_T =
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s1_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s1_full_pred_0_slot_valids_0
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& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8B & _s1_ghv_wdatas_WIRE_44494_1
|
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& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
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& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_139_T =
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s1_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s1_full_pred_0_slot_valids_0
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& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8C & _s1_ghv_wdatas_WIRE_44494_1
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& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
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& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_140_T =
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s1_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s1_full_pred_0_slot_valids_0
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& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8D & _s1_ghv_wdatas_WIRE_44494_1
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& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
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& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_141_T =
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s1_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s1_full_pred_0_slot_valids_0
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& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8E & _s1_ghv_wdatas_WIRE_44494_1
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& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
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& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_142_T =
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s1_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s1_full_pred_0_slot_valids_0
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& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h8F & _s1_ghv_wdatas_WIRE_44494_1
|
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& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
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& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_143_T =
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s1_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s1_full_pred_0_slot_valids_0
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|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h90 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_144_T =
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|
s1_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h91 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_145_T =
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|
s1_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h92 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_146_T =
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|
s1_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h93 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_147_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h94 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_148_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h95 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_149_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h96 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_150_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h97 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_151_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h98 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_152_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h99 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_153_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_154_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9B & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_155_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9C & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_156_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9D & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_157_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9E & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_158_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'h9F & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_159_T =
|
|
s1_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA0 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_160_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA1 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_161_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA2 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_162_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA3 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_163_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA4 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_164_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA5 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_165_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA6 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_166_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA7 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_167_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA8 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_168_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hA9 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_169_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAA & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_170_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAB & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_171_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAC & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_172_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAD & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_173_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAE & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_174_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hAF & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_175_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB0 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_176_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB1 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_177_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB2 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_178_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB3 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_179_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB4 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_180_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB5 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_181_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB6 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_182_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB7 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_183_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB8 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_184_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hB9 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_185_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBA & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_186_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBB & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_187_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBC & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_188_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBD & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_189_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBE & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_190_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hBF & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_191_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC0 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_192_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC1 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_193_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC2 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_194_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC3 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_195_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC4 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_196_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC5 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_197_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC6 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_198_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC7 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_199_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC8 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_200_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hC9 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_201_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCA & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_202_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCB & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_203_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCC & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_204_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCD & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_205_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCE & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_206_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hCF & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_207_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD0 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_208_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD1 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_209_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD2 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_210_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD3 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_211_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD4 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_212_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD5 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_213_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD6 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_214_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD7 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_215_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD8 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_216_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hD9 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_217_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDA & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_218_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDB & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_219_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDC & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_220_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDD & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_221_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDE & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_222_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hDF & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_223_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE0 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_224_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE1 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_225_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE2 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_226_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE3 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
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wire _ghv_wens_227_T =
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s1_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s1_full_pred_0_slot_valids_0
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& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE4 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
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& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_228_T =
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s1_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s1_full_pred_0_slot_valids_0
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& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE5 & _s1_ghv_wdatas_WIRE_44494_1
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|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
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& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_229_T =
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s1_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s1_full_pred_0_slot_valids_0
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& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE6 & _s1_ghv_wdatas_WIRE_44494_1
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& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
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& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_230_T =
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s1_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s1_full_pred_0_slot_valids_0
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& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE7 & _s1_ghv_wdatas_WIRE_44494_1
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& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
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& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_231_T =
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s1_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
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& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE8 & _s1_ghv_wdatas_WIRE_44494_1
|
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& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
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& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_232_T =
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|
s1_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hE9 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_233_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEA & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_234_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEB & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_235_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEC & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_236_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hED & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_237_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEE & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_238_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hEF & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_239_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF0 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_240_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF1 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_241_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF2 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_242_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF3 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_243_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF4 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_244_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF5 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_245_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF6 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_246_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF7 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_247_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF8 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_248_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hF9 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_249_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFA & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_250_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFB & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_251_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFC & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_252_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFD & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_253_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | s1_ghist_ptr_dup_0_value == 8'hFE & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_254_T =
|
|
s1_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | (&s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_255_T =
|
|
(&s1_ghist_ptr_dup_0_value) & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& s1_valid_dup_3 | ~(|s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& s1_valid_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :323:35, :494:{58,129}, :516:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire [8:0] _GEN_17 = {s2_ghist_ptr_dup_0_flag, s2_ghist_ptr_dup_0_value}; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1 =
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|
9'(_GEN_17 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3 =
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|
9'(_GEN_17 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5 =
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|
9'(_GEN_17 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire [8:0] _GEN_18 = {s2_ghist_ptr_dup_1_flag, s2_ghist_ptr_dup_1_value}; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7 =
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|
9'(_GEN_18 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9 =
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|
9'(_GEN_18 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11 =
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|
9'(_GEN_18 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
wire [8:0] _GEN_19 = {s2_ghist_ptr_dup_2_flag, s2_ghist_ptr_dup_2_value}; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13 =
|
|
9'(_GEN_19 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15 =
|
|
9'(_GEN_19 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17 =
|
|
9'(_GEN_19 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
wire [8:0] _GEN_20 = {s2_ghist_ptr_dup_3_flag, s2_ghist_ptr_dup_3_value}; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19 =
|
|
9'(_GEN_20 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21 =
|
|
9'(_GEN_20 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23 =
|
|
9'(_GEN_20 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1 =
|
|
_predictors_io_out_s2_full_pred_0_slot_valids_1
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48
|
|
wire _s2_predicted_ghist_ptr_dup_WIRE_56_0_0 =
|
|
~_predictors_io_out_s2_full_pred_0_hit
|
|
| ~(_predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
| _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
wire _selVecOH_T_66 =
|
|
_predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
wire _cfiIndex_bits_T_262 =
|
|
_predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25
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|
wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53 =
|
|
_predictors_io_out_s2_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:474:27
|
|
wire _s2_predicted_ghist_ptr_dup_WIRE_56_0_1 =
|
|
_predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& (_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1)
|
|
& _predictors_io_out_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
|
|
wire _s2_predicted_ghist_ptr_dup_WIRE_56_0_2 =
|
|
_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _predictors_io_out_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
|
|
wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1 =
|
|
_predictors_io_out_s2_full_pred_1_slot_valids_1
|
|
& _predictors_io_out_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48
|
|
wire _s2_predicted_ghist_ptr_dup_WIRE_56_1_0 =
|
|
~_predictors_io_out_s2_full_pred_1_hit
|
|
| ~(_predictors_io_out_s2_full_pred_1_slot_valids_0
|
|
| _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
wire _selVecOH_T_74 =
|
|
_predictors_io_out_s2_full_pred_1_slot_valids_0
|
|
& _predictors_io_out_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
wire _cfiIndex_bits_T_283 =
|
|
_predictors_io_out_s2_full_pred_1_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25
|
|
wire _s2_predicted_ghist_ptr_dup_WIRE_56_1_1 =
|
|
_predictors_io_out_s2_full_pred_1_slot_valids_0
|
|
& (_selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit
|
|
| ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1)
|
|
& _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
|
|
wire _s2_predicted_ghist_ptr_dup_WIRE_56_1_2 =
|
|
_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1
|
|
& ~(_selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit)
|
|
& _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
|
|
wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1 =
|
|
_predictors_io_out_s2_full_pred_2_slot_valids_1
|
|
& _predictors_io_out_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48
|
|
wire _s2_predicted_ghist_ptr_dup_WIRE_56_2_0 =
|
|
~_predictors_io_out_s2_full_pred_2_hit
|
|
| ~(_predictors_io_out_s2_full_pred_2_slot_valids_0
|
|
| _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
wire _selVecOH_T_82 =
|
|
_predictors_io_out_s2_full_pred_2_slot_valids_0
|
|
& _predictors_io_out_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
wire _cfiIndex_bits_T_304 =
|
|
_predictors_io_out_s2_full_pred_2_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25
|
|
wire _s2_predicted_ghist_ptr_dup_WIRE_56_2_1 =
|
|
_predictors_io_out_s2_full_pred_2_slot_valids_0
|
|
& (_selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit
|
|
| ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1)
|
|
& _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
|
|
wire _s2_predicted_ghist_ptr_dup_WIRE_56_2_2 =
|
|
_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1
|
|
& ~(_selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit)
|
|
& _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
|
|
wire _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1 =
|
|
_predictors_io_out_s2_full_pred_3_slot_valids_1
|
|
& _predictors_io_out_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48
|
|
wire _s2_predicted_ghist_ptr_dup_WIRE_56_3_0 =
|
|
~_predictors_io_out_s2_full_pred_3_hit
|
|
| ~(_predictors_io_out_s2_full_pred_3_slot_valids_0
|
|
| _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
wire _selVecOH_T_90 =
|
|
_predictors_io_out_s2_full_pred_3_slot_valids_0
|
|
& _predictors_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
wire _cfiIndex_bits_T_325 =
|
|
_predictors_io_out_s2_full_pred_3_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25
|
|
wire _s2_predicted_ghist_ptr_dup_WIRE_56_3_1 =
|
|
_predictors_io_out_s2_full_pred_3_slot_valids_0
|
|
& (_selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit
|
|
| ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1)
|
|
& _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
|
|
wire _s2_predicted_ghist_ptr_dup_WIRE_56_3_2 =
|
|
_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1
|
|
& ~(_selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit)
|
|
& _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
|
|
wire _s2_predicted_fh_dup_WIRE_56_1_0 =
|
|
~_predictors_io_out_s2_full_pred_1_hit
|
|
| ~(_predictors_io_out_s2_full_pred_1_slot_valids_0
|
|
| _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
wire _s2_predicted_fh_dup_WIRE_56_1_1 =
|
|
_predictors_io_out_s2_full_pred_1_slot_valids_0
|
|
& (_selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit
|
|
| ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1)
|
|
& _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
|
|
wire _s2_predicted_fh_dup_WIRE_56_1_2 =
|
|
_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1
|
|
& ~(_selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit)
|
|
& _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
|
|
wire _s2_predicted_fh_dup_WIRE_56_2_0 =
|
|
~_predictors_io_out_s2_full_pred_2_hit
|
|
| ~(_predictors_io_out_s2_full_pred_2_slot_valids_0
|
|
| _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
wire _s2_predicted_fh_dup_WIRE_56_2_1 =
|
|
_predictors_io_out_s2_full_pred_2_slot_valids_0
|
|
& (_selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit
|
|
| ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1)
|
|
& _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
|
|
wire _s2_predicted_fh_dup_WIRE_56_2_2 =
|
|
_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1
|
|
& ~(_selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit)
|
|
& _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
|
|
wire _s2_predicted_fh_dup_WIRE_56_3_0 =
|
|
~_predictors_io_out_s2_full_pred_3_hit
|
|
| ~(_predictors_io_out_s2_full_pred_3_slot_valids_0
|
|
| _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
wire _s2_predicted_fh_dup_WIRE_56_3_1 =
|
|
_predictors_io_out_s2_full_pred_3_slot_valids_0
|
|
& (_selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit
|
|
| ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1)
|
|
& _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
|
|
wire _s2_predicted_fh_dup_WIRE_56_3_2 =
|
|
_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1
|
|
& ~(_selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit)
|
|
& _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
|
|
wire s2_ahead_fh_ob_src_dup_1_afhob_0_bits_0 =
|
|
_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s2_ahead_fh_ob_src_dup_1_afhob_0_bits_2 =
|
|
_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s2_ahead_fh_ob_src_dup_1_afhob_0_bits_3 =
|
|
_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s2_ahead_fh_ob_src_dup_1_afhob_1_bits_0 =
|
|
_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s2_ahead_fh_ob_src_dup_2_afhob_0_bits_0 =
|
|
_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s2_ahead_fh_ob_src_dup_2_afhob_0_bits_2 =
|
|
_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s2_ahead_fh_ob_src_dup_2_afhob_0_bits_3 =
|
|
_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s2_ahead_fh_ob_src_dup_2_afhob_1_bits_0 =
|
|
_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s2_ahead_fh_ob_src_dup_3_afhob_0_bits_0 =
|
|
_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s2_ahead_fh_ob_src_dup_3_afhob_0_bits_2 =
|
|
_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s2_ahead_fh_ob_src_dup_3_afhob_0_bits_3 =
|
|
_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s2_ahead_fh_ob_src_dup_3_afhob_1_bits_0 =
|
|
_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
reg previous_s1_pred_info_hit_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_hit_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_hit_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_hit_3; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg [38:0] previous_s1_pred_info_target_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg [38:0] previous_s1_pred_info_target_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg [38:0] previous_s1_pred_info_target_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg [38:0] previous_s1_pred_info_target_3; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_lastBrPosOH_0_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_lastBrPosOH_0_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_lastBrPosOH_0_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_lastBrPosOH_1_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_lastBrPosOH_1_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_lastBrPosOH_1_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_lastBrPosOH_2_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_lastBrPosOH_2_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_lastBrPosOH_2_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_lastBrPosOH_3_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_lastBrPosOH_3_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_lastBrPosOH_3_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_taken_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_taken_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_taken_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_taken_3; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_takenMask_0_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_takenMask_0_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_takenMask_1_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_takenMask_1_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_takenMask_2_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_takenMask_2_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_takenMask_3_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg previous_s1_pred_info_takenMask_3_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg [3:0] previous_s1_pred_info_cfiIndex_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg [3:0] previous_s1_pred_info_cfiIndex_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg [3:0] previous_s1_pred_info_cfiIndex_2; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
reg [3:0] previous_s1_pred_info_cfiIndex_3; // src/main/scala/xiangshan/frontend/BPU.scala:600:40
|
|
wire [38:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_0_3 =
|
|
39'(_predictors_io_out_s2_pc_0 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47
|
|
wire [38:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_1_3 =
|
|
39'(_predictors_io_out_s2_pc_1 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47
|
|
wire [38:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_2_3 =
|
|
39'(_predictors_io_out_s2_pc_2 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47
|
|
wire [38:0] _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_3_3 =
|
|
39'(_predictors_io_out_s2_pc_3 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47
|
|
assign s2_redirect_dup_0 =
|
|
s2_valid_dup_3
|
|
& (previous_s1_pred_info_takenMask_0_0 & previous_s1_pred_info_hit_0
|
|
& _predictors_io_out_s2_full_pred_0_targets_0 != previous_s1_pred_info_target_0
|
|
| ~previous_s1_pred_info_takenMask_0_0 & previous_s1_pred_info_takenMask_0_1
|
|
& previous_s1_pred_info_hit_0
|
|
& _predictors_io_out_s2_full_pred_0_targets_1 != previous_s1_pred_info_target_0
|
|
| {previous_s1_pred_info_takenMask_0_1,
|
|
previous_s1_pred_info_takenMask_0_0} == 2'h0 & previous_s1_pred_info_hit_0
|
|
& _predictors_io_out_s2_full_pred_0_fallThroughAddr != previous_s1_pred_info_target_0
|
|
| ~previous_s1_pred_info_hit_0
|
|
& _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_0_3 != previous_s1_pred_info_target_0
|
|
| {previous_s1_pred_info_lastBrPosOH_0_2,
|
|
previous_s1_pred_info_lastBrPosOH_0_1,
|
|
previous_s1_pred_info_lastBrPosOH_0_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66
|
|
& _predictors_io_out_s2_full_pred_0_hit)
|
|
& _predictors_io_out_s2_full_pred_0_hit,
|
|
_predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& (_selVecOH_T_66
|
|
& _predictors_io_out_s2_full_pred_0_hit
|
|
| ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1)
|
|
& _predictors_io_out_s2_full_pred_0_hit,
|
|
~_predictors_io_out_s2_full_pred_0_hit
|
|
| ~(_predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
| _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1)}
|
|
| previous_s1_pred_info_taken_0 != (|{_predictors_io_out_s2_full_pred_0_slot_valids_1
|
|
& (_cfiIndex_bits_T_262
|
|
| ~_predictors_io_out_s2_full_pred_0_is_br_sharing)
|
|
& _predictors_io_out_s2_full_pred_0_hit,
|
|
_selVecOH_T_66
|
|
& _predictors_io_out_s2_full_pred_0_hit})
|
|
| previous_s1_pred_info_taken_0
|
|
& (|{_predictors_io_out_s2_full_pred_0_slot_valids_1
|
|
& (_cfiIndex_bits_T_262 | ~_predictors_io_out_s2_full_pred_0_is_br_sharing)
|
|
& _predictors_io_out_s2_full_pred_0_hit,
|
|
_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit})
|
|
& previous_s1_pred_info_cfiIndex_0 != ((_selVecOH_T_66
|
|
& _predictors_io_out_s2_full_pred_0_hit
|
|
? _predictors_io_out_s2_full_pred_0_offsets_0
|
|
: _predictors_io_out_s2_full_pred_0_offsets_1)
|
|
| {4{{_predictors_io_out_s2_full_pred_0_slot_valids_1
|
|
& (_cfiIndex_bits_T_262
|
|
| ~_predictors_io_out_s2_full_pred_0_is_br_sharing)
|
|
& _predictors_io_out_s2_full_pred_0_hit,
|
|
_selVecOH_T_66
|
|
& _predictors_io_out_s2_full_pred_0_hit} == 2'h0}})); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :535:64, :542:{112,119,127}, :543:97, :544:{147,153}, :600:40, :605:{28,68}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:51, :421:{21,28,43}, :453:48, :458:69, :460:{25,47,50}, :467:38, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}, :505:47, :519:{46,53}, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77
|
|
wire s2_redirect_dup_1 =
|
|
s2_valid_dup_3
|
|
& (previous_s1_pred_info_takenMask_1_0 & previous_s1_pred_info_hit_1
|
|
& _predictors_io_out_s2_full_pred_1_targets_0 != previous_s1_pred_info_target_1
|
|
| ~previous_s1_pred_info_takenMask_1_0 & previous_s1_pred_info_takenMask_1_1
|
|
& previous_s1_pred_info_hit_1
|
|
& _predictors_io_out_s2_full_pred_1_targets_1 != previous_s1_pred_info_target_1
|
|
| {previous_s1_pred_info_takenMask_1_1,
|
|
previous_s1_pred_info_takenMask_1_0} == 2'h0 & previous_s1_pred_info_hit_1
|
|
& _predictors_io_out_s2_full_pred_1_fallThroughAddr != previous_s1_pred_info_target_1
|
|
| ~previous_s1_pred_info_hit_1
|
|
& _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_1_3 != previous_s1_pred_info_target_1
|
|
| {previous_s1_pred_info_lastBrPosOH_1_2,
|
|
previous_s1_pred_info_lastBrPosOH_1_1,
|
|
previous_s1_pred_info_lastBrPosOH_1_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1
|
|
& ~(_selVecOH_T_74
|
|
& _predictors_io_out_s2_full_pred_1_hit)
|
|
& _predictors_io_out_s2_full_pred_1_hit,
|
|
_predictors_io_out_s2_full_pred_1_slot_valids_0
|
|
& (_selVecOH_T_74
|
|
& _predictors_io_out_s2_full_pred_1_hit
|
|
| ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1)
|
|
& _predictors_io_out_s2_full_pred_1_hit,
|
|
~_predictors_io_out_s2_full_pred_1_hit
|
|
| ~(_predictors_io_out_s2_full_pred_1_slot_valids_0
|
|
| _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1)}
|
|
| previous_s1_pred_info_taken_1 != (|{_predictors_io_out_s2_full_pred_1_slot_valids_1
|
|
& (_cfiIndex_bits_T_283
|
|
| ~_predictors_io_out_s2_full_pred_1_is_br_sharing)
|
|
& _predictors_io_out_s2_full_pred_1_hit,
|
|
_selVecOH_T_74
|
|
& _predictors_io_out_s2_full_pred_1_hit})
|
|
| previous_s1_pred_info_taken_1
|
|
& (|{_predictors_io_out_s2_full_pred_1_slot_valids_1
|
|
& (_cfiIndex_bits_T_283 | ~_predictors_io_out_s2_full_pred_1_is_br_sharing)
|
|
& _predictors_io_out_s2_full_pred_1_hit,
|
|
_selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit})
|
|
& previous_s1_pred_info_cfiIndex_1 != ((_selVecOH_T_74
|
|
& _predictors_io_out_s2_full_pred_1_hit
|
|
? _predictors_io_out_s2_full_pred_1_offsets_0
|
|
: _predictors_io_out_s2_full_pred_1_offsets_1)
|
|
| {4{{_predictors_io_out_s2_full_pred_1_slot_valids_1
|
|
& (_cfiIndex_bits_T_283
|
|
| ~_predictors_io_out_s2_full_pred_1_is_br_sharing)
|
|
& _predictors_io_out_s2_full_pred_1_hit,
|
|
_selVecOH_T_74
|
|
& _predictors_io_out_s2_full_pred_1_hit} == 2'h0}})); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :535:64, :542:{112,119,127}, :543:97, :544:{147,153}, :600:40, :605:{28,68}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:51, :421:{21,28,43}, :453:48, :458:69, :460:{25,47,50}, :467:38, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}, :505:47, :519:{46,53}, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77
|
|
assign s2_redirect_dup_2 =
|
|
s2_valid_dup_3
|
|
& (previous_s1_pred_info_takenMask_2_0 & previous_s1_pred_info_hit_2
|
|
& _predictors_io_out_s2_full_pred_2_targets_0 != previous_s1_pred_info_target_2
|
|
| ~previous_s1_pred_info_takenMask_2_0 & previous_s1_pred_info_takenMask_2_1
|
|
& previous_s1_pred_info_hit_2
|
|
& _predictors_io_out_s2_full_pred_2_targets_1 != previous_s1_pred_info_target_2
|
|
| {previous_s1_pred_info_takenMask_2_1,
|
|
previous_s1_pred_info_takenMask_2_0} == 2'h0 & previous_s1_pred_info_hit_2
|
|
& _predictors_io_out_s2_full_pred_2_fallThroughAddr != previous_s1_pred_info_target_2
|
|
| ~previous_s1_pred_info_hit_2
|
|
& _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_2_3 != previous_s1_pred_info_target_2
|
|
| {previous_s1_pred_info_lastBrPosOH_2_2,
|
|
previous_s1_pred_info_lastBrPosOH_2_1,
|
|
previous_s1_pred_info_lastBrPosOH_2_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1
|
|
& ~(_selVecOH_T_82
|
|
& _predictors_io_out_s2_full_pred_2_hit)
|
|
& _predictors_io_out_s2_full_pred_2_hit,
|
|
_predictors_io_out_s2_full_pred_2_slot_valids_0
|
|
& (_selVecOH_T_82
|
|
& _predictors_io_out_s2_full_pred_2_hit
|
|
| ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1)
|
|
& _predictors_io_out_s2_full_pred_2_hit,
|
|
~_predictors_io_out_s2_full_pred_2_hit
|
|
| ~(_predictors_io_out_s2_full_pred_2_slot_valids_0
|
|
| _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1)}
|
|
| previous_s1_pred_info_taken_2 != (|{_predictors_io_out_s2_full_pred_2_slot_valids_1
|
|
& (_cfiIndex_bits_T_304
|
|
| ~_predictors_io_out_s2_full_pred_2_is_br_sharing)
|
|
& _predictors_io_out_s2_full_pred_2_hit,
|
|
_selVecOH_T_82
|
|
& _predictors_io_out_s2_full_pred_2_hit})
|
|
| previous_s1_pred_info_taken_2
|
|
& (|{_predictors_io_out_s2_full_pred_2_slot_valids_1
|
|
& (_cfiIndex_bits_T_304 | ~_predictors_io_out_s2_full_pred_2_is_br_sharing)
|
|
& _predictors_io_out_s2_full_pred_2_hit,
|
|
_selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit})
|
|
& previous_s1_pred_info_cfiIndex_2 != ((_selVecOH_T_82
|
|
& _predictors_io_out_s2_full_pred_2_hit
|
|
? _predictors_io_out_s2_full_pred_2_offsets_0
|
|
: _predictors_io_out_s2_full_pred_2_offsets_1)
|
|
| {4{{_predictors_io_out_s2_full_pred_2_slot_valids_1
|
|
& (_cfiIndex_bits_T_304
|
|
| ~_predictors_io_out_s2_full_pred_2_is_br_sharing)
|
|
& _predictors_io_out_s2_full_pred_2_hit,
|
|
_selVecOH_T_82
|
|
& _predictors_io_out_s2_full_pred_2_hit} == 2'h0}})); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :535:64, :542:{112,119,127}, :543:97, :544:{147,153}, :600:40, :605:{28,68}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:51, :421:{21,28,43}, :453:48, :458:69, :460:{25,47,50}, :467:38, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}, :505:47, :519:{46,53}, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77
|
|
wire s2_redirect_dup_3 =
|
|
s2_valid_dup_3
|
|
& (previous_s1_pred_info_takenMask_3_0 & previous_s1_pred_info_hit_3
|
|
& _predictors_io_out_s2_full_pred_3_targets_0 != previous_s1_pred_info_target_3
|
|
| ~previous_s1_pred_info_takenMask_3_0 & previous_s1_pred_info_takenMask_3_1
|
|
& previous_s1_pred_info_hit_3
|
|
& _predictors_io_out_s2_full_pred_3_targets_1 != previous_s1_pred_info_target_3
|
|
| {previous_s1_pred_info_takenMask_3_1,
|
|
previous_s1_pred_info_takenMask_3_0} == 2'h0 & previous_s1_pred_info_hit_3
|
|
& _predictors_io_out_s2_full_pred_3_fallThroughAddr != previous_s1_pred_info_target_3
|
|
| ~previous_s1_pred_info_hit_3
|
|
& _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_3_3 != previous_s1_pred_info_target_3
|
|
| {previous_s1_pred_info_lastBrPosOH_3_2,
|
|
previous_s1_pred_info_lastBrPosOH_3_1,
|
|
previous_s1_pred_info_lastBrPosOH_3_0} != {_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1
|
|
& ~(_selVecOH_T_90
|
|
& _predictors_io_out_s2_full_pred_3_hit)
|
|
& _predictors_io_out_s2_full_pred_3_hit,
|
|
_predictors_io_out_s2_full_pred_3_slot_valids_0
|
|
& (_selVecOH_T_90
|
|
& _predictors_io_out_s2_full_pred_3_hit
|
|
| ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1)
|
|
& _predictors_io_out_s2_full_pred_3_hit,
|
|
~_predictors_io_out_s2_full_pred_3_hit
|
|
| ~(_predictors_io_out_s2_full_pred_3_slot_valids_0
|
|
| _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1)}
|
|
| previous_s1_pred_info_taken_3 != (|{_predictors_io_out_s2_full_pred_3_slot_valids_1
|
|
& (_cfiIndex_bits_T_325
|
|
| ~_predictors_io_out_s2_full_pred_3_is_br_sharing)
|
|
& _predictors_io_out_s2_full_pred_3_hit,
|
|
_selVecOH_T_90
|
|
& _predictors_io_out_s2_full_pred_3_hit})
|
|
| previous_s1_pred_info_taken_3
|
|
& (|{_predictors_io_out_s2_full_pred_3_slot_valids_1
|
|
& (_cfiIndex_bits_T_325 | ~_predictors_io_out_s2_full_pred_3_is_br_sharing)
|
|
& _predictors_io_out_s2_full_pred_3_hit,
|
|
_selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit})
|
|
& previous_s1_pred_info_cfiIndex_3 != ((_selVecOH_T_90
|
|
& _predictors_io_out_s2_full_pred_3_hit
|
|
? _predictors_io_out_s2_full_pred_3_offsets_0
|
|
: _predictors_io_out_s2_full_pred_3_offsets_1)
|
|
| {4{{_predictors_io_out_s2_full_pred_3_slot_valids_1
|
|
& (_cfiIndex_bits_T_325
|
|
| ~_predictors_io_out_s2_full_pred_3_is_br_sharing)
|
|
& _predictors_io_out_s2_full_pred_3_hit,
|
|
_selVecOH_T_90
|
|
& _predictors_io_out_s2_full_pred_3_hit} == 2'h0}})); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :535:64, :542:{112,119,127}, :543:97, :544:{147,153}, :600:40, :605:{28,68}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:51, :421:{21,28,43}, :453:48, :458:69, :460:{25,47,50}, :467:38, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}, :505:47, :519:{46,53}, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77
|
|
wire _GEN_21 =
|
|
_predictors_io_out_s2_full_pred_0_slot_valids_1
|
|
& (_cfiIndex_bits_T_262 | ~_predictors_io_out_s2_full_pred_0_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire _GEN_22 =
|
|
_predictors_io_out_s2_full_pred_1_slot_valids_1
|
|
& (_cfiIndex_bits_T_283 | ~_predictors_io_out_s2_full_pred_1_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire _GEN_23 =
|
|
_predictors_io_out_s2_full_pred_2_slot_valids_1
|
|
& (_cfiIndex_bits_T_304 | ~_predictors_io_out_s2_full_pred_2_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire _GEN_24 =
|
|
_predictors_io_out_s2_full_pred_3_slot_valids_1
|
|
& (_cfiIndex_bits_T_325 | ~_predictors_io_out_s2_full_pred_3_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire _GEN_25 = _selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32
|
|
wire _GEN_26 = _selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32
|
|
wire _GEN_27 = _selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32
|
|
wire _ghv_wens_0_T_1 =
|
|
~(|s2_ghist_ptr_dup_0_value) & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_1_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_2_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_3_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_4_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_5_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_6_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_7_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_8_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_9_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_10_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_11_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_12_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_13_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_14_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_15_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h10
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_16_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h11
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_17_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h12
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_18_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h13
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_19_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h14
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_20_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h15
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_21_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h16
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_22_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h17
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_23_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h18
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_24_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h19
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_25_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_26_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_27_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_28_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_29_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_30_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h1F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_31_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h20
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_32_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h21
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_33_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h22
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_34_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h23
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_35_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h24
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_36_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h25
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_37_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h26
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_38_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h27
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_39_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h28
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_40_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h29
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_41_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_42_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_43_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_44_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_45_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_46_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h2F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_47_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h30
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_48_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h31
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_49_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h32
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_50_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h33
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_51_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h34
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_52_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h35
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_53_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h36
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_54_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h37
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_55_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h38
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_56_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h39
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_57_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_58_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_59_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_60_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_61_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_62_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h3F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_63_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h40
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_64_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h41
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_65_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h42
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_66_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h43
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_67_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h44
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_68_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h45
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_69_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h46
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_70_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h47
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_71_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h48
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_72_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h49
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_73_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_74_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_75_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_76_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_77_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_78_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h4F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_79_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h50
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_80_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h51
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_81_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h52
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_82_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h53
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_83_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h54
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_84_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h55
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_85_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h56
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_86_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h57
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_87_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h58
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_88_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h59
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_89_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_90_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_91_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_92_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_93_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_94_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h5F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_95_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h60
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_96_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h61
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_97_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h62
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_98_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h63
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_99_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h64
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_100_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h65
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_101_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h66
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_102_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h67
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_103_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h68
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_104_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h69
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_105_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_106_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_107_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_108_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_109_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_110_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h6F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_111_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h70
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_112_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h71
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_113_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h72
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_114_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h73
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_115_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h74
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_116_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h75
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_117_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h76
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_118_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h77
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_119_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h78
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_120_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h79
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_121_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_122_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_123_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_124_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_125_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_126_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h7F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_127_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h80
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_128_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h81
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_129_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h82
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_130_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h83
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_131_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h84
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_132_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h85
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_133_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h86
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_134_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h87
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_135_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h88
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_136_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h89
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_137_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_138_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_139_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_140_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_141_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_142_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h8F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_143_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h90
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_144_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h91
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_145_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h92
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_146_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h93
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_147_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h94
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_148_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h95
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_149_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h96
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_150_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h97
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_151_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h98
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_152_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h99
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_153_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_154_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_155_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_156_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_157_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_158_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'h9F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_159_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA0
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_160_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA1
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_161_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA2
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_162_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA3
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_163_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA4
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_164_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA5
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_165_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA6
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_166_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA7
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_167_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA8
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_168_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hA9
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_169_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAA
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_170_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAB
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_171_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAC
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_172_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAD
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_173_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAE
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_174_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hAF
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_175_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB0
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_176_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB1
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_177_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB2
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_178_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB3
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_179_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB4
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_180_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB5
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_181_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB6
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_182_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB7
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_183_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB8
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_184_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hB9
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_185_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBA
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_186_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBB
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_187_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBC
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_188_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBD
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_189_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBE
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_190_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hBF
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_191_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC0
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_192_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC1
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_193_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC2
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_194_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC3
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_195_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC4
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_196_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC5
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_197_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC6
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_198_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC7
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_199_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC8
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_200_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hC9
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_201_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCA
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_202_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCB
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_203_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCC
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_204_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCD
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_205_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCE
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_206_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hCF
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_207_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD0
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_208_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD1
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_209_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD2
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_210_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD3
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_211_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD4
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_212_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD5
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_213_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD6
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_214_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD7
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_215_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD8
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_216_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hD9
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_217_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDA
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_218_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDB
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_219_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDC
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_220_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDD
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_221_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDE
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_222_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hDF
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_223_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE0
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_224_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE1
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_225_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE2
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_226_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE3
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_227_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE4
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_228_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE5
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_229_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE6
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_230_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE7
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_231_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE8
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_232_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hE9
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_233_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEA
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_234_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEB
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_235_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEC
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_236_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hED
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_237_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEE
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_238_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hEF
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_239_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF0
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_240_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF1
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_241_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF2
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_242_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF3
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_243_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF4
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_244_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF5
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_245_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF6
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_246_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF7
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_247_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF8
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_248_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hF9
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_249_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFA
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_250_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFB
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_251_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFC
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_252_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFD
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_253_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | s2_ghist_ptr_dup_0_value == 8'hFE
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_254_T_1 =
|
|
s2_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | (&s2_ghist_ptr_dup_0_value)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_255_T_1 =
|
|
(&s2_ghist_ptr_dup_0_value) & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& s2_redirect_dup_0 | ~(|s2_ghist_ptr_dup_0_value)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit) & s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:{58,129}, :605:28, :619:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire [8:0] _GEN_28 = {s3_ghist_ptr_dup_0_flag, s3_ghist_ptr_dup_0_value}; // src/main/scala/xiangshan/frontend/BPU.scala:325:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1 =
|
|
9'(_GEN_28 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3 =
|
|
9'(_GEN_28 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5 =
|
|
9'(_GEN_28 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _GEN_29 = {s3_ghist_ptr_dup_1_flag, s3_ghist_ptr_dup_1_value}; // src/main/scala/xiangshan/frontend/BPU.scala:325:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7 =
|
|
9'(_GEN_29 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9 =
|
|
9'(_GEN_29 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11 =
|
|
9'(_GEN_29 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _GEN_30 = {s3_ghist_ptr_dup_2_flag, s3_ghist_ptr_dup_2_value}; // src/main/scala/xiangshan/frontend/BPU.scala:325:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13 =
|
|
9'(_GEN_30 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15 =
|
|
9'(_GEN_30 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17 =
|
|
9'(_GEN_30 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _GEN_31 = {s3_ghist_ptr_dup_3_flag, s3_ghist_ptr_dup_3_value}; // src/main/scala/xiangshan/frontend/BPU.scala:325:35, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19 =
|
|
9'(_GEN_31 - 9'h100); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21 =
|
|
9'(_GEN_31 + 9'hFF); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23 =
|
|
9'(_GEN_31 + 9'hFE); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire _s3_ghv_wdatas_WIRE_13797_1 =
|
|
_predictors_io_out_s3_full_pred_0_slot_valids_1
|
|
& _predictors_io_out_s3_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48
|
|
wire _s3_predicted_ghist_ptr_dup_WIRE_56_0_0 =
|
|
~_predictors_io_out_s3_full_pred_0_hit
|
|
| ~(_predictors_io_out_s3_full_pred_0_slot_valids_0 | _s3_ghv_wdatas_WIRE_13797_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
wire _selVecOH_T_98 =
|
|
_predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
wire _s3_redirect_on_jalr_target_dup_T_9 =
|
|
_predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25
|
|
wire _s3_both_first_taken_dup_T_7 =
|
|
_predictors_io_out_s3_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s3_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:474:27
|
|
wire _s3_predicted_ghist_ptr_dup_WIRE_56_0_1 =
|
|
_predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& (_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| ~_s3_ghv_wdatas_WIRE_13797_1) & _predictors_io_out_s3_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
|
|
wire _s3_predicted_ghist_ptr_dup_WIRE_56_0_2 =
|
|
_s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _predictors_io_out_s3_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
|
|
wire _s3_predicted_fh_dup_WIRE_21_1 =
|
|
_predictors_io_out_s3_full_pred_1_slot_valids_1
|
|
& _predictors_io_out_s3_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48
|
|
wire _s3_predicted_ghist_ptr_dup_WIRE_56_1_0 =
|
|
~_predictors_io_out_s3_full_pred_1_hit
|
|
| ~(_predictors_io_out_s3_full_pred_1_slot_valids_0 | _s3_predicted_fh_dup_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
wire _selVecOH_T_106 =
|
|
_predictors_io_out_s3_full_pred_1_slot_valids_0
|
|
& _predictors_io_out_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
wire _s3_redirect_on_jalr_target_dup_T_29 =
|
|
_predictors_io_out_s3_full_pred_1_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25
|
|
wire _s3_predicted_ghist_ptr_dup_WIRE_56_1_1 =
|
|
_predictors_io_out_s3_full_pred_1_slot_valids_0
|
|
& (_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit
|
|
| ~_s3_predicted_fh_dup_WIRE_21_1) & _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
|
|
wire _s3_predicted_ghist_ptr_dup_WIRE_56_1_2 =
|
|
_s3_predicted_fh_dup_WIRE_21_1
|
|
& ~(_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit)
|
|
& _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
|
|
wire _s3_predicted_fh_dup_WIRE_35_1 =
|
|
_predictors_io_out_s3_full_pred_2_slot_valids_1
|
|
& _predictors_io_out_s3_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48
|
|
wire _s3_predicted_ghist_ptr_dup_WIRE_56_2_0 =
|
|
~_predictors_io_out_s3_full_pred_2_hit
|
|
| ~(_predictors_io_out_s3_full_pred_2_slot_valids_0 | _s3_predicted_fh_dup_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
wire _selVecOH_T_114 =
|
|
_predictors_io_out_s3_full_pred_2_slot_valids_0
|
|
& _predictors_io_out_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
wire _s3_redirect_on_jalr_target_dup_T_49 =
|
|
_predictors_io_out_s3_full_pred_2_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25
|
|
wire _s3_predicted_ghist_ptr_dup_WIRE_56_2_1 =
|
|
_predictors_io_out_s3_full_pred_2_slot_valids_0
|
|
& (_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit
|
|
| ~_s3_predicted_fh_dup_WIRE_35_1) & _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
|
|
wire _s3_predicted_ghist_ptr_dup_WIRE_56_2_2 =
|
|
_s3_predicted_fh_dup_WIRE_35_1
|
|
& ~(_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit)
|
|
& _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
|
|
wire _s3_predicted_fh_dup_WIRE_49_1 =
|
|
_predictors_io_out_s3_full_pred_3_slot_valids_1
|
|
& _predictors_io_out_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48
|
|
wire _s3_predicted_ghist_ptr_dup_WIRE_56_3_0 =
|
|
~_predictors_io_out_s3_full_pred_3_hit
|
|
| ~(_predictors_io_out_s3_full_pred_3_slot_valids_0 | _s3_predicted_fh_dup_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
wire _selVecOH_T_122 =
|
|
_predictors_io_out_s3_full_pred_3_slot_valids_0
|
|
& _predictors_io_out_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
wire _s3_redirect_on_jalr_target_dup_T_69 =
|
|
_predictors_io_out_s3_full_pred_3_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25
|
|
wire _s3_predicted_ghist_ptr_dup_WIRE_56_3_1 =
|
|
_predictors_io_out_s3_full_pred_3_slot_valids_0
|
|
& (_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit
|
|
| ~_s3_predicted_fh_dup_WIRE_49_1) & _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
|
|
wire _s3_predicted_ghist_ptr_dup_WIRE_56_3_2 =
|
|
_s3_predicted_fh_dup_WIRE_49_1
|
|
& ~(_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit)
|
|
& _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
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|
wire _s3_predicted_fh_dup_WIRE_56_1_0 =
|
|
~_predictors_io_out_s3_full_pred_1_hit
|
|
| ~(_predictors_io_out_s3_full_pred_1_slot_valids_0 | _s3_predicted_fh_dup_WIRE_21_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
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|
wire _s3_predicted_fh_dup_WIRE_56_1_1 =
|
|
_predictors_io_out_s3_full_pred_1_slot_valids_0
|
|
& (_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit
|
|
| ~_s3_predicted_fh_dup_WIRE_21_1) & _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
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wire _s3_predicted_fh_dup_WIRE_56_1_2 =
|
|
_s3_predicted_fh_dup_WIRE_21_1
|
|
& ~(_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit)
|
|
& _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
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|
wire _s3_predicted_fh_dup_WIRE_56_2_0 =
|
|
~_predictors_io_out_s3_full_pred_2_hit
|
|
| ~(_predictors_io_out_s3_full_pred_2_slot_valids_0 | _s3_predicted_fh_dup_WIRE_35_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
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wire _s3_predicted_fh_dup_WIRE_56_2_1 =
|
|
_predictors_io_out_s3_full_pred_2_slot_valids_0
|
|
& (_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit
|
|
| ~_s3_predicted_fh_dup_WIRE_35_1) & _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
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wire _s3_predicted_fh_dup_WIRE_56_2_2 =
|
|
_s3_predicted_fh_dup_WIRE_35_1
|
|
& ~(_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit)
|
|
& _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
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wire _s3_predicted_fh_dup_WIRE_56_3_0 =
|
|
~_predictors_io_out_s3_full_pred_3_hit
|
|
| ~(_predictors_io_out_s3_full_pred_3_slot_valids_0 | _s3_predicted_fh_dup_WIRE_49_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
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|
wire _s3_predicted_fh_dup_WIRE_56_3_1 =
|
|
_predictors_io_out_s3_full_pred_3_slot_valids_0
|
|
& (_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit
|
|
| ~_s3_predicted_fh_dup_WIRE_49_1) & _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :488:{34,37,97}
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|
wire _s3_predicted_fh_dup_WIRE_56_3_2 =
|
|
_s3_predicted_fh_dup_WIRE_49_1
|
|
& ~(_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit)
|
|
& _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :487:9, :488:97
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|
wire s3_ahead_fh_ob_src_dup_1_afhob_0_bits_0 =
|
|
_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
wire s3_ahead_fh_ob_src_dup_1_afhob_0_bits_2 =
|
|
_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s3_ahead_fh_ob_src_dup_1_afhob_0_bits_3 =
|
|
_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s3_ahead_fh_ob_src_dup_1_afhob_1_bits_0 =
|
|
_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s3_ahead_fh_ob_src_dup_2_afhob_0_bits_0 =
|
|
_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s3_ahead_fh_ob_src_dup_2_afhob_0_bits_2 =
|
|
_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s3_ahead_fh_ob_src_dup_2_afhob_0_bits_3 =
|
|
_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s3_ahead_fh_ob_src_dup_2_afhob_1_bits_0 =
|
|
_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s3_ahead_fh_ob_src_dup_3_afhob_0_bits_0 =
|
|
_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s3_ahead_fh_ob_src_dup_3_afhob_0_bits_2 =
|
|
_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s3_ahead_fh_ob_src_dup_3_afhob_0_bits_3 =
|
|
_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire s3_ahead_fh_ob_src_dup_3_afhob_1_bits_0 =
|
|
_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
reg [38:0] previous_s2_pred_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg [38:0] previous_s2_pred_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg [38:0] previous_s2_pred_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg [38:0] previous_s2_pred_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg [38:0] previous_s2_pred_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg [38:0] previous_s2_pred_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg [38:0] previous_s2_pred_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg [38:0] previous_s2_pred_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg [38:0] previous_s2_pred_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg [38:0] previous_s2_pred_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg [38:0] previous_s2_pred_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg [38:0] previous_s2_pred_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg [38:0] previous_s2_pred_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg [38:0] previous_s2_pred_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg [38:0] previous_s2_pred_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg [38:0] previous_s2_pred_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
reg previous_s2_pred_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:673:35
|
|
wire _s3_redirect_on_target_dup_selVecOH_T_34 =
|
|
previous_s2_pred_full_pred_0_slot_valids_0
|
|
& previous_s2_pred_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
wire _s3_redirect_on_target_dup_selVecOH_T_42 =
|
|
previous_s2_pred_full_pred_1_slot_valids_0
|
|
& previous_s2_pred_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
wire _s3_redirect_on_target_dup_selVecOH_T_50 =
|
|
previous_s2_pred_full_pred_2_slot_valids_0
|
|
& previous_s2_pred_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
wire _s3_redirect_on_target_dup_selVecOH_T_58 =
|
|
previous_s2_pred_full_pred_3_slot_valids_0
|
|
& previous_s2_pred_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
wire _s3_redirect_on_target_dup_WIRE_1 =
|
|
_predictors_io_out_s3_full_pred_0_slot_valids_1
|
|
& (_s3_redirect_on_jalr_target_dup_T_9
|
|
| ~_predictors_io_out_s3_full_pred_0_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire [38:0] _s3_redirect_on_target_dup_WIRE_1_3 =
|
|
39'(_predictors_io_out_s3_pc_0 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47
|
|
wire _s3_redirect_on_target_dup_WIRE_3_1 =
|
|
_predictors_io_out_s3_full_pred_1_slot_valids_1
|
|
& (_s3_redirect_on_jalr_target_dup_T_29
|
|
| ~_predictors_io_out_s3_full_pred_1_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire [38:0] _s3_redirect_on_target_dup_WIRE_4_3 =
|
|
39'(_predictors_io_out_s3_pc_1 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47
|
|
wire _s3_redirect_on_target_dup_WIRE_6_1 =
|
|
_predictors_io_out_s3_full_pred_2_slot_valids_1
|
|
& (_s3_redirect_on_jalr_target_dup_T_49
|
|
| ~_predictors_io_out_s3_full_pred_2_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire [38:0] _s3_redirect_on_target_dup_WIRE_7_3 =
|
|
39'(_predictors_io_out_s3_pc_2 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47
|
|
wire _s3_redirect_on_target_dup_WIRE_9_1 =
|
|
_predictors_io_out_s3_full_pred_3_slot_valids_1
|
|
& (_s3_redirect_on_jalr_target_dup_T_69
|
|
| ~_predictors_io_out_s3_full_pred_3_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire [38:0] _s3_redirect_on_target_dup_WIRE_10_3 =
|
|
39'(_predictors_io_out_s3_pc_3 + 39'h20); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:505:47
|
|
wire _s3_redirect_on_target_dup_WIRE_13_1 =
|
|
previous_s2_pred_full_pred_0_slot_valids_1
|
|
& (previous_s2_pred_full_pred_0_is_br_sharing
|
|
& previous_s2_pred_full_pred_0_br_taken_mask_1
|
|
| ~previous_s2_pred_full_pred_0_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire _s3_redirect_on_target_dup_WIRE_16_1 =
|
|
previous_s2_pred_full_pred_1_slot_valids_1
|
|
& (previous_s2_pred_full_pred_1_is_br_sharing
|
|
& previous_s2_pred_full_pred_1_br_taken_mask_1
|
|
| ~previous_s2_pred_full_pred_1_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire _s3_redirect_on_target_dup_WIRE_19_1 =
|
|
previous_s2_pred_full_pred_2_slot_valids_1
|
|
& (previous_s2_pred_full_pred_2_is_br_sharing
|
|
& previous_s2_pred_full_pred_2_br_taken_mask_1
|
|
| ~previous_s2_pred_full_pred_2_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire _s3_redirect_on_target_dup_WIRE_22_1 =
|
|
previous_s2_pred_full_pred_3_slot_valids_1
|
|
& (previous_s2_pred_full_pred_3_is_br_sharing
|
|
& previous_s2_pred_full_pred_3_br_taken_mask_1
|
|
| ~previous_s2_pred_full_pred_3_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:673:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
assign s3_redirect_dup_0 =
|
|
s3_valid_dup_3
|
|
& ({_s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit,
|
|
_selVecOH_T_98
|
|
& _predictors_io_out_s3_full_pred_0_hit} != {previous_s2_pred_full_pred_0_br_taken_mask_1
|
|
& previous_s2_pred_full_pred_0_slot_valids_1
|
|
& previous_s2_pred_full_pred_0_is_br_sharing
|
|
& previous_s2_pred_full_pred_0_hit,
|
|
_s3_redirect_on_target_dup_selVecOH_T_34
|
|
& previous_s2_pred_full_pred_0_hit}
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
& _s3_redirect_on_target_dup_selVecOH_T_34 & previous_s2_pred_full_pred_0_hit)
|
|
| ((_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
? _predictors_io_out_s3_full_pred_0_targets_0
|
|
: 39'h0)
|
|
| (~_selVecOH_T_98 & _s3_redirect_on_target_dup_WIRE_1
|
|
& _predictors_io_out_s3_full_pred_0_hit
|
|
? _predictors_io_out_s3_full_pred_0_targets_1
|
|
: 39'h0)
|
|
| ({_s3_redirect_on_target_dup_WIRE_1, _selVecOH_T_98} == 2'h0
|
|
& _predictors_io_out_s3_full_pred_0_hit
|
|
? _predictors_io_out_s3_full_pred_0_fallThroughAddr
|
|
: 39'h0)
|
|
| (_predictors_io_out_s3_full_pred_0_hit
|
|
? 39'h0
|
|
: _s3_redirect_on_target_dup_WIRE_1_3)) != ((_s3_redirect_on_target_dup_selVecOH_T_34
|
|
& previous_s2_pred_full_pred_0_hit
|
|
? previous_s2_pred_full_pred_0_targets_0
|
|
: 39'h0)
|
|
| (~_s3_redirect_on_target_dup_selVecOH_T_34
|
|
& _s3_redirect_on_target_dup_WIRE_13_1
|
|
& previous_s2_pred_full_pred_0_hit
|
|
? previous_s2_pred_full_pred_0_targets_1
|
|
: 39'h0)
|
|
| ({_s3_redirect_on_target_dup_WIRE_13_1,
|
|
_s3_redirect_on_target_dup_selVecOH_T_34} == 2'h0
|
|
& previous_s2_pred_full_pred_0_hit
|
|
? previous_s2_pred_full_pred_0_fallThroughAddr
|
|
: 39'h0)
|
|
| (previous_s2_pred_full_pred_0_hit
|
|
? 39'h0
|
|
: 39'(previous_s2_pred_pc_0
|
|
+ 39'h20)))
|
|
| _predictors_io_out_s3_full_pred_0_hit
|
|
& _predictors_io_out_s3_full_pred_0_fallThroughErr); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :673:35, :675:{136,143,172}, :676:135, :677:110, :684:28, :685:{32,35,82}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :473:32, :474:{27,63}, :505:47, :508:33
|
|
wire s3_redirect_dup_1 =
|
|
s3_valid_dup_3
|
|
& ({_predictors_io_out_s3_full_pred_1_br_taken_mask_1
|
|
& _predictors_io_out_s3_full_pred_1_slot_valids_1
|
|
& _predictors_io_out_s3_full_pred_1_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_1_hit,
|
|
_selVecOH_T_106
|
|
& _predictors_io_out_s3_full_pred_1_hit} != {previous_s2_pred_full_pred_1_br_taken_mask_1
|
|
& previous_s2_pred_full_pred_1_slot_valids_1
|
|
& previous_s2_pred_full_pred_1_is_br_sharing
|
|
& previous_s2_pred_full_pred_1_hit,
|
|
_s3_redirect_on_target_dup_selVecOH_T_42
|
|
& previous_s2_pred_full_pred_1_hit}
|
|
& ~(_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit
|
|
& _s3_redirect_on_target_dup_selVecOH_T_42 & previous_s2_pred_full_pred_1_hit)
|
|
| ((_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit
|
|
? _predictors_io_out_s3_full_pred_1_targets_0
|
|
: 39'h0)
|
|
| (~_selVecOH_T_106 & _s3_redirect_on_target_dup_WIRE_3_1
|
|
& _predictors_io_out_s3_full_pred_1_hit
|
|
? _predictors_io_out_s3_full_pred_1_targets_1
|
|
: 39'h0)
|
|
| ({_s3_redirect_on_target_dup_WIRE_3_1, _selVecOH_T_106} == 2'h0
|
|
& _predictors_io_out_s3_full_pred_1_hit
|
|
? _predictors_io_out_s3_full_pred_1_fallThroughAddr
|
|
: 39'h0)
|
|
| (_predictors_io_out_s3_full_pred_1_hit
|
|
? 39'h0
|
|
: _s3_redirect_on_target_dup_WIRE_4_3)) != ((_s3_redirect_on_target_dup_selVecOH_T_42
|
|
& previous_s2_pred_full_pred_1_hit
|
|
? previous_s2_pred_full_pred_1_targets_0
|
|
: 39'h0)
|
|
| (~_s3_redirect_on_target_dup_selVecOH_T_42
|
|
& _s3_redirect_on_target_dup_WIRE_16_1
|
|
& previous_s2_pred_full_pred_1_hit
|
|
? previous_s2_pred_full_pred_1_targets_1
|
|
: 39'h0)
|
|
| ({_s3_redirect_on_target_dup_WIRE_16_1,
|
|
_s3_redirect_on_target_dup_selVecOH_T_42} == 2'h0
|
|
& previous_s2_pred_full_pred_1_hit
|
|
? previous_s2_pred_full_pred_1_fallThroughAddr
|
|
: 39'h0)
|
|
| (previous_s2_pred_full_pred_1_hit
|
|
? 39'h0
|
|
: 39'(previous_s2_pred_pc_1
|
|
+ 39'h20)))
|
|
| _predictors_io_out_s3_full_pred_1_hit
|
|
& _predictors_io_out_s3_full_pred_1_fallThroughErr); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :673:35, :675:{136,143,172}, :676:135, :677:110, :684:28, :685:{32,35,82}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :473:32, :474:63, :505:47, :508:33
|
|
assign s3_redirect_dup_2 =
|
|
s3_valid_dup_3
|
|
& ({_predictors_io_out_s3_full_pred_2_br_taken_mask_1
|
|
& _predictors_io_out_s3_full_pred_2_slot_valids_1
|
|
& _predictors_io_out_s3_full_pred_2_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_2_hit,
|
|
_selVecOH_T_114
|
|
& _predictors_io_out_s3_full_pred_2_hit} != {previous_s2_pred_full_pred_2_br_taken_mask_1
|
|
& previous_s2_pred_full_pred_2_slot_valids_1
|
|
& previous_s2_pred_full_pred_2_is_br_sharing
|
|
& previous_s2_pred_full_pred_2_hit,
|
|
_s3_redirect_on_target_dup_selVecOH_T_50
|
|
& previous_s2_pred_full_pred_2_hit}
|
|
& ~(_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit
|
|
& _s3_redirect_on_target_dup_selVecOH_T_50 & previous_s2_pred_full_pred_2_hit)
|
|
| ((_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit
|
|
? _predictors_io_out_s3_full_pred_2_targets_0
|
|
: 39'h0)
|
|
| (~_selVecOH_T_114 & _s3_redirect_on_target_dup_WIRE_6_1
|
|
& _predictors_io_out_s3_full_pred_2_hit
|
|
? _predictors_io_out_s3_full_pred_2_targets_1
|
|
: 39'h0)
|
|
| ({_s3_redirect_on_target_dup_WIRE_6_1, _selVecOH_T_114} == 2'h0
|
|
& _predictors_io_out_s3_full_pred_2_hit
|
|
? _predictors_io_out_s3_full_pred_2_fallThroughAddr
|
|
: 39'h0)
|
|
| (_predictors_io_out_s3_full_pred_2_hit
|
|
? 39'h0
|
|
: _s3_redirect_on_target_dup_WIRE_7_3)) != ((_s3_redirect_on_target_dup_selVecOH_T_50
|
|
& previous_s2_pred_full_pred_2_hit
|
|
? previous_s2_pred_full_pred_2_targets_0
|
|
: 39'h0)
|
|
| (~_s3_redirect_on_target_dup_selVecOH_T_50
|
|
& _s3_redirect_on_target_dup_WIRE_19_1
|
|
& previous_s2_pred_full_pred_2_hit
|
|
? previous_s2_pred_full_pred_2_targets_1
|
|
: 39'h0)
|
|
| ({_s3_redirect_on_target_dup_WIRE_19_1,
|
|
_s3_redirect_on_target_dup_selVecOH_T_50} == 2'h0
|
|
& previous_s2_pred_full_pred_2_hit
|
|
? previous_s2_pred_full_pred_2_fallThroughAddr
|
|
: 39'h0)
|
|
| (previous_s2_pred_full_pred_2_hit
|
|
? 39'h0
|
|
: 39'(previous_s2_pred_pc_2
|
|
+ 39'h20)))
|
|
| _predictors_io_out_s3_full_pred_2_hit
|
|
& _predictors_io_out_s3_full_pred_2_fallThroughErr); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :673:35, :675:{136,143,172}, :676:135, :677:110, :684:28, :685:{32,35,82}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :473:32, :474:63, :505:47, :508:33
|
|
assign s3_redirect_dup_3 =
|
|
s3_valid_dup_3
|
|
& ({_predictors_io_out_s3_full_pred_3_br_taken_mask_1
|
|
& _predictors_io_out_s3_full_pred_3_slot_valids_1
|
|
& _predictors_io_out_s3_full_pred_3_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_3_hit,
|
|
_selVecOH_T_122
|
|
& _predictors_io_out_s3_full_pred_3_hit} != {previous_s2_pred_full_pred_3_br_taken_mask_1
|
|
& previous_s2_pred_full_pred_3_slot_valids_1
|
|
& previous_s2_pred_full_pred_3_is_br_sharing
|
|
& previous_s2_pred_full_pred_3_hit,
|
|
_s3_redirect_on_target_dup_selVecOH_T_58
|
|
& previous_s2_pred_full_pred_3_hit}
|
|
& ~(_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit
|
|
& _s3_redirect_on_target_dup_selVecOH_T_58 & previous_s2_pred_full_pred_3_hit)
|
|
| ((_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit
|
|
? _predictors_io_out_s3_full_pred_3_targets_0
|
|
: 39'h0)
|
|
| (~_selVecOH_T_122 & _s3_redirect_on_target_dup_WIRE_9_1
|
|
& _predictors_io_out_s3_full_pred_3_hit
|
|
? _predictors_io_out_s3_full_pred_3_targets_1
|
|
: 39'h0)
|
|
| ({_s3_redirect_on_target_dup_WIRE_9_1, _selVecOH_T_122} == 2'h0
|
|
& _predictors_io_out_s3_full_pred_3_hit
|
|
? _predictors_io_out_s3_full_pred_3_fallThroughAddr
|
|
: 39'h0)
|
|
| (_predictors_io_out_s3_full_pred_3_hit
|
|
? 39'h0
|
|
: _s3_redirect_on_target_dup_WIRE_10_3)) != ((_s3_redirect_on_target_dup_selVecOH_T_58
|
|
& previous_s2_pred_full_pred_3_hit
|
|
? previous_s2_pred_full_pred_3_targets_0
|
|
: 39'h0)
|
|
| (~_s3_redirect_on_target_dup_selVecOH_T_58
|
|
& _s3_redirect_on_target_dup_WIRE_22_1
|
|
& previous_s2_pred_full_pred_3_hit
|
|
? previous_s2_pred_full_pred_3_targets_1
|
|
: 39'h0)
|
|
| ({_s3_redirect_on_target_dup_WIRE_22_1,
|
|
_s3_redirect_on_target_dup_selVecOH_T_58} == 2'h0
|
|
& previous_s2_pred_full_pred_3_hit
|
|
? previous_s2_pred_full_pred_3_fallThroughAddr
|
|
: 39'h0)
|
|
| (previous_s2_pred_full_pred_3_hit
|
|
? 39'h0
|
|
: 39'(previous_s2_pred_pc_3
|
|
+ 39'h20)))
|
|
| _predictors_io_out_s3_full_pred_3_hit
|
|
& _predictors_io_out_s3_full_pred_3_fallThroughErr); // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :271:65, :343:53, :673:35, :675:{136,143,172}, :676:135, :677:110, :684:28, :685:{32,35,82}, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :473:32, :474:63, :505:47, :508:33
|
|
wire _GEN_32 =
|
|
_predictors_io_out_s3_full_pred_0_slot_valids_1
|
|
& (_s3_redirect_on_jalr_target_dup_T_9
|
|
| ~_predictors_io_out_s3_full_pred_0_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire _GEN_33 =
|
|
_predictors_io_out_s3_full_pred_1_slot_valids_1
|
|
& (_s3_redirect_on_jalr_target_dup_T_29
|
|
| ~_predictors_io_out_s3_full_pred_1_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire _GEN_34 =
|
|
_predictors_io_out_s3_full_pred_2_slot_valids_1
|
|
& (_s3_redirect_on_jalr_target_dup_T_49
|
|
| ~_predictors_io_out_s3_full_pred_2_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire _GEN_35 =
|
|
_predictors_io_out_s3_full_pred_3_slot_valids_1
|
|
& (_s3_redirect_on_jalr_target_dup_T_69
|
|
| ~_predictors_io_out_s3_full_pred_3_is_br_sharing); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25, :460:{25,47,50}
|
|
wire _GEN_36 = _selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32
|
|
wire _GEN_37 = _selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32
|
|
wire _GEN_38 = _selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32
|
|
wire _ghv_wens_0_T_2 =
|
|
~(|s3_ghist_ptr_dup_0_value) & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_1_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_2_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_3_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_4_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_5_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_6_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_7_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
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& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_8_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_9_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_10_T_2 =
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s3_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s3_full_pred_0_slot_valids_0
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|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_11_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_12_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_13_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_14_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_15_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h10 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_16_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h11 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_17_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h12 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_18_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h13 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_19_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h14 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_20_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h15 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_21_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h16 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_22_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h17 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_23_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h18 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_24_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h19 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_25_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1A & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_26_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1B & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_27_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_28_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_29_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_30_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h1F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_31_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h20 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_32_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h21 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_33_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h22 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_34_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h23 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_35_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h24 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_36_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h25 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_37_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h26 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_38_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h27 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_39_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h28 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_40_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h29 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_41_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2A & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_42_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2B & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_43_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_44_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_45_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_46_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h2F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_47_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h30 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_48_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h31 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_49_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h32 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_50_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h33 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_51_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h34 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_52_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h35 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_53_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h36 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_54_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h37 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_55_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h38 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_56_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h39 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_57_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3A & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_58_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3B & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_59_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_60_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_61_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_62_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h3F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_63_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h40 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_64_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h41 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_65_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h42 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_66_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h43 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_67_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h44 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_68_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h45 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_69_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
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& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h46 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_70_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
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& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h47 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_71_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h48 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_72_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h49 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_73_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4A & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_74_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4B & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_75_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_76_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_77_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_78_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h4F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_79_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h50 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_80_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h51 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_81_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h52 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_82_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h53 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_83_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h54 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_84_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h55 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_85_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h56 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_86_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h57 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_87_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h58 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_88_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h59 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_89_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5A & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_90_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5B & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_91_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_92_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_93_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_94_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h5F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_95_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h60 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_96_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h61 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_97_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h62 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_98_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h63 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_99_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h64 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_100_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
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& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h65 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_101_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h66 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_102_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h67 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_103_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h68 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_104_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h69 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_105_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6A & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_106_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6B & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_107_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_108_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_109_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_110_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h6F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_111_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h70 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_112_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h71 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_113_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h72 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_114_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h73 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_115_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h74 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_116_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h75 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_117_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h76 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_118_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h77 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_119_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h78 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_120_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h79 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_121_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7A & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_122_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7B & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_123_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_124_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_125_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_126_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h7F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_127_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h80 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_128_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h81 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_129_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h82 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_130_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h83 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_131_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h84 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_132_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h85 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_133_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h86 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_134_T_2 =
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s3_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h87 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_135_T_2 =
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s3_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h88 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_136_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h89 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_137_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8A & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_138_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8B & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_139_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_140_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_141_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_142_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h8F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_143_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h90 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_144_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h91 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_145_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h92 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_146_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h93 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_147_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h94 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_148_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h95 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_149_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h96 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_150_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h97 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_151_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h98 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_152_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h99 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_153_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9A & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_154_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9B & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_155_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_156_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_157_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_158_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'h9F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_159_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA0 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_160_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA1 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_161_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA2 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_162_T_2 =
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s3_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA3 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_163_T_2 =
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s3_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA4 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_164_T_2 =
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s3_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA5 & _s3_ghv_wdatas_WIRE_13797_1
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& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_165_T_2 =
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s3_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA6 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_166_T_2 =
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s3_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA7 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_167_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA8 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_168_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hA9 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_169_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAA & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_170_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAB & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_171_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAC & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_172_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAD & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_173_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAE & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_174_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hAF & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_175_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB0 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_176_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB1 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_177_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB2 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_178_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB3 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_179_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB4 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_180_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB5 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_181_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB6 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_182_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB7 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_183_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB8 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_184_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hB9 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_185_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBA & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_186_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBB & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_187_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBC & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_188_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBD & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_189_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBE & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_190_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hBF & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_191_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC0 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_192_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC1 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_193_T_2 =
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s3_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
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& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC2 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_194_T_2 =
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s3_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC3 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_195_T_2 =
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s3_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC4 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_196_T_2 =
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s3_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s3_full_pred_0_slot_valids_0
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|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC5 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_197_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC6 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_198_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC7 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_199_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC8 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_200_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hC9 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_201_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCA & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_202_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCB & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_203_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCC & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_204_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCD & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_205_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCE & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_206_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hCF & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_207_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD0 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_208_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD1 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_209_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD2 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_210_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD3 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_211_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD4 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_212_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD5 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_213_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD6 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_214_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD7 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_215_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD8 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_216_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hD9 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_217_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDA & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_218_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDB & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_219_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDC & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_220_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDD & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_221_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDE & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_222_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hDF & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_223_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
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& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE0 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_224_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE1 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_225_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE2 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_226_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE3 & _s3_ghv_wdatas_WIRE_13797_1
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|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_227_T_2 =
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s3_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE4 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_228_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE5 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_229_T_2 =
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|
s3_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE6 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_230_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE7 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_231_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE8 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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|
wire _ghv_wens_232_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hE9 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_233_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEA & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_234_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEB & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_235_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEC & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_236_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hED & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_237_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEE & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_238_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hEF & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_239_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF0 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_240_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF1 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_241_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF2 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_242_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF3 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_243_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF4 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_244_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF5 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_245_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF6 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_246_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF7 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_247_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF8 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_248_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hF9 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_249_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFA & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_250_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFB & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_251_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFC & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_252_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFD & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_253_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | s3_ghist_ptr_dup_0_value == 8'hFE & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
|
|
wire _ghv_wens_254_T_2 =
|
|
s3_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | (&s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12
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wire _ghv_wens_255_T_2 =
|
|
(&s3_ghist_ptr_dup_0_value) & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& s3_redirect_dup_0 | ~(|s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit) & s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:{58,129}, :684:28, :704:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12
|
|
reg s2_ftq_idx_flag; // src/main/scala/xiangshan/frontend/BPU.scala:708:29
|
|
reg [5:0] s2_ftq_idx_value; // src/main/scala/xiangshan/frontend/BPU.scala:708:29
|
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reg s3_ftq_idx_flag; // src/main/scala/xiangshan/frontend/BPU.scala:709:29
|
|
reg [5:0] s3_ftq_idx_value; // src/main/scala/xiangshan/frontend/BPU.scala:709:29
|
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reg predictors_io_update_REG_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
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reg [38:0] predictors_io_update_REG_bits_pc; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
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reg [10:0]
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [10:0]
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [6:0]
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [7:0]
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [8:0]
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [3:0]
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [7:0]
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [8:0]
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [6:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [7:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [6:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [8:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [6:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [7:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [7:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [7:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [10:0] predictors_io_update_REG_bits_spec_info_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_ftb_entry_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [3:0] predictors_io_update_REG_bits_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [11:0] predictors_io_update_REG_bits_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [1:0] predictors_io_update_REG_bits_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_ftb_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [3:0] predictors_io_update_REG_bits_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [19:0] predictors_io_update_REG_bits_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [1:0] predictors_io_update_REG_bits_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [3:0] predictors_io_update_REG_bits_ftb_entry_pftAddr; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_ftb_entry_carry; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_ftb_entry_isCall; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_ftb_entry_isRet; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_ftb_entry_isJalr; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_ftb_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_ftb_entry_always_taken_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_cfi_idx_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [3:0] predictors_io_update_REG_bits_cfi_idx_bits; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_jmp_taken; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_mispred_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_mispred_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_mispred_mask_2; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg predictors_io_update_REG_bits_old_entry; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [218:0] predictors_io_update_REG_bits_meta; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
reg [38:0] predictors_io_update_REG_bits_full_target; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
wire [1:0] _shouldShiftVec_dup_T_46 = 2'(thisBrNumOH_dup_shiftAmount - 2'h1); // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:156
|
|
wire [3:0] _shouldShiftVec_dup_T_4 = 4'h1 << _shouldShiftVec_dup_T_46; // src/main/scala/xiangshan/frontend/BPU.scala:737:{147,156}
|
|
wire [1:0] _GEN_39 = _shouldShiftVec_dup_T_4[1:0] | _shouldShiftVec_dup_T_4[2:1]; // src/main/scala/xiangshan/frontend/BPU.scala:737:147, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53
|
|
wire shouldShiftVec_dup_0_0 =
|
|
(|thisBrNumOH_dup_shiftAmount)
|
|
& (_GEN_39[0] | _shouldShiftVec_dup_T_46 == 2'h2 | (&_shouldShiftVec_dup_T_46)); // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :440:30, :737:{54,61,156}, utility/src/main/scala/utility/BitUtils.scala:124:42, utility/src/main/scala/utility/ParallelMux.scala:36:53
|
|
wire shouldShiftVec_dup_0_1 =
|
|
(|thisBrNumOH_dup_shiftAmount) & (_GEN_39[1] | (&_shouldShiftVec_dup_T_46)); // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:{54,61,156}, utility/src/main/scala/utility/ParallelMux.scala:36:53
|
|
wire real_br_taken_mask_dup_0_0 =
|
|
thisBrNumOH_dup_shiftAmount == 2'h1 & do_redirect_dup_3_bits_cfiUpdate_taken
|
|
& do_redirect_dup_3_bits_cfiUpdate_addIntoHist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :747:{44,65}
|
|
wire real_br_taken_mask_dup_0_1 =
|
|
thisBrNumOH_dup_shiftAmount == 2'h2 & do_redirect_dup_3_bits_cfiUpdate_taken
|
|
& do_redirect_dup_3_bits_cfiUpdate_addIntoHist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :440:30, :747:{44,65}
|
|
wire [8:0] _updated_ptr_dup_flipped_new_ptr_T_6 =
|
|
9'(9'h100 - {7'h0, thisBrNumOH_dup_shiftAmount}); // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50
|
|
wire [8:0] _GEN_40 =
|
|
{do_redirect_dup_3_bits_cfiUpdate_histPtr_flag,
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_1 =
|
|
9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50
|
|
wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_3 =
|
|
9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50
|
|
wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_5 =
|
|
9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50
|
|
wire [8:0] _updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_7 =
|
|
9'(_GEN_40 + _updated_ptr_dup_flipped_new_ptr_T_6); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :54:50
|
|
wire
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1 =
|
|
do_redirect_dup_3_bits_cfiUpdate_taken & do_redirect_dup_3_bits_cfiUpdate_addIntoHist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83
|
|
wire _GEN_41 =
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[0]
|
|
| _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29
|
|
wire [7:0] _updated_fh_dup_WIRE_1_0_hist_0_folded_hist =
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[7:1], _GEN_41}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29
|
|
wire _GEN_42 =
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[0]
|
|
| _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29
|
|
wire [3:0] _updated_fh_dup_WIRE_1_0_hist_12_folded_hist =
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[3:1], _GEN_42}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29
|
|
wire _GEN_43 =
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[0]
|
|
| _updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29
|
|
wire [7:0] _updated_fh_dup_WIRE_1_0_hist_14_folded_hist =
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[7:1], _GEN_43}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29
|
|
wire [7:0] _updated_fh_dup_WIRE_2_0_hist_0_folded_hist =
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[7:1], _GEN_41}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29
|
|
wire [3:0] _updated_fh_dup_WIRE_2_0_hist_12_folded_hist =
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[3:1], _GEN_42}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29
|
|
wire [7:0] _updated_fh_dup_WIRE_2_0_hist_14_folded_hist =
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[7:1], _GEN_43}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29
|
|
wire [7:0] _updated_fh_dup_WIRE_3_0_hist_0_folded_hist =
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[7:1], _GEN_41}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29
|
|
wire [3:0] _updated_fh_dup_WIRE_3_0_hist_12_folded_hist =
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[3:1], _GEN_42}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29
|
|
wire [7:0] _updated_fh_dup_WIRE_3_0_hist_14_folded_hist =
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[7:1], _GEN_43}; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:29
|
|
wire [3:0] _GEN_44 = {2'h0, thisBrNumOH_dup_shiftAmount}; // src/main/scala/chisel3/util/OneHot.scala:65:12, src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40
|
|
wire [3:0] _thisBrNumOH_dup_T_1 = 4'h1 << _GEN_44; // src/main/scala/chisel3/util/OneHot.scala:65:12, src/main/scala/xiangshan/frontend/BPU.scala:737:147
|
|
wire [3:0] _thisBrNumOH_dup_T_2 = 4'h1 << _GEN_44; // src/main/scala/chisel3/util/OneHot.scala:65:12, src/main/scala/xiangshan/frontend/BPU.scala:737:147
|
|
wire [3:0] _thisBrNumOH_dup_T_3 = 4'h1 << _GEN_44; // src/main/scala/chisel3/util/OneHot.scala:65:12, src/main/scala/xiangshan/frontend/BPU.scala:737:147
|
|
wire thisAheadFhOb_dup_1_afhob_0_bits_0 =
|
|
_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire thisAheadFhOb_dup_1_afhob_0_bits_2 =
|
|
_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire thisAheadFhOb_dup_1_afhob_0_bits_3 =
|
|
_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire thisAheadFhOb_dup_1_afhob_1_bits_0 =
|
|
_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire thisAheadFhOb_dup_2_afhob_0_bits_0 =
|
|
_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire thisAheadFhOb_dup_2_afhob_0_bits_2 =
|
|
_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire thisAheadFhOb_dup_2_afhob_0_bits_3 =
|
|
_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire thisAheadFhOb_dup_2_afhob_1_bits_0 =
|
|
_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
wire thisAheadFhOb_dup_3_afhob_0_bits_0 =
|
|
_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hA)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire thisAheadFhOb_dup_3_afhob_0_bits_2 =
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_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h8)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire thisAheadFhOb_dup_3_afhob_0_bits_3 =
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_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h7)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire thisAheadFhOb_dup_3_afhob_1_bits_0 =
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_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hD)]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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wire _ghv_wens_0_T_3 =
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~(|do_redirect_dup_3_bits_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0
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|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1
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|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_1_T_3 =
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|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1 & shouldShiftVec_dup_0_0
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& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2
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& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_2_T_3 =
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|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2 & shouldShiftVec_dup_0_0
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& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3
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|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_3_T_3 =
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|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3 & shouldShiftVec_dup_0_0
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|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4
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& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_4_T_3 =
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|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4 & shouldShiftVec_dup_0_0
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& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5
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& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_5_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5 & shouldShiftVec_dup_0_0
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& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6
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|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_6_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6 & shouldShiftVec_dup_0_0
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|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_7_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_8_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_9_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_10_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_11_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_12_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_13_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_14_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_15_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h10
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_16_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h10 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h11
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_17_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h11 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h12
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_18_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h12 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h13
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_19_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h13 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h14
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_20_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h14 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h15
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_21_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h15 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h16
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_22_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h16 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h17
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_23_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h17 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h18
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_24_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h18 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h19
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_25_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h19 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1A
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_26_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1A & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1B
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_27_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1B & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1C
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_28_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1C & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1D
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_29_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1D & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1E
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_30_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1E & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1F
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_31_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1F & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h20
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_32_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h20 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h21
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_33_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h21 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h22
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_34_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h22 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h23
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_35_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h23 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h24
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_36_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h24 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h25
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_37_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h25 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h26
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_38_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h26 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h27
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_39_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h27 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h28
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_40_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h28 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h29
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_41_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h29 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2A
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_42_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2A & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2B
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_43_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2B & shouldShiftVec_dup_0_0
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& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2C
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& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_44_T_3 =
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|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2C & shouldShiftVec_dup_0_0
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& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2D
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& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_45_T_3 =
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do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2D & shouldShiftVec_dup_0_0
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|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2E
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|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_46_T_3 =
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|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2E & shouldShiftVec_dup_0_0
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& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2F
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& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_47_T_3 =
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|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2F & shouldShiftVec_dup_0_0
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& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h30
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|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_48_T_3 =
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|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h30 & shouldShiftVec_dup_0_0
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|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h31
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|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_49_T_3 =
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|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h31 & shouldShiftVec_dup_0_0
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|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h32
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& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_50_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h32 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h33
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|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_51_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h33 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h34
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_52_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h34 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h35
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_53_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h35 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h36
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_54_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h36 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h37
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_55_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h37 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h38
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_56_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h38 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h39
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_57_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h39 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3A
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_58_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3A & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3B
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_59_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3B & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3C
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_60_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3C & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3D
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_61_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3D & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3E
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_62_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3E & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3F
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_63_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3F & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h40
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_64_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h40 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h41
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_65_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h41 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h42
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_66_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h42 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h43
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_67_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h43 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h44
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_68_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h44 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h45
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_69_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h45 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h46
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_70_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h46 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h47
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_71_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h47 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h48
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_72_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h48 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h49
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_73_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h49 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4A
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_74_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4A & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4B
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_75_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4B & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4C
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_76_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4C & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4D
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_77_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4D & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4E
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_78_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4E & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4F
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_79_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4F & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h50
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_80_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h50 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h51
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_81_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h51 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h52
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_82_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h52 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h53
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_83_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h53 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h54
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_84_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h54 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h55
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_85_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h55 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h56
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_86_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h56 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h57
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_87_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h57 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h58
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_88_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h58 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h59
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_89_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h59 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5A
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_90_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5A & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5B
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_91_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5B & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5C
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_92_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5C & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5D
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_93_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5D & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5E
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_94_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5E & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5F
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_95_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5F & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h60
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_96_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h60 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h61
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_97_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h61 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h62
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_98_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h62 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h63
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_99_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h63 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h64
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_100_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h64 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h65
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_101_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h65 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h66
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_102_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h66 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h67
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_103_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h67 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h68
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_104_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h68 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h69
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_105_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h69 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6A
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_106_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6A & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6B
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_107_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6B & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6C
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_108_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6C & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6D
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_109_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6D & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6E
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_110_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6E & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6F
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_111_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6F & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h70
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_112_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h70 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h71
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_113_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h71 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h72
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_114_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h72 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h73
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_115_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h73 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h74
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_116_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h74 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h75
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_117_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h75 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h76
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_118_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h76 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h77
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_119_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h77 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h78
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_120_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h78 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h79
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_121_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h79 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7A
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_122_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7A & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7B
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_123_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7B & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7C
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_124_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7C & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7D
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_125_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7D & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7E
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_126_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7E & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7F
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_127_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7F & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h80
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_128_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h80 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h81
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_129_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h81 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h82
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_130_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h82 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h83
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_131_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h83 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h84
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_132_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h84 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h85
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_133_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h85 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h86
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_134_T_3 =
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do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h86 & shouldShiftVec_dup_0_0
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& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h87
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& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_135_T_3 =
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do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h87 & shouldShiftVec_dup_0_0
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& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h88
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& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_136_T_3 =
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do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h88 & shouldShiftVec_dup_0_0
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& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h89
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& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_137_T_3 =
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do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h89 & shouldShiftVec_dup_0_0
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& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8A
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& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_138_T_3 =
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do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8A & shouldShiftVec_dup_0_0
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& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8B
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& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_139_T_3 =
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do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8B & shouldShiftVec_dup_0_0
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& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8C
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& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_140_T_3 =
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do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8C & shouldShiftVec_dup_0_0
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& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8D
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& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_141_T_3 =
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do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8D & shouldShiftVec_dup_0_0
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& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8E
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& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_142_T_3 =
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|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8E & shouldShiftVec_dup_0_0
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& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8F
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|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_143_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8F & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h90
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|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_144_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h90 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h91
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|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_145_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h91 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h92
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|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_146_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h92 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h93
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_147_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h93 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h94
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_148_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h94 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h95
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|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_149_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h95 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h96
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_150_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h96 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h97
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_151_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h97 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h98
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_152_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h98 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h99
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_153_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h99 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9A
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_154_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9A & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9B
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_155_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9B & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9C
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_156_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9C & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9D
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_157_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9D & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9E
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_158_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9E & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9F
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_159_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9F & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA0
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_160_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA0 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA1
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_161_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA1 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA2
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_162_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA2 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA3
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_163_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA3 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA4
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_164_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA4 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA5
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_165_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA5 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA6
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_166_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA6 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA7
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_167_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA7 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA8
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_168_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA8 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA9
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_169_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA9 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAA
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_170_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAA & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAB
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_171_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAB & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAC
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_172_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAC & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAD
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_173_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAD & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAE
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_174_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAE & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAF
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_175_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAF & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB0
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_176_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB0 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB1
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_177_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB1 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB2
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_178_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB2 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB3
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
|
|
wire _ghv_wens_179_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB3 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB4
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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wire _ghv_wens_180_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB4 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB5
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|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26
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|
wire _ghv_wens_181_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB5 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB6
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
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wire _ghv_wens_182_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB6 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB7
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
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|
wire _ghv_wens_183_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB7 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB8
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_184_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB8 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB9
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_185_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB9 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBA
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_186_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBA & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBB
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_187_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBB & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBC
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_188_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBC & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBD
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_189_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBD & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBE
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_190_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBE & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBF
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_191_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBF & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC0
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_192_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC0 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC1
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_193_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC1 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC2
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_194_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC2 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC3
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_195_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC3 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC4
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_196_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC4 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC5
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_197_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC5 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC6
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_198_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC6 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC7
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_199_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC7 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC8
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_200_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC8 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC9
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_201_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC9 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCA
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_202_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCA & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCB
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_203_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCB & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCC
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_204_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCC & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCD
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_205_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCD & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCE
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_206_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCE & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCF
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_207_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCF & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD0
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_208_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD0 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD1
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_209_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD1 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD2
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_210_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD2 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD3
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_211_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD3 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD4
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_212_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD4 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD5
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_213_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD5 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD6
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_214_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD6 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD7
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_215_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD7 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD8
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_216_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD8 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD9
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_217_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD9 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDA
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_218_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDA & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDB
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_219_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDB & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDC
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_220_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDC & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDD
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_221_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDD & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDE
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_222_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDE & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDF
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_223_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDF & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE0
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_224_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE0 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE1
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_225_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE1 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE2
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_226_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE2 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE3
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_227_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE3 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE4
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_228_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE4 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE5
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_229_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE5 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE6
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_230_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE6 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE7
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_231_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE7 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE8
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_232_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE8 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE9
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_233_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE9 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEA
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_234_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEA & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEB
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_235_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEB & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEC
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_236_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEC & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hED
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_237_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hED & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEE
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_238_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEE & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEF
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_239_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEF & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF0
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_240_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF0 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF1
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_241_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF1 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF2
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_242_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF2 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF3
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_243_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF3 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF4
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_244_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF4 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF5
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_245_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF5 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF6
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_246_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF6 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF7
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_247_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF7 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF8
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_248_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF8 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF9
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_249_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF9 & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFA
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_250_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFA & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFB
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_251_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFB & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFC
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_252_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFC & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFD
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_253_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFD & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFE
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_254_T_3 =
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFE & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | (&do_redirect_dup_3_bits_cfiUpdate_histPtr_value)
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
wire _ghv_wens_255_T_3 =
|
|
(&do_redirect_dup_3_bits_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0
|
|
& do_redirect_dup_3_valid | ~(|do_redirect_dup_3_bits_cfiUpdate_histPtr_value)
|
|
& shouldShiftVec_dup_0_1 & do_redirect_dup_3_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :760:{50,117}, :855:26
|
|
wire [3:0][10:0] _GEN_45 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[7:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9]}},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][10:0] _GEN_46 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[6:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][6:0] _GEN_47 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[3:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5]}},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_48 =
|
|
{{_updated_fh_dup_WIRE_1_0_hist_14_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[5:0],
|
|
1'h0,
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[6:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{_updated_fh_dup_WIRE_1_0_hist_14_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][8:0] _GEN_49 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[6:4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[1:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7:4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][3:0] _GEN_50 =
|
|
{{_updated_fh_dup_WIRE_1_0_hist_12_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[1:0],
|
|
1'h0,
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[2:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{_updated_fh_dup_WIRE_1_0_hist_12_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_51 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[5:2],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6:2],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][8:0] _GEN_52 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[6:5],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[2:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7:5],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][6:0] _GEN_53 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[1:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5:4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_54 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[4:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6]}},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][6:0] _GEN_55 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[4:1],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0],
|
|
1'h0,
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5:1],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[6]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][8:0] _GEN_56 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[4:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][6:0] _GEN_57 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[4:0],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_58 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[5],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[2:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6:5],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_59 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[5:0],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_60 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[5:0],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][10:0] _GEN_61 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[8:2],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9:2],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_62 =
|
|
{{_updated_fh_dup_WIRE_1_0_hist_0_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[5:0],
|
|
1'h0,
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[6:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{_updated_fh_dup_WIRE_1_0_hist_0_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][10:0] _GEN_63 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[7:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9]}},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][10:0] _GEN_64 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[6:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][6:0] _GEN_65 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[3:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5]}},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_66 =
|
|
{{_updated_fh_dup_WIRE_2_0_hist_14_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[5:0],
|
|
1'h0,
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[6:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{_updated_fh_dup_WIRE_2_0_hist_14_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][8:0] _GEN_67 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[6:4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[1:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7:4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][3:0] _GEN_68 =
|
|
{{_updated_fh_dup_WIRE_2_0_hist_12_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[1:0],
|
|
1'h0,
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[2:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{_updated_fh_dup_WIRE_2_0_hist_12_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_69 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[5:2],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6:2],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][8:0] _GEN_70 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[6:5],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[2:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7:5],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][6:0] _GEN_71 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[1:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5:4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_72 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[4:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6]}},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][6:0] _GEN_73 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[4:1],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0],
|
|
1'h0,
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5:1],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[6]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][8:0] _GEN_74 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[4:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][6:0] _GEN_75 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[4:0],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_76 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[5],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[2:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6:5],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_77 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[5:0],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_78 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[5:0],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][10:0] _GEN_79 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[8:2],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9:2],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_80 =
|
|
{{_updated_fh_dup_WIRE_2_0_hist_0_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[5:0],
|
|
1'h0,
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[6:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{_updated_fh_dup_WIRE_2_0_hist_0_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][10:0] _GEN_81 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[7:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9]}},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[9],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[8:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist[10]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][10:0] _GEN_82 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[6:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[9],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[8],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[7:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist[10]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][6:0] _GEN_83 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[3:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5]}},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[5],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[4:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist[6]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_84 =
|
|
{{_updated_fh_dup_WIRE_3_0_hist_14_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[5:0],
|
|
1'h0,
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist[6:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{_updated_fh_dup_WIRE_3_0_hist_14_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][8:0] _GEN_85 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[6:4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[1:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[7:4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[3],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[2:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist[8]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][3:0] _GEN_86 =
|
|
{{_updated_fh_dup_WIRE_3_0_hist_12_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[1:0],
|
|
1'h0,
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist[2:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{_updated_fh_dup_WIRE_3_0_hist_12_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_87 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[5:2],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[6:2],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[1],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist[7]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][8:0] _GEN_88 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[6:5],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[2:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[7:5],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[4],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[3:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist[8]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][6:0] _GEN_89 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[1:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[5:4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[3],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[2:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist[6]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_90 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[4:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6]}},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[6],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[5:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist[7]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][6:0] _GEN_91 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[4:1],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0],
|
|
1'h0,
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[5:1],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist[6]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][8:0] _GEN_92 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist},
|
|
{{(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[4:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[7],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[6],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[5:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist[8]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][6:0] _GEN_93 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[4:0],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[5:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist[6]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_94 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[5],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[2:0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[6:5],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[4],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[3:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist[7]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_95 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[5:0],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[6:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist[7]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_96 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[5:0],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[6:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist[7]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][10:0] _GEN_97 =
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[8:2],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9]}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[9:2],
|
|
(do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[0]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[1]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1
|
|
| do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH[2]
|
|
& do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2)
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[1],
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist[10]}},
|
|
{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist}}; // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire [3:0][7:0] _GEN_98 =
|
|
{{_updated_fh_dup_WIRE_3_0_hist_0_folded_hist},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[5:0],
|
|
1'h0,
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{{do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist[6:0],
|
|
_updated_fh_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}},
|
|
{_updated_fh_dup_WIRE_3_0_hist_0_folded_hist}}; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40, :755:83, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
wire _GEN_99 =
|
|
_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :473:32
|
|
wire s2_flush_dup_0 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :684:28
|
|
wire s2_flush_dup_1 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :684:28
|
|
wire s2_flush_dup_2 = io_ftq_to_bpu_redirect_valid | s3_redirect_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :684:28
|
|
wire s1_flush_dup_0 = s2_flush_dup_0 | s2_redirect_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :360:26, :605:28
|
|
wire s1_flush_dup_1 = s2_flush_dup_1 | s2_redirect_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :360:26, :605:28
|
|
wire s1_flush_dup_2 = s2_flush_dup_2 | s2_redirect_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :360:26, :605:28
|
|
wire s1_flush_dup_3 = s2_flush_dup_3 | s2_redirect_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:358:26, :360:26, :605:28
|
|
wire _GEN_100 = s3_valid_dup_3 | io_ftq_to_bpu_redirect_valid; // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :408:{26,37}, :409:26, :410:{26,37}
|
|
always @(posedge clock or posedge reset) begin
|
|
if (reset) begin
|
|
s1_valid_dup_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65
|
|
s2_valid_dup_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65
|
|
s3_valid_dup_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65
|
|
s0_folded_gh_reg_dup_1_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s1_folded_gh_dup_1_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35
|
|
s1_folded_gh_dup_1_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_2_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_2_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_2_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_2_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35
|
|
s1_folded_gh_dup_2_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_2_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_2_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_2_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_2_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_2_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_2_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_3_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_3_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_3_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_3_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35
|
|
s1_folded_gh_dup_3_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_3_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_3_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_3_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_3_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_3_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_3_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s2_folded_gh_dup_1_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35
|
|
s2_folded_gh_dup_1_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35
|
|
s2_folded_gh_dup_2_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35
|
|
s2_folded_gh_dup_3_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s3_folded_gh_dup_1_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35
|
|
s3_folded_gh_dup_1_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35
|
|
s3_folded_gh_dup_2_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35
|
|
s3_folded_gh_dup_3_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s0_last_br_num_oh_reg_dup_1 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76
|
|
s0_last_br_num_oh_reg_dup_2 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76
|
|
s0_last_br_num_oh_reg_dup_3 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76
|
|
s1_last_br_num_oh_dup_1 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76}
|
|
s1_last_br_num_oh_dup_2 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76}
|
|
s1_last_br_num_oh_dup_3 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76}
|
|
s2_last_br_num_oh_dup_1 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40
|
|
s2_last_br_num_oh_dup_2 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40
|
|
s2_last_br_num_oh_dup_3 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40
|
|
s3_last_br_num_oh_dup_1 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40
|
|
s3_last_br_num_oh_dup_2 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40
|
|
s3_last_br_num_oh_dup_3 <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
ghv_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_4 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_5 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_6 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_7 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_8 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_9 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_10 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_11 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_12 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_13 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_14 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_15 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_16 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_17 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_18 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_19 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_20 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_21 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_22 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_23 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_24 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_25 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_26 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_27 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_28 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_29 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_30 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_31 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_32 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_33 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_34 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_35 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_36 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_37 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_38 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_39 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_40 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_41 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_42 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_43 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_44 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_45 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_46 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_47 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_48 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_49 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_50 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_51 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_52 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_53 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_54 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_55 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_56 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_57 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_58 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_59 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_60 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_61 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_62 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_63 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_64 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_65 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_66 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_67 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_68 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_69 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_70 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_71 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_72 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_73 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_74 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_75 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_76 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_77 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_78 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_79 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_80 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_81 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_82 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_83 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_84 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_85 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_86 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_87 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_88 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_89 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_90 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_91 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_92 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_93 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_94 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_95 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_96 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_97 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_98 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_99 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_100 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_101 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_102 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_103 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_104 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_105 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_106 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_107 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_108 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_109 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_110 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_111 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_112 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_113 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_114 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_115 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_116 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_117 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_118 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_119 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_120 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_121 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_122 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_123 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_124 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_125 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_126 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_127 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_128 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_129 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_130 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_131 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_132 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_133 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_134 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_135 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_136 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_137 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_138 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_139 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_140 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_141 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_142 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_143 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_144 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_145 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_146 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_147 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_148 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_149 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_150 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_151 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_152 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_153 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_154 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_155 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_156 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_157 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_158 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_159 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_160 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_161 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_162 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_163 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_164 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_165 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_166 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_167 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_168 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_169 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_170 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_171 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_172 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_173 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_174 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_175 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_176 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_177 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_178 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_179 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_180 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_181 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_182 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_183 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_184 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_185 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_186 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_187 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_188 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_189 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_190 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_191 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_192 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_193 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_194 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_195 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_196 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_197 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_198 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_199 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_200 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_201 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_202 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_203 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_204 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_205 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_206 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_207 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_208 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_209 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_210 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_211 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_212 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_213 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_214 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_215 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_216 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_217 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_218 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_219 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_220 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_221 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_222 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_223 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_224 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_225 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_226 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_227 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_228 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_229 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_230 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_231 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_232 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_233 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_234 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_235 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_236 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_237 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_238 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_239 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_240 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_241 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_242 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_243 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_244 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_245 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_246 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_247 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_248 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_249 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_250 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_251 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_252 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_253 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_254 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_255 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
s0_ghist_ptr_reg_dup_0_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63
|
|
s0_ghist_ptr_reg_dup_0_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63
|
|
s0_ghist_ptr_reg_dup_1_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63
|
|
s0_ghist_ptr_reg_dup_1_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63
|
|
s0_ghist_ptr_reg_dup_2_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63
|
|
s0_ghist_ptr_reg_dup_2_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63
|
|
s0_ghist_ptr_reg_dup_3_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63
|
|
s0_ghist_ptr_reg_dup_3_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63
|
|
s1_ghist_ptr_dup_0_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35
|
|
s1_ghist_ptr_dup_0_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35
|
|
s1_ghist_ptr_dup_1_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35
|
|
s1_ghist_ptr_dup_1_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35
|
|
s1_ghist_ptr_dup_2_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35
|
|
s1_ghist_ptr_dup_2_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35
|
|
s1_ghist_ptr_dup_3_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35
|
|
s1_ghist_ptr_dup_3_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35
|
|
s2_ghist_ptr_dup_0_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35
|
|
s2_ghist_ptr_dup_0_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35
|
|
s2_ghist_ptr_dup_1_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35
|
|
s2_ghist_ptr_dup_1_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35
|
|
s2_ghist_ptr_dup_2_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35
|
|
s2_ghist_ptr_dup_2_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35
|
|
s2_ghist_ptr_dup_3_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35
|
|
s2_ghist_ptr_dup_3_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35
|
|
s3_ghist_ptr_dup_0_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35
|
|
s3_ghist_ptr_dup_0_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35
|
|
s3_ghist_ptr_dup_1_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35
|
|
s3_ghist_ptr_dup_1_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35
|
|
s3_ghist_ptr_dup_2_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35
|
|
s3_ghist_ptr_dup_2_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35
|
|
s3_ghist_ptr_dup_3_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35
|
|
s3_ghist_ptr_dup_3_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35
|
|
do_redirect_dup_3_valid <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_level <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_pc <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_pd_isRVC <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_pd_isCall <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_pd_isRet <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_ssp <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_sctr <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_TOSW_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_TOSW_value <= 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_TOSR_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_TOSR_value <= 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_NOS_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_NOS_value <= 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist <= 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist <= 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist <= 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH <= 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_flag <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value <= 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_target <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_taken <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
thisBrNumOH_dup_shiftAmount <= 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_addIntoHist <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
previous_s1_pred_info_hit_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_hit_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_hit_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_hit_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_target_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40
|
|
previous_s1_pred_info_target_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40
|
|
previous_s1_pred_info_target_2 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40
|
|
previous_s1_pred_info_target_3 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_0_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_0_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_0_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_1_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_1_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_1_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_2_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_2_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_2_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_3_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_3_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_3_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_taken_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_taken_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_taken_2 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_taken_3 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_takenMask_0_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_takenMask_0_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_takenMask_1_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_takenMask_1_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_takenMask_2_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_takenMask_2_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_takenMask_3_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_takenMask_3_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_cfiIndex_0 <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_cfiIndex_1 <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_cfiIndex_2 <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_cfiIndex_3 <= 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s2_pred_pc_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_pc_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_pc_2 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_pc_3 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_0_br_taken_mask_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_0_br_taken_mask_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_0_slot_valids_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_0_slot_valids_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_0_targets_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_0_targets_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_0_fallThroughAddr <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_0_is_br_sharing <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_0_hit <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_1_br_taken_mask_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_1_br_taken_mask_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_1_slot_valids_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_1_slot_valids_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_1_targets_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_1_targets_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_1_fallThroughAddr <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_1_is_br_sharing <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_1_hit <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_2_br_taken_mask_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_2_br_taken_mask_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_2_slot_valids_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_2_slot_valids_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_2_targets_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_2_targets_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_2_fallThroughAddr <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_2_is_br_sharing <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_2_hit <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_3_br_taken_mask_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_3_br_taken_mask_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_3_slot_valids_0 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_3_slot_valids_1 <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_3_targets_0 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_3_targets_1 <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_3_fallThroughAddr <= 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_3_is_br_sharing <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_3_hit <= 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
end
|
|
else begin
|
|
s1_valid_dup_3 <=
|
|
~io_ftq_to_bpu_redirect_valid
|
|
& (s0_fire_dup_3
|
|
| ~(s1_flush_dup_3 | s1_fire_dup_3 | io_ftq_to_bpu_redirect_valid)
|
|
& (s0_fire_dup_2
|
|
| ~(s1_flush_dup_2 | s1_fire_dup_2 | io_ftq_to_bpu_redirect_valid)
|
|
& (s0_fire_dup_1
|
|
| ~(s1_flush_dup_1 | s1_fire_dup_1 | io_ftq_to_bpu_redirect_valid)
|
|
& (s0_fire_dup_0 | ~(s1_flush_dup_0 | s1_fire_dup_0)
|
|
& s1_valid_dup_3)))); // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :360:26, :367:36, :374:60, :383:{31,42}, :384:{31,42}, :385:{31,42}, :386:{31,42}
|
|
s2_valid_dup_3 <=
|
|
~s2_flush_dup_3
|
|
& (s1_fire_dup_3
|
|
? ~s1_flush_dup_3
|
|
: ~(s2_valid_dup_3 | s2_flush_dup_2)
|
|
& (s1_fire_dup_2
|
|
? ~s1_flush_dup_2
|
|
: ~(s2_valid_dup_3 | s2_flush_dup_1)
|
|
& (s1_fire_dup_1
|
|
? ~s1_flush_dup_1
|
|
: ~(s2_valid_dup_3 | s2_flush_dup_0) & s1_fire_dup_0
|
|
& ~s1_flush_dup_0))); // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :358:26, :360:26, :374:60, :395:{26,37}, :396:{26,37,40}, :397:{26,37}
|
|
s3_valid_dup_3 <=
|
|
~io_ftq_to_bpu_redirect_valid
|
|
& (s2_valid_dup_3
|
|
? ~s2_flush_dup_3
|
|
: ~_GEN_100
|
|
& (s2_valid_dup_3
|
|
? ~s2_flush_dup_2
|
|
: ~_GEN_100
|
|
& (s2_valid_dup_3
|
|
? ~s2_flush_dup_1
|
|
: ~_GEN_100 & s2_valid_dup_3 & ~s2_flush_dup_0))); // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :358:26, :383:{31,42}, :384:31, :408:{26,37}, :409:{26,37,40}, :410:{26,37}
|
|
s0_folded_gh_reg_dup_1_hist_17_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_1_hist_16_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_1_hist_15_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_1_hist_14_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_1_hist_13_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_1_hist_12_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_1_hist_11_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_1_hist_10_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_1_hist_9_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_1_hist_8_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_1_hist_7_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_1_hist_6_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_1_hist_5_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_1_hist_4_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_1_hist_3_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_1_hist_2_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_1_hist_1_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_1_hist_0_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_17_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_16_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_15_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_14_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_13_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_12_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_11_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_10_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_9_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_8_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_7_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_6_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_5_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_4_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_3_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_2_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_1_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_2_hist_0_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_17_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_16_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_15_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_14_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_13_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_12_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_11_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_10_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_9_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_8_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_7_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_6_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_5_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_4_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_3_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_2_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_1_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_folded_gh_reg_dup_3_hist_0_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:285:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (s0_fire_dup_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:367:36
|
|
s1_folded_gh_dup_1_hist_17_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_1_hist_16_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_1_hist_15_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_1_hist_14_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_1_hist_13_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_1_hist_12_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_1_hist_11_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_1_hist_10_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_1_hist_9_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_1_hist_8_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_1_hist_7_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_1_hist_6_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_1_hist_5_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_1_hist_4_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_1_hist_3_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_1_hist_2_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_1_hist_1_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_1_hist_0_folded_hist <=
|
|
_s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_17_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_16_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_15_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_14_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_13_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_12_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_11_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_10_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_9_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_8_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_7_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_6_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_5_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_4_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_3_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_2_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_1_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_2_hist_0_folded_hist <=
|
|
_s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_17_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_16_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_15_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_14_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_13_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_12_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_11_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_10_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_9_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_8_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_7_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_6_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_5_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_4_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_3_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_2_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_1_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_folded_gh_dup_3_hist_0_folded_hist <=
|
|
_s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_last_br_num_oh_dup_1 <= _s0_last_br_num_oh_dup_1_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_last_br_num_oh_dup_2 <= _s0_last_br_num_oh_dup_2_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_last_br_num_oh_dup_3 <= _s0_last_br_num_oh_dup_3_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ghist_ptr_dup_0_flag <= _s0_ghist_ptr_dup_0_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ghist_ptr_dup_0_value <= _s0_ghist_ptr_dup_0_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ghist_ptr_dup_1_flag <= _s0_ghist_ptr_dup_1_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ghist_ptr_dup_1_value <= _s0_ghist_ptr_dup_1_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ghist_ptr_dup_2_flag <= _s0_ghist_ptr_dup_2_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ghist_ptr_dup_2_value <= _s0_ghist_ptr_dup_2_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ghist_ptr_dup_3_flag <= _s0_ghist_ptr_dup_3_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s1_ghist_ptr_dup_3_value <= _s0_ghist_ptr_dup_3_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
end
|
|
if (s1_fire_dup_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:374:60
|
|
s2_folded_gh_dup_1_hist_17_folded_hist <= s1_folded_gh_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_1_hist_16_folded_hist <= s1_folded_gh_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_1_hist_15_folded_hist <= s1_folded_gh_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_1_hist_14_folded_hist <= s1_folded_gh_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_1_hist_13_folded_hist <= s1_folded_gh_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_1_hist_12_folded_hist <= s1_folded_gh_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_1_hist_11_folded_hist <= s1_folded_gh_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_1_hist_10_folded_hist <= s1_folded_gh_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_1_hist_9_folded_hist <= s1_folded_gh_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_1_hist_8_folded_hist <= s1_folded_gh_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_1_hist_7_folded_hist <= s1_folded_gh_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_1_hist_6_folded_hist <= s1_folded_gh_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_1_hist_5_folded_hist <= s1_folded_gh_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_1_hist_4_folded_hist <= s1_folded_gh_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_1_hist_3_folded_hist <= s1_folded_gh_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_1_hist_2_folded_hist <= s1_folded_gh_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_1_hist_1_folded_hist <= s1_folded_gh_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_1_hist_0_folded_hist <= s1_folded_gh_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_17_folded_hist <= s1_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_16_folded_hist <= s1_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_15_folded_hist <= s1_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_14_folded_hist <= s1_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_13_folded_hist <= s1_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_12_folded_hist <= s1_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_11_folded_hist <= s1_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_10_folded_hist <= s1_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_9_folded_hist <= s1_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_8_folded_hist <= s1_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_7_folded_hist <= s1_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_6_folded_hist <= s1_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_5_folded_hist <= s1_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_4_folded_hist <= s1_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_3_folded_hist <= s1_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_2_folded_hist <= s1_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_1_folded_hist <= s1_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_2_hist_0_folded_hist <= s1_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_17_folded_hist <= s1_folded_gh_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_16_folded_hist <= s1_folded_gh_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_15_folded_hist <= s1_folded_gh_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_14_folded_hist <= s1_folded_gh_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_13_folded_hist <= s1_folded_gh_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_12_folded_hist <= s1_folded_gh_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_11_folded_hist <= s1_folded_gh_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_10_folded_hist <= s1_folded_gh_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_9_folded_hist <= s1_folded_gh_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_8_folded_hist <= s1_folded_gh_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_7_folded_hist <= s1_folded_gh_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_6_folded_hist <= s1_folded_gh_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_5_folded_hist <= s1_folded_gh_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_4_folded_hist <= s1_folded_gh_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_3_folded_hist <= s1_folded_gh_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_2_folded_hist <= s1_folded_gh_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_1_folded_hist <= s1_folded_gh_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_folded_gh_dup_3_hist_0_folded_hist <= s1_folded_gh_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:286:35, :287:35
|
|
s2_last_br_num_oh_dup_1 <= s1_last_br_num_oh_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, :293:40
|
|
s2_last_br_num_oh_dup_2 <= s1_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, :293:40
|
|
s2_last_br_num_oh_dup_3 <= s1_last_br_num_oh_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:292:40, :293:40
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <=
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <=
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <=
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:298:46, :299:46
|
|
s2_ghist_ptr_dup_0_flag <= s1_ghist_ptr_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35
|
|
s2_ghist_ptr_dup_0_value <= s1_ghist_ptr_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35
|
|
s2_ghist_ptr_dup_1_flag <= s1_ghist_ptr_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35
|
|
s2_ghist_ptr_dup_1_value <= s1_ghist_ptr_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35
|
|
s2_ghist_ptr_dup_2_flag <= s1_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35
|
|
s2_ghist_ptr_dup_2_value <= s1_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35
|
|
s2_ghist_ptr_dup_3_flag <= s1_ghist_ptr_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35
|
|
s2_ghist_ptr_dup_3_value <= s1_ghist_ptr_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:323:35, :324:35
|
|
end
|
|
if (s2_valid_dup_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:271:65
|
|
s3_folded_gh_dup_1_hist_17_folded_hist <= s2_folded_gh_dup_1_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_1_hist_16_folded_hist <= s2_folded_gh_dup_1_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_1_hist_15_folded_hist <= s2_folded_gh_dup_1_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_1_hist_14_folded_hist <= s2_folded_gh_dup_1_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_1_hist_13_folded_hist <= s2_folded_gh_dup_1_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_1_hist_12_folded_hist <= s2_folded_gh_dup_1_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_1_hist_11_folded_hist <= s2_folded_gh_dup_1_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_1_hist_10_folded_hist <= s2_folded_gh_dup_1_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_1_hist_9_folded_hist <= s2_folded_gh_dup_1_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_1_hist_8_folded_hist <= s2_folded_gh_dup_1_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_1_hist_7_folded_hist <= s2_folded_gh_dup_1_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_1_hist_6_folded_hist <= s2_folded_gh_dup_1_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_1_hist_5_folded_hist <= s2_folded_gh_dup_1_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_1_hist_4_folded_hist <= s2_folded_gh_dup_1_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_1_hist_3_folded_hist <= s2_folded_gh_dup_1_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_1_hist_2_folded_hist <= s2_folded_gh_dup_1_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_1_hist_1_folded_hist <= s2_folded_gh_dup_1_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_1_hist_0_folded_hist <= s2_folded_gh_dup_1_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_17_folded_hist <= s2_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_16_folded_hist <= s2_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_15_folded_hist <= s2_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_14_folded_hist <= s2_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_13_folded_hist <= s2_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_12_folded_hist <= s2_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_11_folded_hist <= s2_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_10_folded_hist <= s2_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_9_folded_hist <= s2_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_8_folded_hist <= s2_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_7_folded_hist <= s2_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_6_folded_hist <= s2_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_5_folded_hist <= s2_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_4_folded_hist <= s2_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_3_folded_hist <= s2_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_2_folded_hist <= s2_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_1_folded_hist <= s2_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_2_hist_0_folded_hist <= s2_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_17_folded_hist <= s2_folded_gh_dup_3_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_16_folded_hist <= s2_folded_gh_dup_3_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_15_folded_hist <= s2_folded_gh_dup_3_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_14_folded_hist <= s2_folded_gh_dup_3_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_13_folded_hist <= s2_folded_gh_dup_3_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_12_folded_hist <= s2_folded_gh_dup_3_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_11_folded_hist <= s2_folded_gh_dup_3_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_10_folded_hist <= s2_folded_gh_dup_3_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_9_folded_hist <= s2_folded_gh_dup_3_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_8_folded_hist <= s2_folded_gh_dup_3_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_7_folded_hist <= s2_folded_gh_dup_3_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_6_folded_hist <= s2_folded_gh_dup_3_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_5_folded_hist <= s2_folded_gh_dup_3_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_4_folded_hist <= s2_folded_gh_dup_3_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_3_folded_hist <= s2_folded_gh_dup_3_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_2_folded_hist <= s2_folded_gh_dup_3_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_1_folded_hist <= s2_folded_gh_dup_3_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_folded_gh_dup_3_hist_0_folded_hist <= s2_folded_gh_dup_3_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:287:35, :288:35
|
|
s3_last_br_num_oh_dup_1 <= s2_last_br_num_oh_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:293:40, :294:40
|
|
s3_last_br_num_oh_dup_2 <= s2_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:293:40, :294:40
|
|
s3_last_br_num_oh_dup_3 <= s2_last_br_num_oh_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:293:40, :294:40
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 <=
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 <=
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 <=
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:299:46, :300:46
|
|
s3_ghist_ptr_dup_0_flag <= s2_ghist_ptr_dup_0_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35
|
|
s3_ghist_ptr_dup_0_value <= s2_ghist_ptr_dup_0_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35
|
|
s3_ghist_ptr_dup_1_flag <= s2_ghist_ptr_dup_1_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35
|
|
s3_ghist_ptr_dup_1_value <= s2_ghist_ptr_dup_1_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35
|
|
s3_ghist_ptr_dup_2_flag <= s2_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35
|
|
s3_ghist_ptr_dup_2_value <= s2_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35
|
|
s3_ghist_ptr_dup_3_flag <= s2_ghist_ptr_dup_3_flag; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35
|
|
s3_ghist_ptr_dup_3_value <= s2_ghist_ptr_dup_3_value; // src/main/scala/xiangshan/frontend/BPU.scala:324:35, :325:35
|
|
previous_s2_pred_pc_0 <= _predictors_io_out_s2_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_pc_1 <= _predictors_io_out_s2_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_pc_2 <= _predictors_io_out_s2_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_pc_3 <= _predictors_io_out_s2_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_0_br_taken_mask_0 <=
|
|
_predictors_io_out_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_0_br_taken_mask_1 <=
|
|
_predictors_io_out_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_0_slot_valids_0 <=
|
|
_predictors_io_out_s2_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_0_slot_valids_1 <=
|
|
_predictors_io_out_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_0_targets_0 <=
|
|
_predictors_io_out_s2_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_0_targets_1 <=
|
|
_predictors_io_out_s2_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_0_fallThroughAddr <=
|
|
_predictors_io_out_s2_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_0_is_br_sharing <=
|
|
_predictors_io_out_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_0_hit <= _predictors_io_out_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_1_br_taken_mask_0 <=
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_1_br_taken_mask_1 <=
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_1_slot_valids_0 <=
|
|
_predictors_io_out_s2_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_1_slot_valids_1 <=
|
|
_predictors_io_out_s2_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_1_targets_0 <=
|
|
_predictors_io_out_s2_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_1_targets_1 <=
|
|
_predictors_io_out_s2_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_1_fallThroughAddr <=
|
|
_predictors_io_out_s2_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_1_is_br_sharing <=
|
|
_predictors_io_out_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_1_hit <= _predictors_io_out_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_2_br_taken_mask_0 <=
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_2_br_taken_mask_1 <=
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_2_slot_valids_0 <=
|
|
_predictors_io_out_s2_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_2_slot_valids_1 <=
|
|
_predictors_io_out_s2_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_2_targets_0 <=
|
|
_predictors_io_out_s2_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_2_targets_1 <=
|
|
_predictors_io_out_s2_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_2_fallThroughAddr <=
|
|
_predictors_io_out_s2_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_2_is_br_sharing <=
|
|
_predictors_io_out_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_2_hit <= _predictors_io_out_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_3_br_taken_mask_0 <=
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_3_br_taken_mask_1 <=
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_3_slot_valids_0 <=
|
|
_predictors_io_out_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_3_slot_valids_1 <=
|
|
_predictors_io_out_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_3_targets_0 <=
|
|
_predictors_io_out_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_3_targets_1 <=
|
|
_predictors_io_out_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_3_fallThroughAddr <=
|
|
_predictors_io_out_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_3_is_br_sharing <=
|
|
_predictors_io_out_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
previous_s2_pred_full_pred_3_hit <= _predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :673:35
|
|
end
|
|
s0_last_br_num_oh_reg_dup_1 <= _s0_last_br_num_oh_dup_1_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_last_br_num_oh_reg_dup_2 <= _s0_last_br_num_oh_dup_2_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_last_br_num_oh_reg_dup_3 <= _s0_last_br_num_oh_dup_3_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 <=
|
|
_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:297:85, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_0_T | _ghv_wens_0_T_1 | _ghv_wens_0_T_2 | _ghv_wens_0_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_0 <= _ghv_write_datas_0_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_1_T | _ghv_wens_1_T_1 | _ghv_wens_1_T_2 | _ghv_wens_1_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_1 <= _ghv_write_datas_1_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_2_T | _ghv_wens_2_T_1 | _ghv_wens_2_T_2 | _ghv_wens_2_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_2 <= _ghv_write_datas_2_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_3_T | _ghv_wens_3_T_1 | _ghv_wens_3_T_2 | _ghv_wens_3_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_3 <= _ghv_write_datas_3_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_4_T | _ghv_wens_4_T_1 | _ghv_wens_4_T_2 | _ghv_wens_4_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_4 <= _ghv_write_datas_4_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_5_T | _ghv_wens_5_T_1 | _ghv_wens_5_T_2 | _ghv_wens_5_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_5 <= _ghv_write_datas_5_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_6_T | _ghv_wens_6_T_1 | _ghv_wens_6_T_2 | _ghv_wens_6_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_6 <= _ghv_write_datas_6_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_7_T | _ghv_wens_7_T_1 | _ghv_wens_7_T_2 | _ghv_wens_7_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_7 <= _ghv_write_datas_7_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_8_T | _ghv_wens_8_T_1 | _ghv_wens_8_T_2 | _ghv_wens_8_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_8 <= _ghv_write_datas_8_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_9_T | _ghv_wens_9_T_1 | _ghv_wens_9_T_2 | _ghv_wens_9_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_9 <= _ghv_write_datas_9_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_10_T | _ghv_wens_10_T_1 | _ghv_wens_10_T_2 | _ghv_wens_10_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_10 <= _ghv_write_datas_10_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_11_T | _ghv_wens_11_T_1 | _ghv_wens_11_T_2 | _ghv_wens_11_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_11 <= _ghv_write_datas_11_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_12_T | _ghv_wens_12_T_1 | _ghv_wens_12_T_2 | _ghv_wens_12_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_12 <= _ghv_write_datas_12_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_13_T | _ghv_wens_13_T_1 | _ghv_wens_13_T_2 | _ghv_wens_13_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_13 <= _ghv_write_datas_13_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_14_T | _ghv_wens_14_T_1 | _ghv_wens_14_T_2 | _ghv_wens_14_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_14 <= _ghv_write_datas_14_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_15_T | _ghv_wens_15_T_1 | _ghv_wens_15_T_2 | _ghv_wens_15_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_15 <= _ghv_write_datas_15_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_16_T | _ghv_wens_16_T_1 | _ghv_wens_16_T_2 | _ghv_wens_16_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_16 <= _ghv_write_datas_16_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_17_T | _ghv_wens_17_T_1 | _ghv_wens_17_T_2 | _ghv_wens_17_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_17 <= _ghv_write_datas_17_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_18_T | _ghv_wens_18_T_1 | _ghv_wens_18_T_2 | _ghv_wens_18_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_18 <= _ghv_write_datas_18_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_19_T | _ghv_wens_19_T_1 | _ghv_wens_19_T_2 | _ghv_wens_19_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_19 <= _ghv_write_datas_19_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_20_T | _ghv_wens_20_T_1 | _ghv_wens_20_T_2 | _ghv_wens_20_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_20 <= _ghv_write_datas_20_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_21_T | _ghv_wens_21_T_1 | _ghv_wens_21_T_2 | _ghv_wens_21_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_21 <= _ghv_write_datas_21_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_22_T | _ghv_wens_22_T_1 | _ghv_wens_22_T_2 | _ghv_wens_22_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_22 <= _ghv_write_datas_22_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_23_T | _ghv_wens_23_T_1 | _ghv_wens_23_T_2 | _ghv_wens_23_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_23 <= _ghv_write_datas_23_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_24_T | _ghv_wens_24_T_1 | _ghv_wens_24_T_2 | _ghv_wens_24_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_24 <= _ghv_write_datas_24_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_25_T | _ghv_wens_25_T_1 | _ghv_wens_25_T_2 | _ghv_wens_25_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_25 <= _ghv_write_datas_25_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_26_T | _ghv_wens_26_T_1 | _ghv_wens_26_T_2 | _ghv_wens_26_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_26 <= _ghv_write_datas_26_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_27_T | _ghv_wens_27_T_1 | _ghv_wens_27_T_2 | _ghv_wens_27_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_27 <= _ghv_write_datas_27_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_28_T | _ghv_wens_28_T_1 | _ghv_wens_28_T_2 | _ghv_wens_28_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_28 <= _ghv_write_datas_28_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_29_T | _ghv_wens_29_T_1 | _ghv_wens_29_T_2 | _ghv_wens_29_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_29 <= _ghv_write_datas_29_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_30_T | _ghv_wens_30_T_1 | _ghv_wens_30_T_2 | _ghv_wens_30_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_30 <= _ghv_write_datas_30_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_31_T | _ghv_wens_31_T_1 | _ghv_wens_31_T_2 | _ghv_wens_31_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_31 <= _ghv_write_datas_31_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_32_T | _ghv_wens_32_T_1 | _ghv_wens_32_T_2 | _ghv_wens_32_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_32 <= _ghv_write_datas_32_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_33_T | _ghv_wens_33_T_1 | _ghv_wens_33_T_2 | _ghv_wens_33_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_33 <= _ghv_write_datas_33_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_34_T | _ghv_wens_34_T_1 | _ghv_wens_34_T_2 | _ghv_wens_34_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_34 <= _ghv_write_datas_34_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_35_T | _ghv_wens_35_T_1 | _ghv_wens_35_T_2 | _ghv_wens_35_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_35 <= _ghv_write_datas_35_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_36_T | _ghv_wens_36_T_1 | _ghv_wens_36_T_2 | _ghv_wens_36_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_36 <= _ghv_write_datas_36_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_37_T | _ghv_wens_37_T_1 | _ghv_wens_37_T_2 | _ghv_wens_37_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_37 <= _ghv_write_datas_37_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_38_T | _ghv_wens_38_T_1 | _ghv_wens_38_T_2 | _ghv_wens_38_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_38 <= _ghv_write_datas_38_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_39_T | _ghv_wens_39_T_1 | _ghv_wens_39_T_2 | _ghv_wens_39_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_39 <= _ghv_write_datas_39_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_40_T | _ghv_wens_40_T_1 | _ghv_wens_40_T_2 | _ghv_wens_40_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_40 <= _ghv_write_datas_40_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_41_T | _ghv_wens_41_T_1 | _ghv_wens_41_T_2 | _ghv_wens_41_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_41 <= _ghv_write_datas_41_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_42_T | _ghv_wens_42_T_1 | _ghv_wens_42_T_2 | _ghv_wens_42_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_42 <= _ghv_write_datas_42_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_43_T | _ghv_wens_43_T_1 | _ghv_wens_43_T_2 | _ghv_wens_43_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_43 <= _ghv_write_datas_43_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_44_T | _ghv_wens_44_T_1 | _ghv_wens_44_T_2 | _ghv_wens_44_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_44 <= _ghv_write_datas_44_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_45_T | _ghv_wens_45_T_1 | _ghv_wens_45_T_2 | _ghv_wens_45_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_45 <= _ghv_write_datas_45_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_46_T | _ghv_wens_46_T_1 | _ghv_wens_46_T_2 | _ghv_wens_46_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_46 <= _ghv_write_datas_46_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_47_T | _ghv_wens_47_T_1 | _ghv_wens_47_T_2 | _ghv_wens_47_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_47 <= _ghv_write_datas_47_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_48_T | _ghv_wens_48_T_1 | _ghv_wens_48_T_2 | _ghv_wens_48_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_48 <= _ghv_write_datas_48_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_49_T | _ghv_wens_49_T_1 | _ghv_wens_49_T_2 | _ghv_wens_49_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_49 <= _ghv_write_datas_49_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_50_T | _ghv_wens_50_T_1 | _ghv_wens_50_T_2 | _ghv_wens_50_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_50 <= _ghv_write_datas_50_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_51_T | _ghv_wens_51_T_1 | _ghv_wens_51_T_2 | _ghv_wens_51_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_51 <= _ghv_write_datas_51_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_52_T | _ghv_wens_52_T_1 | _ghv_wens_52_T_2 | _ghv_wens_52_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_52 <= _ghv_write_datas_52_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_53_T | _ghv_wens_53_T_1 | _ghv_wens_53_T_2 | _ghv_wens_53_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_53 <= _ghv_write_datas_53_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_54_T | _ghv_wens_54_T_1 | _ghv_wens_54_T_2 | _ghv_wens_54_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_54 <= _ghv_write_datas_54_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_55_T | _ghv_wens_55_T_1 | _ghv_wens_55_T_2 | _ghv_wens_55_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_55 <= _ghv_write_datas_55_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_56_T | _ghv_wens_56_T_1 | _ghv_wens_56_T_2 | _ghv_wens_56_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_56 <= _ghv_write_datas_56_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_57_T | _ghv_wens_57_T_1 | _ghv_wens_57_T_2 | _ghv_wens_57_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_57 <= _ghv_write_datas_57_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_58_T | _ghv_wens_58_T_1 | _ghv_wens_58_T_2 | _ghv_wens_58_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_58 <= _ghv_write_datas_58_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_59_T | _ghv_wens_59_T_1 | _ghv_wens_59_T_2 | _ghv_wens_59_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_59 <= _ghv_write_datas_59_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_60_T | _ghv_wens_60_T_1 | _ghv_wens_60_T_2 | _ghv_wens_60_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_60 <= _ghv_write_datas_60_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_61_T | _ghv_wens_61_T_1 | _ghv_wens_61_T_2 | _ghv_wens_61_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_61 <= _ghv_write_datas_61_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_62_T | _ghv_wens_62_T_1 | _ghv_wens_62_T_2 | _ghv_wens_62_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_62 <= _ghv_write_datas_62_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_63_T | _ghv_wens_63_T_1 | _ghv_wens_63_T_2 | _ghv_wens_63_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_63 <= _ghv_write_datas_63_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_64_T | _ghv_wens_64_T_1 | _ghv_wens_64_T_2 | _ghv_wens_64_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_64 <= _ghv_write_datas_64_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_65_T | _ghv_wens_65_T_1 | _ghv_wens_65_T_2 | _ghv_wens_65_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_65 <= _ghv_write_datas_65_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_66_T | _ghv_wens_66_T_1 | _ghv_wens_66_T_2 | _ghv_wens_66_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_66 <= _ghv_write_datas_66_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_67_T | _ghv_wens_67_T_1 | _ghv_wens_67_T_2 | _ghv_wens_67_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_67 <= _ghv_write_datas_67_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_68_T | _ghv_wens_68_T_1 | _ghv_wens_68_T_2 | _ghv_wens_68_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_68 <= _ghv_write_datas_68_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_69_T | _ghv_wens_69_T_1 | _ghv_wens_69_T_2 | _ghv_wens_69_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_69 <= _ghv_write_datas_69_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_70_T | _ghv_wens_70_T_1 | _ghv_wens_70_T_2 | _ghv_wens_70_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_70 <= _ghv_write_datas_70_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_71_T | _ghv_wens_71_T_1 | _ghv_wens_71_T_2 | _ghv_wens_71_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_71 <= _ghv_write_datas_71_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_72_T | _ghv_wens_72_T_1 | _ghv_wens_72_T_2 | _ghv_wens_72_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_72 <= _ghv_write_datas_72_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_73_T | _ghv_wens_73_T_1 | _ghv_wens_73_T_2 | _ghv_wens_73_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_73 <= _ghv_write_datas_73_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_74_T | _ghv_wens_74_T_1 | _ghv_wens_74_T_2 | _ghv_wens_74_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_74 <= _ghv_write_datas_74_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_75_T | _ghv_wens_75_T_1 | _ghv_wens_75_T_2 | _ghv_wens_75_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_75 <= _ghv_write_datas_75_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_76_T | _ghv_wens_76_T_1 | _ghv_wens_76_T_2 | _ghv_wens_76_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_76 <= _ghv_write_datas_76_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_77_T | _ghv_wens_77_T_1 | _ghv_wens_77_T_2 | _ghv_wens_77_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_77 <= _ghv_write_datas_77_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_78_T | _ghv_wens_78_T_1 | _ghv_wens_78_T_2 | _ghv_wens_78_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_78 <= _ghv_write_datas_78_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_79_T | _ghv_wens_79_T_1 | _ghv_wens_79_T_2 | _ghv_wens_79_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_79 <= _ghv_write_datas_79_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_80_T | _ghv_wens_80_T_1 | _ghv_wens_80_T_2 | _ghv_wens_80_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_80 <= _ghv_write_datas_80_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_81_T | _ghv_wens_81_T_1 | _ghv_wens_81_T_2 | _ghv_wens_81_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_81 <= _ghv_write_datas_81_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_82_T | _ghv_wens_82_T_1 | _ghv_wens_82_T_2 | _ghv_wens_82_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_82 <= _ghv_write_datas_82_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_83_T | _ghv_wens_83_T_1 | _ghv_wens_83_T_2 | _ghv_wens_83_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_83 <= _ghv_write_datas_83_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_84_T | _ghv_wens_84_T_1 | _ghv_wens_84_T_2 | _ghv_wens_84_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_84 <= _ghv_write_datas_84_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_85_T | _ghv_wens_85_T_1 | _ghv_wens_85_T_2 | _ghv_wens_85_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_85 <= _ghv_write_datas_85_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_86_T | _ghv_wens_86_T_1 | _ghv_wens_86_T_2 | _ghv_wens_86_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_86 <= _ghv_write_datas_86_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_87_T | _ghv_wens_87_T_1 | _ghv_wens_87_T_2 | _ghv_wens_87_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_87 <= _ghv_write_datas_87_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_88_T | _ghv_wens_88_T_1 | _ghv_wens_88_T_2 | _ghv_wens_88_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_88 <= _ghv_write_datas_88_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_89_T | _ghv_wens_89_T_1 | _ghv_wens_89_T_2 | _ghv_wens_89_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_89 <= _ghv_write_datas_89_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_90_T | _ghv_wens_90_T_1 | _ghv_wens_90_T_2 | _ghv_wens_90_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_90 <= _ghv_write_datas_90_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_91_T | _ghv_wens_91_T_1 | _ghv_wens_91_T_2 | _ghv_wens_91_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_91 <= _ghv_write_datas_91_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_92_T | _ghv_wens_92_T_1 | _ghv_wens_92_T_2 | _ghv_wens_92_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_92 <= _ghv_write_datas_92_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_93_T | _ghv_wens_93_T_1 | _ghv_wens_93_T_2 | _ghv_wens_93_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_93 <= _ghv_write_datas_93_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_94_T | _ghv_wens_94_T_1 | _ghv_wens_94_T_2 | _ghv_wens_94_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_94 <= _ghv_write_datas_94_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_95_T | _ghv_wens_95_T_1 | _ghv_wens_95_T_2 | _ghv_wens_95_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_95 <= _ghv_write_datas_95_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_96_T | _ghv_wens_96_T_1 | _ghv_wens_96_T_2 | _ghv_wens_96_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_96 <= _ghv_write_datas_96_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_97_T | _ghv_wens_97_T_1 | _ghv_wens_97_T_2 | _ghv_wens_97_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_97 <= _ghv_write_datas_97_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_98_T | _ghv_wens_98_T_1 | _ghv_wens_98_T_2 | _ghv_wens_98_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_98 <= _ghv_write_datas_98_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_99_T | _ghv_wens_99_T_1 | _ghv_wens_99_T_2 | _ghv_wens_99_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_99 <= _ghv_write_datas_99_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_100_T | _ghv_wens_100_T_1 | _ghv_wens_100_T_2 | _ghv_wens_100_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_100 <= _ghv_write_datas_100_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_101_T | _ghv_wens_101_T_1 | _ghv_wens_101_T_2 | _ghv_wens_101_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_101 <= _ghv_write_datas_101_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_102_T | _ghv_wens_102_T_1 | _ghv_wens_102_T_2 | _ghv_wens_102_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_102 <= _ghv_write_datas_102_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_103_T | _ghv_wens_103_T_1 | _ghv_wens_103_T_2 | _ghv_wens_103_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_103 <= _ghv_write_datas_103_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_104_T | _ghv_wens_104_T_1 | _ghv_wens_104_T_2 | _ghv_wens_104_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_104 <= _ghv_write_datas_104_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_105_T | _ghv_wens_105_T_1 | _ghv_wens_105_T_2 | _ghv_wens_105_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_105 <= _ghv_write_datas_105_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_106_T | _ghv_wens_106_T_1 | _ghv_wens_106_T_2 | _ghv_wens_106_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_106 <= _ghv_write_datas_106_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_107_T | _ghv_wens_107_T_1 | _ghv_wens_107_T_2 | _ghv_wens_107_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_107 <= _ghv_write_datas_107_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_108_T | _ghv_wens_108_T_1 | _ghv_wens_108_T_2 | _ghv_wens_108_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_108 <= _ghv_write_datas_108_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_109_T | _ghv_wens_109_T_1 | _ghv_wens_109_T_2 | _ghv_wens_109_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_109 <= _ghv_write_datas_109_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_110_T | _ghv_wens_110_T_1 | _ghv_wens_110_T_2 | _ghv_wens_110_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_110 <= _ghv_write_datas_110_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_111_T | _ghv_wens_111_T_1 | _ghv_wens_111_T_2 | _ghv_wens_111_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_111 <= _ghv_write_datas_111_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_112_T | _ghv_wens_112_T_1 | _ghv_wens_112_T_2 | _ghv_wens_112_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_112 <= _ghv_write_datas_112_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_113_T | _ghv_wens_113_T_1 | _ghv_wens_113_T_2 | _ghv_wens_113_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_113 <= _ghv_write_datas_113_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_114_T | _ghv_wens_114_T_1 | _ghv_wens_114_T_2 | _ghv_wens_114_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_114 <= _ghv_write_datas_114_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_115_T | _ghv_wens_115_T_1 | _ghv_wens_115_T_2 | _ghv_wens_115_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_115 <= _ghv_write_datas_115_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_116_T | _ghv_wens_116_T_1 | _ghv_wens_116_T_2 | _ghv_wens_116_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_116 <= _ghv_write_datas_116_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_117_T | _ghv_wens_117_T_1 | _ghv_wens_117_T_2 | _ghv_wens_117_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_117 <= _ghv_write_datas_117_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_118_T | _ghv_wens_118_T_1 | _ghv_wens_118_T_2 | _ghv_wens_118_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_118 <= _ghv_write_datas_118_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_119_T | _ghv_wens_119_T_1 | _ghv_wens_119_T_2 | _ghv_wens_119_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_119 <= _ghv_write_datas_119_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_120_T | _ghv_wens_120_T_1 | _ghv_wens_120_T_2 | _ghv_wens_120_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_120 <= _ghv_write_datas_120_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_121_T | _ghv_wens_121_T_1 | _ghv_wens_121_T_2 | _ghv_wens_121_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_121 <= _ghv_write_datas_121_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_122_T | _ghv_wens_122_T_1 | _ghv_wens_122_T_2 | _ghv_wens_122_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_122 <= _ghv_write_datas_122_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_123_T | _ghv_wens_123_T_1 | _ghv_wens_123_T_2 | _ghv_wens_123_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_123 <= _ghv_write_datas_123_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_124_T | _ghv_wens_124_T_1 | _ghv_wens_124_T_2 | _ghv_wens_124_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_124 <= _ghv_write_datas_124_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_125_T | _ghv_wens_125_T_1 | _ghv_wens_125_T_2 | _ghv_wens_125_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_125 <= _ghv_write_datas_125_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_126_T | _ghv_wens_126_T_1 | _ghv_wens_126_T_2 | _ghv_wens_126_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_126 <= _ghv_write_datas_126_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_127_T | _ghv_wens_127_T_1 | _ghv_wens_127_T_2 | _ghv_wens_127_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_127 <= _ghv_write_datas_127_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_128_T | _ghv_wens_128_T_1 | _ghv_wens_128_T_2 | _ghv_wens_128_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_128 <= _ghv_write_datas_128_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_129_T | _ghv_wens_129_T_1 | _ghv_wens_129_T_2 | _ghv_wens_129_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_129 <= _ghv_write_datas_129_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_130_T | _ghv_wens_130_T_1 | _ghv_wens_130_T_2 | _ghv_wens_130_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_130 <= _ghv_write_datas_130_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_131_T | _ghv_wens_131_T_1 | _ghv_wens_131_T_2 | _ghv_wens_131_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_131 <= _ghv_write_datas_131_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_132_T | _ghv_wens_132_T_1 | _ghv_wens_132_T_2 | _ghv_wens_132_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_132 <= _ghv_write_datas_132_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_133_T | _ghv_wens_133_T_1 | _ghv_wens_133_T_2 | _ghv_wens_133_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_133 <= _ghv_write_datas_133_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_134_T | _ghv_wens_134_T_1 | _ghv_wens_134_T_2 | _ghv_wens_134_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_134 <= _ghv_write_datas_134_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_135_T | _ghv_wens_135_T_1 | _ghv_wens_135_T_2 | _ghv_wens_135_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_135 <= _ghv_write_datas_135_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_136_T | _ghv_wens_136_T_1 | _ghv_wens_136_T_2 | _ghv_wens_136_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_136 <= _ghv_write_datas_136_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_137_T | _ghv_wens_137_T_1 | _ghv_wens_137_T_2 | _ghv_wens_137_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_137 <= _ghv_write_datas_137_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_138_T | _ghv_wens_138_T_1 | _ghv_wens_138_T_2 | _ghv_wens_138_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_138 <= _ghv_write_datas_138_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_139_T | _ghv_wens_139_T_1 | _ghv_wens_139_T_2 | _ghv_wens_139_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_139 <= _ghv_write_datas_139_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_140_T | _ghv_wens_140_T_1 | _ghv_wens_140_T_2 | _ghv_wens_140_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_140 <= _ghv_write_datas_140_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_141_T | _ghv_wens_141_T_1 | _ghv_wens_141_T_2 | _ghv_wens_141_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_141 <= _ghv_write_datas_141_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_142_T | _ghv_wens_142_T_1 | _ghv_wens_142_T_2 | _ghv_wens_142_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_142 <= _ghv_write_datas_142_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_143_T | _ghv_wens_143_T_1 | _ghv_wens_143_T_2 | _ghv_wens_143_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_143 <= _ghv_write_datas_143_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_144_T | _ghv_wens_144_T_1 | _ghv_wens_144_T_2 | _ghv_wens_144_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_144 <= _ghv_write_datas_144_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_145_T | _ghv_wens_145_T_1 | _ghv_wens_145_T_2 | _ghv_wens_145_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_145 <= _ghv_write_datas_145_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_146_T | _ghv_wens_146_T_1 | _ghv_wens_146_T_2 | _ghv_wens_146_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_146 <= _ghv_write_datas_146_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_147_T | _ghv_wens_147_T_1 | _ghv_wens_147_T_2 | _ghv_wens_147_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_147 <= _ghv_write_datas_147_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_148_T | _ghv_wens_148_T_1 | _ghv_wens_148_T_2 | _ghv_wens_148_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_148 <= _ghv_write_datas_148_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_149_T | _ghv_wens_149_T_1 | _ghv_wens_149_T_2 | _ghv_wens_149_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_149 <= _ghv_write_datas_149_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_150_T | _ghv_wens_150_T_1 | _ghv_wens_150_T_2 | _ghv_wens_150_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_150 <= _ghv_write_datas_150_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_151_T | _ghv_wens_151_T_1 | _ghv_wens_151_T_2 | _ghv_wens_151_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_151 <= _ghv_write_datas_151_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_152_T | _ghv_wens_152_T_1 | _ghv_wens_152_T_2 | _ghv_wens_152_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_152 <= _ghv_write_datas_152_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_153_T | _ghv_wens_153_T_1 | _ghv_wens_153_T_2 | _ghv_wens_153_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_153 <= _ghv_write_datas_153_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_154_T | _ghv_wens_154_T_1 | _ghv_wens_154_T_2 | _ghv_wens_154_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_154 <= _ghv_write_datas_154_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_155_T | _ghv_wens_155_T_1 | _ghv_wens_155_T_2 | _ghv_wens_155_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_155 <= _ghv_write_datas_155_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_156_T | _ghv_wens_156_T_1 | _ghv_wens_156_T_2 | _ghv_wens_156_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_156 <= _ghv_write_datas_156_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_157_T | _ghv_wens_157_T_1 | _ghv_wens_157_T_2 | _ghv_wens_157_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_157 <= _ghv_write_datas_157_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_158_T | _ghv_wens_158_T_1 | _ghv_wens_158_T_2 | _ghv_wens_158_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_158 <= _ghv_write_datas_158_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_159_T | _ghv_wens_159_T_1 | _ghv_wens_159_T_2 | _ghv_wens_159_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_159 <= _ghv_write_datas_159_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_160_T | _ghv_wens_160_T_1 | _ghv_wens_160_T_2 | _ghv_wens_160_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_160 <= _ghv_write_datas_160_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_161_T | _ghv_wens_161_T_1 | _ghv_wens_161_T_2 | _ghv_wens_161_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_161 <= _ghv_write_datas_161_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_162_T | _ghv_wens_162_T_1 | _ghv_wens_162_T_2 | _ghv_wens_162_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_162 <= _ghv_write_datas_162_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_163_T | _ghv_wens_163_T_1 | _ghv_wens_163_T_2 | _ghv_wens_163_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_163 <= _ghv_write_datas_163_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_164_T | _ghv_wens_164_T_1 | _ghv_wens_164_T_2 | _ghv_wens_164_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_164 <= _ghv_write_datas_164_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_165_T | _ghv_wens_165_T_1 | _ghv_wens_165_T_2 | _ghv_wens_165_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_165 <= _ghv_write_datas_165_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_166_T | _ghv_wens_166_T_1 | _ghv_wens_166_T_2 | _ghv_wens_166_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_166 <= _ghv_write_datas_166_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_167_T | _ghv_wens_167_T_1 | _ghv_wens_167_T_2 | _ghv_wens_167_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_167 <= _ghv_write_datas_167_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_168_T | _ghv_wens_168_T_1 | _ghv_wens_168_T_2 | _ghv_wens_168_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_168 <= _ghv_write_datas_168_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_169_T | _ghv_wens_169_T_1 | _ghv_wens_169_T_2 | _ghv_wens_169_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_169 <= _ghv_write_datas_169_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_170_T | _ghv_wens_170_T_1 | _ghv_wens_170_T_2 | _ghv_wens_170_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_170 <= _ghv_write_datas_170_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_171_T | _ghv_wens_171_T_1 | _ghv_wens_171_T_2 | _ghv_wens_171_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_171 <= _ghv_write_datas_171_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_172_T | _ghv_wens_172_T_1 | _ghv_wens_172_T_2 | _ghv_wens_172_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_172 <= _ghv_write_datas_172_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_173_T | _ghv_wens_173_T_1 | _ghv_wens_173_T_2 | _ghv_wens_173_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_173 <= _ghv_write_datas_173_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_174_T | _ghv_wens_174_T_1 | _ghv_wens_174_T_2 | _ghv_wens_174_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_174 <= _ghv_write_datas_174_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_175_T | _ghv_wens_175_T_1 | _ghv_wens_175_T_2 | _ghv_wens_175_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_175 <= _ghv_write_datas_175_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_176_T | _ghv_wens_176_T_1 | _ghv_wens_176_T_2 | _ghv_wens_176_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_176 <= _ghv_write_datas_176_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_177_T | _ghv_wens_177_T_1 | _ghv_wens_177_T_2 | _ghv_wens_177_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_177 <= _ghv_write_datas_177_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_178_T | _ghv_wens_178_T_1 | _ghv_wens_178_T_2 | _ghv_wens_178_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_178 <= _ghv_write_datas_178_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_179_T | _ghv_wens_179_T_1 | _ghv_wens_179_T_2 | _ghv_wens_179_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_179 <= _ghv_write_datas_179_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_180_T | _ghv_wens_180_T_1 | _ghv_wens_180_T_2 | _ghv_wens_180_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_180 <= _ghv_write_datas_180_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_181_T | _ghv_wens_181_T_1 | _ghv_wens_181_T_2 | _ghv_wens_181_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_181 <= _ghv_write_datas_181_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_182_T | _ghv_wens_182_T_1 | _ghv_wens_182_T_2 | _ghv_wens_182_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_182 <= _ghv_write_datas_182_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_183_T | _ghv_wens_183_T_1 | _ghv_wens_183_T_2 | _ghv_wens_183_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_183 <= _ghv_write_datas_183_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_184_T | _ghv_wens_184_T_1 | _ghv_wens_184_T_2 | _ghv_wens_184_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_184 <= _ghv_write_datas_184_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_185_T | _ghv_wens_185_T_1 | _ghv_wens_185_T_2 | _ghv_wens_185_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_185 <= _ghv_write_datas_185_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_186_T | _ghv_wens_186_T_1 | _ghv_wens_186_T_2 | _ghv_wens_186_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_186 <= _ghv_write_datas_186_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_187_T | _ghv_wens_187_T_1 | _ghv_wens_187_T_2 | _ghv_wens_187_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_187 <= _ghv_write_datas_187_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_188_T | _ghv_wens_188_T_1 | _ghv_wens_188_T_2 | _ghv_wens_188_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_188 <= _ghv_write_datas_188_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_189_T | _ghv_wens_189_T_1 | _ghv_wens_189_T_2 | _ghv_wens_189_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_189 <= _ghv_write_datas_189_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_190_T | _ghv_wens_190_T_1 | _ghv_wens_190_T_2 | _ghv_wens_190_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_190 <= _ghv_write_datas_190_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_191_T | _ghv_wens_191_T_1 | _ghv_wens_191_T_2 | _ghv_wens_191_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_191 <= _ghv_write_datas_191_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_192_T | _ghv_wens_192_T_1 | _ghv_wens_192_T_2 | _ghv_wens_192_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_192 <= _ghv_write_datas_192_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_193_T | _ghv_wens_193_T_1 | _ghv_wens_193_T_2 | _ghv_wens_193_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_193 <= _ghv_write_datas_193_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_194_T | _ghv_wens_194_T_1 | _ghv_wens_194_T_2 | _ghv_wens_194_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_194 <= _ghv_write_datas_194_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_195_T | _ghv_wens_195_T_1 | _ghv_wens_195_T_2 | _ghv_wens_195_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_195 <= _ghv_write_datas_195_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_196_T | _ghv_wens_196_T_1 | _ghv_wens_196_T_2 | _ghv_wens_196_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_196 <= _ghv_write_datas_196_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_197_T | _ghv_wens_197_T_1 | _ghv_wens_197_T_2 | _ghv_wens_197_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_197 <= _ghv_write_datas_197_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_198_T | _ghv_wens_198_T_1 | _ghv_wens_198_T_2 | _ghv_wens_198_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_198 <= _ghv_write_datas_198_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_199_T | _ghv_wens_199_T_1 | _ghv_wens_199_T_2 | _ghv_wens_199_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_199 <= _ghv_write_datas_199_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_200_T | _ghv_wens_200_T_1 | _ghv_wens_200_T_2 | _ghv_wens_200_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_200 <= _ghv_write_datas_200_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_201_T | _ghv_wens_201_T_1 | _ghv_wens_201_T_2 | _ghv_wens_201_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_201 <= _ghv_write_datas_201_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_202_T | _ghv_wens_202_T_1 | _ghv_wens_202_T_2 | _ghv_wens_202_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_202 <= _ghv_write_datas_202_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_203_T | _ghv_wens_203_T_1 | _ghv_wens_203_T_2 | _ghv_wens_203_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_203 <= _ghv_write_datas_203_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_204_T | _ghv_wens_204_T_1 | _ghv_wens_204_T_2 | _ghv_wens_204_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_204 <= _ghv_write_datas_204_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_205_T | _ghv_wens_205_T_1 | _ghv_wens_205_T_2 | _ghv_wens_205_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_205 <= _ghv_write_datas_205_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_206_T | _ghv_wens_206_T_1 | _ghv_wens_206_T_2 | _ghv_wens_206_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_206 <= _ghv_write_datas_206_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_207_T | _ghv_wens_207_T_1 | _ghv_wens_207_T_2 | _ghv_wens_207_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_207 <= _ghv_write_datas_207_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_208_T | _ghv_wens_208_T_1 | _ghv_wens_208_T_2 | _ghv_wens_208_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_208 <= _ghv_write_datas_208_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_209_T | _ghv_wens_209_T_1 | _ghv_wens_209_T_2 | _ghv_wens_209_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_209 <= _ghv_write_datas_209_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_210_T | _ghv_wens_210_T_1 | _ghv_wens_210_T_2 | _ghv_wens_210_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_210 <= _ghv_write_datas_210_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_211_T | _ghv_wens_211_T_1 | _ghv_wens_211_T_2 | _ghv_wens_211_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_211 <= _ghv_write_datas_211_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_212_T | _ghv_wens_212_T_1 | _ghv_wens_212_T_2 | _ghv_wens_212_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_212 <= _ghv_write_datas_212_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_213_T | _ghv_wens_213_T_1 | _ghv_wens_213_T_2 | _ghv_wens_213_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_213 <= _ghv_write_datas_213_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_214_T | _ghv_wens_214_T_1 | _ghv_wens_214_T_2 | _ghv_wens_214_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_214 <= _ghv_write_datas_214_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_215_T | _ghv_wens_215_T_1 | _ghv_wens_215_T_2 | _ghv_wens_215_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_215 <= _ghv_write_datas_215_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_216_T | _ghv_wens_216_T_1 | _ghv_wens_216_T_2 | _ghv_wens_216_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_216 <= _ghv_write_datas_216_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_217_T | _ghv_wens_217_T_1 | _ghv_wens_217_T_2 | _ghv_wens_217_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_217 <= _ghv_write_datas_217_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_218_T | _ghv_wens_218_T_1 | _ghv_wens_218_T_2 | _ghv_wens_218_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_218 <= _ghv_write_datas_218_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_219_T | _ghv_wens_219_T_1 | _ghv_wens_219_T_2 | _ghv_wens_219_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_219 <= _ghv_write_datas_219_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_220_T | _ghv_wens_220_T_1 | _ghv_wens_220_T_2 | _ghv_wens_220_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_220 <= _ghv_write_datas_220_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_221_T | _ghv_wens_221_T_1 | _ghv_wens_221_T_2 | _ghv_wens_221_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_221 <= _ghv_write_datas_221_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_222_T | _ghv_wens_222_T_1 | _ghv_wens_222_T_2 | _ghv_wens_222_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_222 <= _ghv_write_datas_222_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_223_T | _ghv_wens_223_T_1 | _ghv_wens_223_T_2 | _ghv_wens_223_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_223 <= _ghv_write_datas_223_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_224_T | _ghv_wens_224_T_1 | _ghv_wens_224_T_2 | _ghv_wens_224_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_224 <= _ghv_write_datas_224_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_225_T | _ghv_wens_225_T_1 | _ghv_wens_225_T_2 | _ghv_wens_225_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_225 <= _ghv_write_datas_225_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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if (_ghv_wens_226_T | _ghv_wens_226_T_1 | _ghv_wens_226_T_2 | _ghv_wens_226_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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ghv_226 <= _ghv_write_datas_226_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_227_T | _ghv_wens_227_T_1 | _ghv_wens_227_T_2 | _ghv_wens_227_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_227 <= _ghv_write_datas_227_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_228_T | _ghv_wens_228_T_1 | _ghv_wens_228_T_2 | _ghv_wens_228_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_228 <= _ghv_write_datas_228_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_229_T | _ghv_wens_229_T_1 | _ghv_wens_229_T_2 | _ghv_wens_229_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_229 <= _ghv_write_datas_229_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_230_T | _ghv_wens_230_T_1 | _ghv_wens_230_T_2 | _ghv_wens_230_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_230 <= _ghv_write_datas_230_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_231_T | _ghv_wens_231_T_1 | _ghv_wens_231_T_2 | _ghv_wens_231_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_231 <= _ghv_write_datas_231_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_232_T | _ghv_wens_232_T_1 | _ghv_wens_232_T_2 | _ghv_wens_232_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_232 <= _ghv_write_datas_232_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_233_T | _ghv_wens_233_T_1 | _ghv_wens_233_T_2 | _ghv_wens_233_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_233 <= _ghv_write_datas_233_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_234_T | _ghv_wens_234_T_1 | _ghv_wens_234_T_2 | _ghv_wens_234_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_234 <= _ghv_write_datas_234_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_235_T | _ghv_wens_235_T_1 | _ghv_wens_235_T_2 | _ghv_wens_235_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
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|
ghv_235 <= _ghv_write_datas_235_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_236_T | _ghv_wens_236_T_1 | _ghv_wens_236_T_2 | _ghv_wens_236_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_236 <= _ghv_write_datas_236_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_237_T | _ghv_wens_237_T_1 | _ghv_wens_237_T_2 | _ghv_wens_237_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_237 <= _ghv_write_datas_237_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_238_T | _ghv_wens_238_T_1 | _ghv_wens_238_T_2 | _ghv_wens_238_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_238 <= _ghv_write_datas_238_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_239_T | _ghv_wens_239_T_1 | _ghv_wens_239_T_2 | _ghv_wens_239_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_239 <= _ghv_write_datas_239_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_240_T | _ghv_wens_240_T_1 | _ghv_wens_240_T_2 | _ghv_wens_240_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_240 <= _ghv_write_datas_240_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_241_T | _ghv_wens_241_T_1 | _ghv_wens_241_T_2 | _ghv_wens_241_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_241 <= _ghv_write_datas_241_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
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|
if (_ghv_wens_242_T | _ghv_wens_242_T_1 | _ghv_wens_242_T_2 | _ghv_wens_242_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_242 <= _ghv_write_datas_242_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_243_T | _ghv_wens_243_T_1 | _ghv_wens_243_T_2 | _ghv_wens_243_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_243 <= _ghv_write_datas_243_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_244_T | _ghv_wens_244_T_1 | _ghv_wens_244_T_2 | _ghv_wens_244_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_244 <= _ghv_write_datas_244_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_245_T | _ghv_wens_245_T_1 | _ghv_wens_245_T_2 | _ghv_wens_245_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_245 <= _ghv_write_datas_245_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_246_T | _ghv_wens_246_T_1 | _ghv_wens_246_T_2 | _ghv_wens_246_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_246 <= _ghv_write_datas_246_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_247_T | _ghv_wens_247_T_1 | _ghv_wens_247_T_2 | _ghv_wens_247_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_247 <= _ghv_write_datas_247_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_248_T | _ghv_wens_248_T_1 | _ghv_wens_248_T_2 | _ghv_wens_248_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_248 <= _ghv_write_datas_248_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_249_T | _ghv_wens_249_T_1 | _ghv_wens_249_T_2 | _ghv_wens_249_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_249 <= _ghv_write_datas_249_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_250_T | _ghv_wens_250_T_1 | _ghv_wens_250_T_2 | _ghv_wens_250_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_250 <= _ghv_write_datas_250_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_251_T | _ghv_wens_251_T_1 | _ghv_wens_251_T_2 | _ghv_wens_251_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_251 <= _ghv_write_datas_251_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_252_T | _ghv_wens_252_T_1 | _ghv_wens_252_T_2 | _ghv_wens_252_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_252 <= _ghv_write_datas_252_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_253_T | _ghv_wens_253_T_1 | _ghv_wens_253_T_2 | _ghv_wens_253_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_253 <= _ghv_write_datas_253_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_254_T | _ghv_wens_254_T_1 | _ghv_wens_254_T_2 | _ghv_wens_254_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_254 <= _ghv_write_datas_254_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
if (_ghv_wens_255_T | _ghv_wens_255_T_1 | _ghv_wens_255_T_2 | _ghv_wens_255_T_3) // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, :875:113
|
|
ghv_255 <= _ghv_write_datas_255_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:311:20, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ghist_ptr_reg_dup_0_flag <= _s0_ghist_ptr_dup_0_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ghist_ptr_reg_dup_0_value <= _s0_ghist_ptr_dup_0_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ghist_ptr_reg_dup_1_flag <= _s0_ghist_ptr_dup_1_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ghist_ptr_reg_dup_1_value <= _s0_ghist_ptr_dup_1_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ghist_ptr_reg_dup_2_flag <= _s0_ghist_ptr_dup_2_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ghist_ptr_reg_dup_2_value <= _s0_ghist_ptr_dup_2_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ghist_ptr_reg_dup_3_flag <= _s0_ghist_ptr_dup_3_ppm_out_res_flag; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_ghist_ptr_reg_dup_3_value <= _s0_ghist_ptr_dup_3_ppm_out_res_value; // src/main/scala/xiangshan/frontend/BPU.scala:322:63, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
do_redirect_dup_3_valid <= io_ftq_to_bpu_redirect_valid; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_level <= io_ftq_to_bpu_redirect_bits_level; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_pc <= io_ftq_to_bpu_redirect_bits_cfiUpdate_pc; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_pd_isRVC <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRVC; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_pd_isCall <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isCall; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_pd_isRet <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_pd_isRet; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_ssp <= io_ftq_to_bpu_redirect_bits_cfiUpdate_ssp; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_sctr <= io_ftq_to_bpu_redirect_bits_cfiUpdate_sctr; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_TOSW_flag <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_TOSW_value <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSW_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_TOSR_flag <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_TOSR_value <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_TOSR_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_NOS_flag <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_NOS_value <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_NOS_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_folded_hist_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3 <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_afhob_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_lastBrNumOH; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_flag <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_flag; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_histPtr_value; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_target <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_target; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_taken <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_taken; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
thisBrNumOH_dup_shiftAmount <= io_ftq_to_bpu_redirect_bits_cfiUpdate_shift; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_addIntoHist <=
|
|
io_ftq_to_bpu_redirect_bits_cfiUpdate_addIntoHist; // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
if (s1_fire_dup_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:374:60
|
|
previous_s1_pred_info_hit_0 <= _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40
|
|
previous_s1_pred_info_hit_1 <= _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40
|
|
previous_s1_pred_info_hit_2 <= _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40
|
|
previous_s1_pred_info_hit_3 <= _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40
|
|
previous_s1_pred_info_target_0 <=
|
|
(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
? _predictors_io_out_s1_full_pred_0_targets_0
|
|
: 39'h0)
|
|
| (~_cfiIndex_bits_WIRE_18_0 & s1_pred_info_takenMask_0_1
|
|
& _predictors_io_out_s1_full_pred_0_hit
|
|
? _predictors_io_out_s1_full_pred_0_targets_1
|
|
: 39'h0)
|
|
| ({s1_pred_info_takenMask_0_1, _cfiIndex_bits_WIRE_18_0} == 2'h0
|
|
& _predictors_io_out_s1_full_pred_0_hit
|
|
? _predictors_io_out_s1_full_pred_0_fallThroughAddr
|
|
: 39'h0) | _GEN_4; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25
|
|
previous_s1_pred_info_target_1 <=
|
|
(_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit
|
|
? _predictors_io_out_s1_full_pred_1_targets_0
|
|
: 39'h0)
|
|
| (~_cfiIndex_bits_WIRE_22_0 & s1_pred_info_takenMask_1_1
|
|
& _predictors_io_out_s1_full_pred_1_hit
|
|
? _predictors_io_out_s1_full_pred_1_targets_1
|
|
: 39'h0)
|
|
| ({s1_pred_info_takenMask_1_1, _cfiIndex_bits_WIRE_22_0} == 2'h0
|
|
& _predictors_io_out_s1_full_pred_1_hit
|
|
? _predictors_io_out_s1_full_pred_1_fallThroughAddr
|
|
: 39'h0) | _GEN_5; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25
|
|
previous_s1_pred_info_target_2 <=
|
|
(_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit
|
|
? _predictors_io_out_s1_full_pred_2_targets_0
|
|
: 39'h0)
|
|
| (~_cfiIndex_bits_WIRE_26_0 & s1_pred_info_takenMask_2_1
|
|
& _predictors_io_out_s1_full_pred_2_hit
|
|
? _predictors_io_out_s1_full_pred_2_targets_1
|
|
: 39'h0)
|
|
| ({s1_pred_info_takenMask_2_1, _cfiIndex_bits_WIRE_26_0} == 2'h0
|
|
& _predictors_io_out_s1_full_pred_2_hit
|
|
? _predictors_io_out_s1_full_pred_2_fallThroughAddr
|
|
: 39'h0) | _GEN_6; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25
|
|
previous_s1_pred_info_target_3 <=
|
|
(_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit
|
|
? _predictors_io_out_s1_full_pred_3_targets_0
|
|
: 39'h0)
|
|
| (~_cfiIndex_bits_WIRE_30_0 & s1_pred_info_takenMask_3_1
|
|
& _predictors_io_out_s1_full_pred_3_hit
|
|
? _predictors_io_out_s1_full_pred_3_targets_1
|
|
: 39'h0)
|
|
| ({s1_pred_info_takenMask_3_1, _cfiIndex_bits_WIRE_30_0} == 2'h0
|
|
& _predictors_io_out_s1_full_pred_3_hit
|
|
? _predictors_io_out_s1_full_pred_3_fallThroughAddr
|
|
: 39'h0) | _GEN_7; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25
|
|
previous_s1_pred_info_lastBrPosOH_0_0 <=
|
|
~_predictors_io_out_s1_full_pred_0_hit
|
|
| ~(_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
| _s1_ghv_wdatas_WIRE_44494_1); // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :484:{14,19,22,41}
|
|
previous_s1_pred_info_lastBrPosOH_0_1 <=
|
|
_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_GEN_99 | ~_s1_ghv_wdatas_WIRE_44494_1)
|
|
& _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :488:{34,37,97}
|
|
previous_s1_pred_info_lastBrPosOH_0_2 <=
|
|
_s1_ghv_wdatas_WIRE_44494_1 & ~_GEN_99 & _predictors_io_out_s1_full_pred_0_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :487:9, :488:97
|
|
previous_s1_pred_info_lastBrPosOH_1_0 <=
|
|
~_predictors_io_out_s1_full_pred_1_hit | ~_GEN_8; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:{14,19,22,41}
|
|
previous_s1_pred_info_lastBrPosOH_1_1 <=
|
|
_predictors_io_out_s1_full_pred_1_slot_valids_0 & _GEN_10
|
|
& _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:488:{34,97}
|
|
previous_s1_pred_info_lastBrPosOH_1_2 <=
|
|
_s1_predicted_fh_dup_WIRE_21_1 & ~_GEN_9
|
|
& _predictors_io_out_s1_full_pred_1_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :487:9, :488:97
|
|
previous_s1_pred_info_lastBrPosOH_2_0 <=
|
|
~_predictors_io_out_s1_full_pred_2_hit | ~_GEN_11; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:{14,19,22,41}
|
|
previous_s1_pred_info_lastBrPosOH_2_1 <=
|
|
_predictors_io_out_s1_full_pred_2_slot_valids_0 & _GEN_13
|
|
& _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:488:{34,97}
|
|
previous_s1_pred_info_lastBrPosOH_2_2 <=
|
|
_s1_predicted_fh_dup_WIRE_35_1 & ~_GEN_12
|
|
& _predictors_io_out_s1_full_pred_2_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :487:9, :488:97
|
|
previous_s1_pred_info_lastBrPosOH_3_0 <=
|
|
~_predictors_io_out_s1_full_pred_3_hit | ~_GEN_14; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:{14,19,22,41}
|
|
previous_s1_pred_info_lastBrPosOH_3_1 <=
|
|
_predictors_io_out_s1_full_pred_3_slot_valids_0 & _GEN_16
|
|
& _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:488:{34,97}
|
|
previous_s1_pred_info_lastBrPosOH_3_2 <=
|
|
_s1_predicted_fh_dup_WIRE_49_1 & ~_GEN_15
|
|
& _predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :487:9, :488:97
|
|
previous_s1_pred_info_taken_0 <=
|
|
|{_predictors_io_out_s1_full_pred_0_slot_valids_1
|
|
& (_cfiIndex_bits_T_94 | ~_predictors_io_out_s1_full_pred_0_is_br_sharing)
|
|
& _predictors_io_out_s1_full_pred_0_hit,
|
|
_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :519:{46,53}
|
|
previous_s1_pred_info_taken_1 <=
|
|
|{_predictors_io_out_s1_full_pred_1_slot_valids_1
|
|
& (_cfiIndex_bits_T_115 | ~_predictors_io_out_s1_full_pred_1_is_br_sharing)
|
|
& _predictors_io_out_s1_full_pred_1_hit,
|
|
_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :519:{46,53}
|
|
previous_s1_pred_info_taken_2 <=
|
|
|{_predictors_io_out_s1_full_pred_2_slot_valids_1
|
|
& (_cfiIndex_bits_T_136 | ~_predictors_io_out_s1_full_pred_2_is_br_sharing)
|
|
& _predictors_io_out_s1_full_pred_2_hit,
|
|
_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :519:{46,53}
|
|
previous_s1_pred_info_taken_3 <=
|
|
|{_predictors_io_out_s1_full_pred_3_slot_valids_1
|
|
& (_cfiIndex_bits_T_157 | ~_predictors_io_out_s1_full_pred_3_is_br_sharing)
|
|
& _predictors_io_out_s1_full_pred_3_hit,
|
|
_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :519:{46,53}
|
|
previous_s1_pred_info_takenMask_0_0 <= _cfiIndex_bits_WIRE_18_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
previous_s1_pred_info_takenMask_0_1 <= s1_pred_info_takenMask_0_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25
|
|
previous_s1_pred_info_takenMask_1_0 <= _cfiIndex_bits_WIRE_22_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
previous_s1_pred_info_takenMask_1_1 <= s1_pred_info_takenMask_1_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25
|
|
previous_s1_pred_info_takenMask_2_0 <= _cfiIndex_bits_WIRE_26_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
previous_s1_pred_info_takenMask_2_1 <= s1_pred_info_takenMask_2_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25
|
|
previous_s1_pred_info_takenMask_3_0 <= _cfiIndex_bits_WIRE_30_0; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
previous_s1_pred_info_takenMask_3_1 <= s1_pred_info_takenMask_3_1; // src/main/scala/xiangshan/frontend/BPU.scala:600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:459:25
|
|
previous_s1_pred_info_cfiIndex_0 <=
|
|
(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
? _predictors_io_out_s1_full_pred_0_offsets_0
|
|
: _predictors_io_out_s1_full_pred_0_offsets_1)
|
|
| {4{{_predictors_io_out_s1_full_pred_0_slot_valids_1
|
|
& (_cfiIndex_bits_T_94
|
|
| ~_predictors_io_out_s1_full_pred_0_is_br_sharing)
|
|
& _predictors_io_out_s1_full_pred_0_hit,
|
|
_cfiIndex_bits_WIRE_18_0
|
|
& _predictors_io_out_s1_full_pred_0_hit} == 2'h0}}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77
|
|
previous_s1_pred_info_cfiIndex_1 <=
|
|
(_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit
|
|
? _predictors_io_out_s1_full_pred_1_offsets_0
|
|
: _predictors_io_out_s1_full_pred_1_offsets_1)
|
|
| {4{{_predictors_io_out_s1_full_pred_1_slot_valids_1
|
|
& (_cfiIndex_bits_T_115
|
|
| ~_predictors_io_out_s1_full_pred_1_is_br_sharing)
|
|
& _predictors_io_out_s1_full_pred_1_hit,
|
|
_cfiIndex_bits_WIRE_22_0
|
|
& _predictors_io_out_s1_full_pred_1_hit} == 2'h0}}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77
|
|
previous_s1_pred_info_cfiIndex_2 <=
|
|
(_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit
|
|
? _predictors_io_out_s1_full_pred_2_offsets_0
|
|
: _predictors_io_out_s1_full_pred_2_offsets_1)
|
|
| {4{{_predictors_io_out_s1_full_pred_2_slot_valids_1
|
|
& (_cfiIndex_bits_T_136
|
|
| ~_predictors_io_out_s1_full_pred_2_is_br_sharing)
|
|
& _predictors_io_out_s1_full_pred_2_hit,
|
|
_cfiIndex_bits_WIRE_26_0
|
|
& _predictors_io_out_s1_full_pred_2_hit} == 2'h0}}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77
|
|
previous_s1_pred_info_cfiIndex_3 <=
|
|
(_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit
|
|
? _predictors_io_out_s1_full_pred_3_offsets_0
|
|
: _predictors_io_out_s1_full_pred_3_offsets_1)
|
|
| {4{{_predictors_io_out_s1_full_pred_3_slot_valids_1
|
|
& (_cfiIndex_bits_T_157
|
|
| ~_predictors_io_out_s1_full_pred_3_is_br_sharing)
|
|
& _predictors_io_out_s1_full_pred_3_hit,
|
|
_cfiIndex_bits_WIRE_30_0
|
|
& _predictors_io_out_s1_full_pred_3_hit} == 2'h0}}; // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, :600:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :522:60, :523:{11,61,68}, utility/src/main/scala/utility/ParallelMux.scala:90:77
|
|
end
|
|
end
|
|
end // always @(posedge, posedge)
|
|
wire [38:0] _GEN_101 = {3'h0, _reset_vector_delay_io_out}; // src/main/scala/xiangshan/frontend/BPU.scala:276:49, :277:58, :278:43, :292:76, utility/src/main/scala/utility/Hold.scala:97:23
|
|
always @(posedge clock) begin
|
|
s0_pc_reg_dup_0 <= REG_1 ? _GEN_101 : _s0_pc_dup_0_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:276:49, :277:{16,58}, :278:43, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_pc_reg_dup_1 <= REG_1 ? _GEN_101 : _s0_pc_dup_1_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:276:49, :277:{16,58}, :278:43, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_pc_reg_dup_2 <= REG_1 ? _GEN_101 : _s0_pc_dup_2_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:276:49, :277:{16,58}, :278:43, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
s0_pc_reg_dup_3 <= REG_1 ? _GEN_101 : _s0_pc_dup_3_ppm_out_res; // src/main/scala/xiangshan/frontend/BPU.scala:276:49, :277:{16,58}, :278:43, utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
REG <= reset; // src/main/scala/xiangshan/frontend/BPU.scala:277:24
|
|
REG_1 <= REG & ~reset; // src/main/scala/xiangshan/frontend/BPU.scala:277:{16,24,39,42}
|
|
if (s1_fire_dup_0) begin // src/main/scala/xiangshan/frontend/BPU.scala:374:60
|
|
s2_ftq_idx_flag <= io_ftq_to_bpu_enq_ptr_flag; // src/main/scala/xiangshan/frontend/BPU.scala:708:29
|
|
s2_ftq_idx_value <= io_ftq_to_bpu_enq_ptr_value; // src/main/scala/xiangshan/frontend/BPU.scala:708:29
|
|
end
|
|
if (s2_valid_dup_3) begin // src/main/scala/xiangshan/frontend/BPU.scala:271:65
|
|
s3_ftq_idx_flag <= s2_ftq_idx_flag; // src/main/scala/xiangshan/frontend/BPU.scala:708:29, :709:29
|
|
s3_ftq_idx_value <= s2_ftq_idx_value; // src/main/scala/xiangshan/frontend/BPU.scala:708:29, :709:29
|
|
end
|
|
predictors_io_update_REG_valid <= io_ftq_to_bpu_update_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_pc <= io_ftq_to_bpu_update_bits_pc; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_17_folded_hist <=
|
|
io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_16_folded_hist <=
|
|
io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_15_folded_hist <=
|
|
io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_14_folded_hist <=
|
|
io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_13_folded_hist <=
|
|
io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_12_folded_hist <=
|
|
io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_11_folded_hist <=
|
|
io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_10_folded_hist <=
|
|
io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_9_folded_hist <=
|
|
io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_8_folded_hist <=
|
|
io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_7_folded_hist <=
|
|
io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_6_folded_hist <=
|
|
io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_5_folded_hist <=
|
|
io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_4_folded_hist <=
|
|
io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_3_folded_hist <=
|
|
io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_2_folded_hist <=
|
|
io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_1_folded_hist <=
|
|
io_ftq_to_bpu_update_bits_spec_info_folded_hist_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_valid <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_brSlots_0_offset <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_brSlots_0_lower <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_brSlots_0_tarStat <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_brSlots_0_sharing <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_brSlots_0_valid <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_tailSlot_offset <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_tailSlot_lower <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_tailSlot_tarStat <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_tailSlot_sharing <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_tailSlot_valid <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_pftAddr <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_pftAddr; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_carry <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_carry; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_isCall <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_isCall; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_isRet <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_isRet; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_isJalr <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_isJalr; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_last_may_be_rvi_call <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_always_taken_0 <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_ftb_entry_always_taken_1 <=
|
|
io_ftq_to_bpu_update_bits_ftb_entry_always_taken_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_cfi_idx_valid <=
|
|
io_ftq_to_bpu_update_bits_cfi_idx_valid; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_cfi_idx_bits <= io_ftq_to_bpu_update_bits_cfi_idx_bits; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_br_taken_mask_0 <=
|
|
io_ftq_to_bpu_update_bits_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_br_taken_mask_1 <=
|
|
io_ftq_to_bpu_update_bits_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_jmp_taken <= io_ftq_to_bpu_update_bits_jmp_taken; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_mispred_mask_0 <=
|
|
io_ftq_to_bpu_update_bits_mispred_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_mispred_mask_1 <=
|
|
io_ftq_to_bpu_update_bits_mispred_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_mispred_mask_2 <=
|
|
io_ftq_to_bpu_update_bits_mispred_mask_2; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_old_entry <= io_ftq_to_bpu_update_bits_old_entry; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_meta <= io_ftq_to_bpu_update_bits_meta; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
predictors_io_update_REG_bits_full_target <= io_ftq_to_bpu_update_bits_full_target; // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
end // always @(posedge)
|
|
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/BPU.scala:221:7
|
|
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/BPU.scala:221:7
|
|
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/BPU.scala:221:7
|
|
`endif // FIRRTL_BEFORE_INITIAL
|
|
logic [31:0] _RANDOM[0:180]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7
|
|
initial begin // src/main/scala/xiangshan/frontend/BPU.scala:221:7
|
|
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/BPU.scala:221:7
|
|
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/BPU.scala:221:7
|
|
`endif // INIT_RANDOM_PROLOG_
|
|
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/BPU.scala:221:7
|
|
for (logic [7:0] i = 8'h0; i < 8'hB5; i += 8'h1) begin
|
|
_RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/BPU.scala:221:7
|
|
end // src/main/scala/xiangshan/frontend/BPU.scala:221:7
|
|
s1_valid_dup_3 = _RANDOM[8'h3][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65
|
|
s2_valid_dup_3 = _RANDOM[8'h3][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65
|
|
s3_valid_dup_3 = _RANDOM[8'h3][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65
|
|
s0_pc_reg_dup_0 = {_RANDOM[8'h3][31:30], _RANDOM[8'h4], _RANDOM[8'h5][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65, :276:49
|
|
s0_pc_reg_dup_1 = {_RANDOM[8'h5][31:5], _RANDOM[8'h6][11:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :276:49
|
|
s0_pc_reg_dup_2 = {_RANDOM[8'h6][31:12], _RANDOM[8'h7][18:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :276:49
|
|
s0_pc_reg_dup_3 = {_RANDOM[8'h7][31:19], _RANDOM[8'h8][25:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :276:49
|
|
REG = _RANDOM[8'h8][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :276:49, :277:24
|
|
REG_1 = _RANDOM[8'h8][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :276:49, :277:16
|
|
s0_folded_gh_reg_dup_1_hist_17_folded_hist = _RANDOM[8'h11][15:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_16_folded_hist = _RANDOM[8'h11][26:16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_15_folded_hist =
|
|
{_RANDOM[8'h11][31:27], _RANDOM[8'h12][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_14_folded_hist = _RANDOM[8'h12][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_13_folded_hist = _RANDOM[8'h12][18:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_12_folded_hist = _RANDOM[8'h12][22:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_11_folded_hist = _RANDOM[8'h12][30:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_10_folded_hist =
|
|
{_RANDOM[8'h12][31], _RANDOM[8'h13][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_9_folded_hist = _RANDOM[8'h13][14:8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_8_folded_hist = _RANDOM[8'h13][22:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_7_folded_hist = _RANDOM[8'h13][29:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_6_folded_hist =
|
|
{_RANDOM[8'h13][31:30], _RANDOM[8'h14][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_5_folded_hist = _RANDOM[8'h14][13:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_4_folded_hist = _RANDOM[8'h14][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_3_folded_hist = _RANDOM[8'h14][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_2_folded_hist =
|
|
{_RANDOM[8'h14][31:30], _RANDOM[8'h15][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_1_folded_hist = _RANDOM[8'h15][16:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_0_folded_hist = _RANDOM[8'h15][24:17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_17_folded_hist =
|
|
{_RANDOM[8'h15][31:25], _RANDOM[8'h16][3:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_16_folded_hist = _RANDOM[8'h16][14:4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_15_folded_hist = _RANDOM[8'h16][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_14_folded_hist = _RANDOM[8'h16][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_13_folded_hist =
|
|
{_RANDOM[8'h16][31:30], _RANDOM[8'h17][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_12_folded_hist = _RANDOM[8'h17][10:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_11_folded_hist = _RANDOM[8'h17][18:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_10_folded_hist = _RANDOM[8'h17][27:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_9_folded_hist =
|
|
{_RANDOM[8'h17][31:28], _RANDOM[8'h18][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_8_folded_hist = _RANDOM[8'h18][10:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_7_folded_hist = _RANDOM[8'h18][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_6_folded_hist = _RANDOM[8'h18][26:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_5_folded_hist =
|
|
{_RANDOM[8'h18][31:27], _RANDOM[8'h19][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_4_folded_hist = _RANDOM[8'h19][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_3_folded_hist = _RANDOM[8'h19][17:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_2_folded_hist = _RANDOM[8'h19][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_1_folded_hist =
|
|
{_RANDOM[8'h19][31:26], _RANDOM[8'h1A][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_0_folded_hist = _RANDOM[8'h1A][12:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_17_folded_hist = _RANDOM[8'h1A][23:13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_16_folded_hist =
|
|
{_RANDOM[8'h1A][31:24], _RANDOM[8'h1B][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_15_folded_hist = _RANDOM[8'h1B][9:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_14_folded_hist = _RANDOM[8'h1B][17:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_13_folded_hist = _RANDOM[8'h1B][26:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_12_folded_hist = _RANDOM[8'h1B][30:27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_11_folded_hist =
|
|
{_RANDOM[8'h1B][31], _RANDOM[8'h1C][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_10_folded_hist = _RANDOM[8'h1C][15:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_9_folded_hist = _RANDOM[8'h1C][22:16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_8_folded_hist = _RANDOM[8'h1C][30:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_7_folded_hist =
|
|
{_RANDOM[8'h1C][31], _RANDOM[8'h1D][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_6_folded_hist = _RANDOM[8'h1D][14:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_5_folded_hist = _RANDOM[8'h1D][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_4_folded_hist = _RANDOM[8'h1D][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_3_folded_hist =
|
|
{_RANDOM[8'h1D][31:30], _RANDOM[8'h1E][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_2_folded_hist = _RANDOM[8'h1E][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_1_folded_hist = _RANDOM[8'h1E][24:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_0_folded_hist =
|
|
{_RANDOM[8'h1E][31:25], _RANDOM[8'h1F][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s1_folded_gh_dup_1_hist_17_folded_hist = _RANDOM[8'h23][31:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_16_folded_hist = _RANDOM[8'h24][10:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_15_folded_hist = _RANDOM[8'h24][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_14_folded_hist = _RANDOM[8'h24][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_13_folded_hist =
|
|
{_RANDOM[8'h24][31:26], _RANDOM[8'h25][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_12_folded_hist = _RANDOM[8'h25][6:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_11_folded_hist = _RANDOM[8'h25][14:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_10_folded_hist = _RANDOM[8'h25][23:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_9_folded_hist = _RANDOM[8'h25][30:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_8_folded_hist = {_RANDOM[8'h25][31], _RANDOM[8'h26][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_7_folded_hist = _RANDOM[8'h26][13:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_6_folded_hist = _RANDOM[8'h26][22:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_5_folded_hist = _RANDOM[8'h26][29:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_4_folded_hist =
|
|
{_RANDOM[8'h26][31:30], _RANDOM[8'h27][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_3_folded_hist = _RANDOM[8'h27][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_2_folded_hist = _RANDOM[8'h27][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_1_folded_hist =
|
|
{_RANDOM[8'h27][31:22], _RANDOM[8'h28][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_0_folded_hist = _RANDOM[8'h28][8:1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_17_folded_hist = _RANDOM[8'h28][19:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_16_folded_hist = _RANDOM[8'h28][30:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_15_folded_hist =
|
|
{_RANDOM[8'h28][31], _RANDOM[8'h29][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_14_folded_hist = _RANDOM[8'h29][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_13_folded_hist = _RANDOM[8'h29][22:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_12_folded_hist = _RANDOM[8'h29][26:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_11_folded_hist =
|
|
{_RANDOM[8'h29][31:27], _RANDOM[8'h2A][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_10_folded_hist = _RANDOM[8'h2A][11:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_9_folded_hist = _RANDOM[8'h2A][18:12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_8_folded_hist = _RANDOM[8'h2A][26:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_7_folded_hist =
|
|
{_RANDOM[8'h2A][31:27], _RANDOM[8'h2B][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_6_folded_hist = _RANDOM[8'h2B][10:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_5_folded_hist = _RANDOM[8'h2B][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_4_folded_hist = _RANDOM[8'h2B][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_3_folded_hist =
|
|
{_RANDOM[8'h2B][31:26], _RANDOM[8'h2C][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_2_folded_hist = _RANDOM[8'h2C][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_1_folded_hist = _RANDOM[8'h2C][20:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_0_folded_hist = _RANDOM[8'h2C][28:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_17_folded_hist =
|
|
{_RANDOM[8'h2C][31:29], _RANDOM[8'h2D][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_16_folded_hist = _RANDOM[8'h2D][18:8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_15_folded_hist = _RANDOM[8'h2D][25:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_14_folded_hist =
|
|
{_RANDOM[8'h2D][31:26], _RANDOM[8'h2E][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_13_folded_hist = _RANDOM[8'h2E][10:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_12_folded_hist = _RANDOM[8'h2E][14:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_11_folded_hist = _RANDOM[8'h2E][22:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_10_folded_hist = _RANDOM[8'h2E][31:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_9_folded_hist = _RANDOM[8'h2F][6:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_8_folded_hist = _RANDOM[8'h2F][14:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_7_folded_hist = _RANDOM[8'h2F][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_6_folded_hist = _RANDOM[8'h2F][30:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_5_folded_hist = {_RANDOM[8'h2F][31], _RANDOM[8'h30][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_4_folded_hist = _RANDOM[8'h30][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_3_folded_hist = _RANDOM[8'h30][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_2_folded_hist = _RANDOM[8'h30][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_1_folded_hist =
|
|
{_RANDOM[8'h30][31:30], _RANDOM[8'h31][8:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_3_hist_0_folded_hist = _RANDOM[8'h31][16:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s2_folded_gh_dup_1_hist_17_folded_hist = _RANDOM[8'h36][15:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_16_folded_hist = _RANDOM[8'h36][26:16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_15_folded_hist =
|
|
{_RANDOM[8'h36][31:27], _RANDOM[8'h37][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_14_folded_hist = _RANDOM[8'h37][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_13_folded_hist = _RANDOM[8'h37][18:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_12_folded_hist = _RANDOM[8'h37][22:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_11_folded_hist = _RANDOM[8'h37][30:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_10_folded_hist =
|
|
{_RANDOM[8'h37][31], _RANDOM[8'h38][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_9_folded_hist = _RANDOM[8'h38][14:8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_8_folded_hist = _RANDOM[8'h38][22:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_7_folded_hist = _RANDOM[8'h38][29:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_6_folded_hist =
|
|
{_RANDOM[8'h38][31:30], _RANDOM[8'h39][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_5_folded_hist = _RANDOM[8'h39][13:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_4_folded_hist = _RANDOM[8'h39][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_3_folded_hist = _RANDOM[8'h39][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_2_folded_hist =
|
|
{_RANDOM[8'h39][31:30], _RANDOM[8'h3A][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_1_folded_hist = _RANDOM[8'h3A][16:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_0_folded_hist = _RANDOM[8'h3A][24:17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_17_folded_hist =
|
|
{_RANDOM[8'h3A][31:25], _RANDOM[8'h3B][3:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_16_folded_hist = _RANDOM[8'h3B][14:4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_15_folded_hist = _RANDOM[8'h3B][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_14_folded_hist = _RANDOM[8'h3B][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_13_folded_hist =
|
|
{_RANDOM[8'h3B][31:30], _RANDOM[8'h3C][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_12_folded_hist = _RANDOM[8'h3C][10:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_11_folded_hist = _RANDOM[8'h3C][18:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_10_folded_hist = _RANDOM[8'h3C][27:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_9_folded_hist =
|
|
{_RANDOM[8'h3C][31:28], _RANDOM[8'h3D][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_8_folded_hist = _RANDOM[8'h3D][10:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_7_folded_hist = _RANDOM[8'h3D][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_6_folded_hist = _RANDOM[8'h3D][26:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_5_folded_hist =
|
|
{_RANDOM[8'h3D][31:27], _RANDOM[8'h3E][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_4_folded_hist = _RANDOM[8'h3E][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_3_folded_hist = _RANDOM[8'h3E][17:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_2_folded_hist = _RANDOM[8'h3E][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_1_folded_hist =
|
|
{_RANDOM[8'h3E][31:26], _RANDOM[8'h3F][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_0_folded_hist = _RANDOM[8'h3F][12:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_17_folded_hist = _RANDOM[8'h3F][23:13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_16_folded_hist =
|
|
{_RANDOM[8'h3F][31:24], _RANDOM[8'h40][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_15_folded_hist = _RANDOM[8'h40][9:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_14_folded_hist = _RANDOM[8'h40][17:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_13_folded_hist = _RANDOM[8'h40][26:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_12_folded_hist = _RANDOM[8'h40][30:27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_11_folded_hist =
|
|
{_RANDOM[8'h40][31], _RANDOM[8'h41][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_10_folded_hist = _RANDOM[8'h41][15:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_9_folded_hist = _RANDOM[8'h41][22:16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_8_folded_hist = _RANDOM[8'h41][30:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_7_folded_hist = {_RANDOM[8'h41][31], _RANDOM[8'h42][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_6_folded_hist = _RANDOM[8'h42][14:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_5_folded_hist = _RANDOM[8'h42][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_4_folded_hist = _RANDOM[8'h42][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_3_folded_hist =
|
|
{_RANDOM[8'h42][31:30], _RANDOM[8'h43][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_2_folded_hist = _RANDOM[8'h43][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_1_folded_hist = _RANDOM[8'h43][24:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_0_folded_hist =
|
|
{_RANDOM[8'h43][31:25], _RANDOM[8'h44][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s3_folded_gh_dup_1_hist_17_folded_hist = _RANDOM[8'h48][31:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_16_folded_hist = _RANDOM[8'h49][10:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_15_folded_hist = _RANDOM[8'h49][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_14_folded_hist = _RANDOM[8'h49][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_13_folded_hist =
|
|
{_RANDOM[8'h49][31:26], _RANDOM[8'h4A][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_12_folded_hist = _RANDOM[8'h4A][6:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_11_folded_hist = _RANDOM[8'h4A][14:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_10_folded_hist = _RANDOM[8'h4A][23:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_9_folded_hist = _RANDOM[8'h4A][30:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_8_folded_hist = {_RANDOM[8'h4A][31], _RANDOM[8'h4B][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_7_folded_hist = _RANDOM[8'h4B][13:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_6_folded_hist = _RANDOM[8'h4B][22:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_5_folded_hist = _RANDOM[8'h4B][29:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_4_folded_hist =
|
|
{_RANDOM[8'h4B][31:30], _RANDOM[8'h4C][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_3_folded_hist = _RANDOM[8'h4C][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_2_folded_hist = _RANDOM[8'h4C][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_1_folded_hist =
|
|
{_RANDOM[8'h4C][31:22], _RANDOM[8'h4D][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_0_folded_hist = _RANDOM[8'h4D][8:1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_17_folded_hist = _RANDOM[8'h4D][19:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_16_folded_hist = _RANDOM[8'h4D][30:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_15_folded_hist =
|
|
{_RANDOM[8'h4D][31], _RANDOM[8'h4E][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_14_folded_hist = _RANDOM[8'h4E][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_13_folded_hist = _RANDOM[8'h4E][22:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_12_folded_hist = _RANDOM[8'h4E][26:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_11_folded_hist =
|
|
{_RANDOM[8'h4E][31:27], _RANDOM[8'h4F][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_10_folded_hist = _RANDOM[8'h4F][11:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_9_folded_hist = _RANDOM[8'h4F][18:12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_8_folded_hist = _RANDOM[8'h4F][26:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_7_folded_hist =
|
|
{_RANDOM[8'h4F][31:27], _RANDOM[8'h50][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_6_folded_hist = _RANDOM[8'h50][10:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_5_folded_hist = _RANDOM[8'h50][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_4_folded_hist = _RANDOM[8'h50][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_3_folded_hist =
|
|
{_RANDOM[8'h50][31:26], _RANDOM[8'h51][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_2_folded_hist = _RANDOM[8'h51][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_1_folded_hist = _RANDOM[8'h51][20:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_0_folded_hist = _RANDOM[8'h51][28:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_17_folded_hist =
|
|
{_RANDOM[8'h51][31:29], _RANDOM[8'h52][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_16_folded_hist = _RANDOM[8'h52][18:8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_15_folded_hist = _RANDOM[8'h52][25:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_14_folded_hist =
|
|
{_RANDOM[8'h52][31:26], _RANDOM[8'h53][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_13_folded_hist = _RANDOM[8'h53][10:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_12_folded_hist = _RANDOM[8'h53][14:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_11_folded_hist = _RANDOM[8'h53][22:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_10_folded_hist = _RANDOM[8'h53][31:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_9_folded_hist = _RANDOM[8'h54][6:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_8_folded_hist = _RANDOM[8'h54][14:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_7_folded_hist = _RANDOM[8'h54][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_6_folded_hist = _RANDOM[8'h54][30:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_5_folded_hist = {_RANDOM[8'h54][31], _RANDOM[8'h55][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_4_folded_hist = _RANDOM[8'h55][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_3_folded_hist = _RANDOM[8'h55][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_2_folded_hist = _RANDOM[8'h55][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_1_folded_hist =
|
|
{_RANDOM[8'h55][31:30], _RANDOM[8'h56][8:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_0_folded_hist = _RANDOM[8'h56][16:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s0_last_br_num_oh_reg_dup_1 = _RANDOM[8'h56][22:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35, :291:73
|
|
s0_last_br_num_oh_reg_dup_2 = _RANDOM[8'h56][25:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35, :291:73
|
|
s0_last_br_num_oh_reg_dup_3 = _RANDOM[8'h56][28:26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35, :291:73
|
|
s1_last_br_num_oh_dup_1 = _RANDOM[8'h57][2:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40
|
|
s1_last_br_num_oh_dup_2 = _RANDOM[8'h57][5:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40
|
|
s1_last_br_num_oh_dup_3 = _RANDOM[8'h57][8:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40
|
|
s2_last_br_num_oh_dup_1 = _RANDOM[8'h57][14:12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :293:40
|
|
s2_last_br_num_oh_dup_2 = _RANDOM[8'h57][17:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :293:40
|
|
s2_last_br_num_oh_dup_3 = _RANDOM[8'h57][20:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :293:40
|
|
s3_last_br_num_oh_dup_1 = _RANDOM[8'h57][26:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :294:40
|
|
s3_last_br_num_oh_dup_2 = _RANDOM[8'h57][29:27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :294:40
|
|
s3_last_br_num_oh_dup_3 = {_RANDOM[8'h57][31:30], _RANDOM[8'h58][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :292:40, :294:40
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 = _RANDOM[8'h58][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85
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|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 = _RANDOM[8'h58][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85
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|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 = _RANDOM[8'h58][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85
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|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 = _RANDOM[8'h58][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85
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|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 = _RANDOM[8'h58][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85
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|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 = _RANDOM[8'h58][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85
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|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 = _RANDOM[8'h58][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40, :297:85
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|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 = _RANDOM[8'h59][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
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|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 = _RANDOM[8'h59][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
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|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 = _RANDOM[8'h59][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
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s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 = _RANDOM[8'h59][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
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s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 = _RANDOM[8'h59][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
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|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 = _RANDOM[8'h59][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 = _RANDOM[8'h59][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
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|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 = _RANDOM[8'h59][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
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|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 = _RANDOM[8'h59][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
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|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 = _RANDOM[8'h59][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
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|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 = _RANDOM[8'h59][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 = _RANDOM[8'h59][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 = _RANDOM[8'h59][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 = _RANDOM[8'h59][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 = _RANDOM[8'h59][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 = _RANDOM[8'h59][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 = _RANDOM[8'h59][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
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|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 = _RANDOM[8'h59][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 = _RANDOM[8'h59][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 = _RANDOM[8'h59][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
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|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 = _RANDOM[8'h59][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 = _RANDOM[8'h59][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 = _RANDOM[8'h59][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 = _RANDOM[8'h59][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 = _RANDOM[8'h59][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 = _RANDOM[8'h59][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 = _RANDOM[8'h59][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 = _RANDOM[8'h59][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 = _RANDOM[8'h59][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 = _RANDOM[8'h59][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 = _RANDOM[8'h59][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 = _RANDOM[8'h59][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 = _RANDOM[8'h5A][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 = _RANDOM[8'h5A][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 = _RANDOM[8'h5A][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 = _RANDOM[8'h5A][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 = _RANDOM[8'h5A][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 = _RANDOM[8'h5A][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 = _RANDOM[8'h5A][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 = _RANDOM[8'h5A][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 = _RANDOM[8'h5A][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 = _RANDOM[8'h5A][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 = _RANDOM[8'h5A][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 = _RANDOM[8'h5A][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 = _RANDOM[8'h5A][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 = _RANDOM[8'h5A][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 = _RANDOM[8'h5A][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 = _RANDOM[8'h5A][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 = _RANDOM[8'h5A][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 = _RANDOM[8'h5A][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 = _RANDOM[8'h5A][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 = _RANDOM[8'h5A][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 = _RANDOM[8'h5A][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 = _RANDOM[8'h5A][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 = _RANDOM[8'h5A][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 = _RANDOM[8'h5A][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 = _RANDOM[8'h5A][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 = _RANDOM[8'h5A][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 = _RANDOM[8'h5A][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 = _RANDOM[8'h5A][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 = _RANDOM[8'h5A][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 = _RANDOM[8'h5A][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 = _RANDOM[8'h5A][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 = _RANDOM[8'h5A][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 = _RANDOM[8'h5B][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = _RANDOM[8'h5B][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = _RANDOM[8'h5B][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = _RANDOM[8'h5B][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = _RANDOM[8'h5B][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = _RANDOM[8'h5B][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = _RANDOM[8'h5B][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = _RANDOM[8'h5B][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :297:85, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = _RANDOM[8'h5C][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = _RANDOM[8'h5C][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = _RANDOM[8'h5C][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = _RANDOM[8'h5C][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = _RANDOM[8'h5C][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = _RANDOM[8'h5C][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = _RANDOM[8'h5C][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = _RANDOM[8'h5C][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = _RANDOM[8'h5C][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = _RANDOM[8'h5C][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = _RANDOM[8'h5C][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = _RANDOM[8'h5C][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = _RANDOM[8'h5C][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = _RANDOM[8'h5C][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = _RANDOM[8'h5C][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = _RANDOM[8'h5C][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = _RANDOM[8'h5C][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = _RANDOM[8'h5C][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = _RANDOM[8'h5C][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = _RANDOM[8'h5C][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = _RANDOM[8'h5C][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = _RANDOM[8'h5C][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = _RANDOM[8'h5C][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = _RANDOM[8'h5C][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = _RANDOM[8'h5C][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = _RANDOM[8'h5C][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = _RANDOM[8'h5C][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = _RANDOM[8'h5C][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = _RANDOM[8'h5C][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = _RANDOM[8'h5C][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = _RANDOM[8'h5C][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = _RANDOM[8'h5D][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = _RANDOM[8'h5D][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = _RANDOM[8'h5D][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = _RANDOM[8'h5D][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = _RANDOM[8'h5D][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = _RANDOM[8'h5D][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = _RANDOM[8'h5D][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = _RANDOM[8'h5D][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = _RANDOM[8'h5D][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = _RANDOM[8'h5D][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = _RANDOM[8'h5D][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = _RANDOM[8'h5D][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = _RANDOM[8'h5D][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = _RANDOM[8'h5D][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = _RANDOM[8'h5D][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = _RANDOM[8'h5D][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = _RANDOM[8'h5D][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = _RANDOM[8'h5D][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = _RANDOM[8'h5D][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = _RANDOM[8'h5D][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = _RANDOM[8'h5D][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = _RANDOM[8'h5D][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = _RANDOM[8'h5D][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = _RANDOM[8'h5D][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = _RANDOM[8'h5D][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = _RANDOM[8'h5D][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = _RANDOM[8'h5D][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = _RANDOM[8'h5D][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = _RANDOM[8'h5D][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = _RANDOM[8'h5D][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = _RANDOM[8'h5D][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = _RANDOM[8'h5E][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = _RANDOM[8'h5E][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = _RANDOM[8'h5E][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = _RANDOM[8'h5E][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = _RANDOM[8'h5E][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = _RANDOM[8'h5E][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = _RANDOM[8'h5E][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = _RANDOM[8'h5E][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :298:46, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = _RANDOM[8'h5F][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = _RANDOM[8'h5F][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = _RANDOM[8'h5F][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = _RANDOM[8'h5F][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = _RANDOM[8'h5F][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = _RANDOM[8'h5F][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = _RANDOM[8'h5F][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = _RANDOM[8'h5F][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = _RANDOM[8'h5F][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = _RANDOM[8'h5F][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = _RANDOM[8'h5F][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = _RANDOM[8'h5F][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = _RANDOM[8'h5F][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = _RANDOM[8'h5F][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = _RANDOM[8'h5F][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = _RANDOM[8'h5F][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = _RANDOM[8'h5F][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = _RANDOM[8'h5F][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = _RANDOM[8'h5F][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = _RANDOM[8'h5F][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = _RANDOM[8'h5F][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = _RANDOM[8'h5F][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = _RANDOM[8'h5F][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = _RANDOM[8'h5F][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = _RANDOM[8'h5F][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = _RANDOM[8'h5F][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = _RANDOM[8'h5F][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = _RANDOM[8'h5F][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = _RANDOM[8'h5F][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = _RANDOM[8'h5F][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = _RANDOM[8'h5F][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = _RANDOM[8'h60][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = _RANDOM[8'h60][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = _RANDOM[8'h60][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = _RANDOM[8'h60][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = _RANDOM[8'h60][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = _RANDOM[8'h60][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = _RANDOM[8'h60][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = _RANDOM[8'h60][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = _RANDOM[8'h60][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = _RANDOM[8'h60][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = _RANDOM[8'h60][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = _RANDOM[8'h60][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = _RANDOM[8'h60][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = _RANDOM[8'h60][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = _RANDOM[8'h60][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = _RANDOM[8'h60][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = _RANDOM[8'h60][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = _RANDOM[8'h60][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = _RANDOM[8'h60][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = _RANDOM[8'h60][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = _RANDOM[8'h60][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = _RANDOM[8'h60][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = _RANDOM[8'h60][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = _RANDOM[8'h60][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = _RANDOM[8'h60][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = _RANDOM[8'h60][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = _RANDOM[8'h60][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = _RANDOM[8'h60][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = _RANDOM[8'h60][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = _RANDOM[8'h60][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = _RANDOM[8'h60][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = _RANDOM[8'h61][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = _RANDOM[8'h61][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = _RANDOM[8'h61][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = _RANDOM[8'h61][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = _RANDOM[8'h61][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = _RANDOM[8'h61][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = _RANDOM[8'h61][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = _RANDOM[8'h61][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :299:46, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = _RANDOM[8'h62][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = _RANDOM[8'h62][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = _RANDOM[8'h62][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = _RANDOM[8'h62][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = _RANDOM[8'h62][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = _RANDOM[8'h62][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = _RANDOM[8'h62][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = _RANDOM[8'h62][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = _RANDOM[8'h62][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = _RANDOM[8'h62][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = _RANDOM[8'h62][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = _RANDOM[8'h62][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = _RANDOM[8'h62][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = _RANDOM[8'h62][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = _RANDOM[8'h62][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = _RANDOM[8'h62][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = _RANDOM[8'h62][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = _RANDOM[8'h62][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = _RANDOM[8'h62][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = _RANDOM[8'h62][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = _RANDOM[8'h62][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = _RANDOM[8'h62][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = _RANDOM[8'h62][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = _RANDOM[8'h62][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = _RANDOM[8'h62][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = _RANDOM[8'h62][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = _RANDOM[8'h62][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = _RANDOM[8'h62][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = _RANDOM[8'h62][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = _RANDOM[8'h62][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = _RANDOM[8'h62][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = _RANDOM[8'h63][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = _RANDOM[8'h63][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = _RANDOM[8'h63][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = _RANDOM[8'h63][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = _RANDOM[8'h63][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = _RANDOM[8'h63][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = _RANDOM[8'h63][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = _RANDOM[8'h63][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = _RANDOM[8'h63][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = _RANDOM[8'h63][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = _RANDOM[8'h63][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = _RANDOM[8'h63][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = _RANDOM[8'h63][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = _RANDOM[8'h63][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = _RANDOM[8'h63][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = _RANDOM[8'h63][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = _RANDOM[8'h63][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = _RANDOM[8'h63][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = _RANDOM[8'h63][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = _RANDOM[8'h63][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = _RANDOM[8'h63][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = _RANDOM[8'h63][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = _RANDOM[8'h63][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = _RANDOM[8'h63][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = _RANDOM[8'h63][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = _RANDOM[8'h63][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = _RANDOM[8'h63][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = _RANDOM[8'h63][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = _RANDOM[8'h63][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = _RANDOM[8'h63][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = _RANDOM[8'h63][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = _RANDOM[8'h64][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
ghv_0 = _RANDOM[8'h64][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_1 = _RANDOM[8'h64][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_2 = _RANDOM[8'h64][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_3 = _RANDOM[8'h64][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_4 = _RANDOM[8'h64][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_5 = _RANDOM[8'h64][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_6 = _RANDOM[8'h64][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_7 = _RANDOM[8'h64][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_8 = _RANDOM[8'h64][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_9 = _RANDOM[8'h64][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_10 = _RANDOM[8'h64][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_11 = _RANDOM[8'h64][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_12 = _RANDOM[8'h64][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_13 = _RANDOM[8'h64][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_14 = _RANDOM[8'h64][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_15 = _RANDOM[8'h64][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_16 = _RANDOM[8'h64][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_17 = _RANDOM[8'h64][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_18 = _RANDOM[8'h64][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_19 = _RANDOM[8'h64][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_20 = _RANDOM[8'h64][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_21 = _RANDOM[8'h64][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_22 = _RANDOM[8'h64][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_23 = _RANDOM[8'h64][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_24 = _RANDOM[8'h64][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_25 = _RANDOM[8'h64][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_26 = _RANDOM[8'h64][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_27 = _RANDOM[8'h64][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_28 = _RANDOM[8'h64][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_29 = _RANDOM[8'h64][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_30 = _RANDOM[8'h64][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46, :311:20
|
|
ghv_31 = _RANDOM[8'h65][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_32 = _RANDOM[8'h65][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_33 = _RANDOM[8'h65][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_34 = _RANDOM[8'h65][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_35 = _RANDOM[8'h65][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_36 = _RANDOM[8'h65][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_37 = _RANDOM[8'h65][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_38 = _RANDOM[8'h65][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_39 = _RANDOM[8'h65][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_40 = _RANDOM[8'h65][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_41 = _RANDOM[8'h65][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_42 = _RANDOM[8'h65][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_43 = _RANDOM[8'h65][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_44 = _RANDOM[8'h65][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_45 = _RANDOM[8'h65][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_46 = _RANDOM[8'h65][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_47 = _RANDOM[8'h65][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_48 = _RANDOM[8'h65][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_49 = _RANDOM[8'h65][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_50 = _RANDOM[8'h65][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_51 = _RANDOM[8'h65][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_52 = _RANDOM[8'h65][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_53 = _RANDOM[8'h65][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_54 = _RANDOM[8'h65][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_55 = _RANDOM[8'h65][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_56 = _RANDOM[8'h65][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_57 = _RANDOM[8'h65][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_58 = _RANDOM[8'h65][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_59 = _RANDOM[8'h65][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_60 = _RANDOM[8'h65][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_61 = _RANDOM[8'h65][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_62 = _RANDOM[8'h65][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_63 = _RANDOM[8'h66][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_64 = _RANDOM[8'h66][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_65 = _RANDOM[8'h66][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_66 = _RANDOM[8'h66][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_67 = _RANDOM[8'h66][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_68 = _RANDOM[8'h66][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_69 = _RANDOM[8'h66][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_70 = _RANDOM[8'h66][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_71 = _RANDOM[8'h66][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_72 = _RANDOM[8'h66][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_73 = _RANDOM[8'h66][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_74 = _RANDOM[8'h66][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_75 = _RANDOM[8'h66][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_76 = _RANDOM[8'h66][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_77 = _RANDOM[8'h66][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_78 = _RANDOM[8'h66][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_79 = _RANDOM[8'h66][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_80 = _RANDOM[8'h66][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_81 = _RANDOM[8'h66][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_82 = _RANDOM[8'h66][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_83 = _RANDOM[8'h66][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_84 = _RANDOM[8'h66][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_85 = _RANDOM[8'h66][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_86 = _RANDOM[8'h66][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_87 = _RANDOM[8'h66][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_88 = _RANDOM[8'h66][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_89 = _RANDOM[8'h66][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_90 = _RANDOM[8'h66][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_91 = _RANDOM[8'h66][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_92 = _RANDOM[8'h66][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_93 = _RANDOM[8'h66][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_94 = _RANDOM[8'h66][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_95 = _RANDOM[8'h67][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_96 = _RANDOM[8'h67][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_97 = _RANDOM[8'h67][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_98 = _RANDOM[8'h67][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_99 = _RANDOM[8'h67][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_100 = _RANDOM[8'h67][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_101 = _RANDOM[8'h67][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_102 = _RANDOM[8'h67][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_103 = _RANDOM[8'h67][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_104 = _RANDOM[8'h67][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_105 = _RANDOM[8'h67][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_106 = _RANDOM[8'h67][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_107 = _RANDOM[8'h67][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_108 = _RANDOM[8'h67][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_109 = _RANDOM[8'h67][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_110 = _RANDOM[8'h67][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_111 = _RANDOM[8'h67][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_112 = _RANDOM[8'h67][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_113 = _RANDOM[8'h67][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_114 = _RANDOM[8'h67][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_115 = _RANDOM[8'h67][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_116 = _RANDOM[8'h67][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_117 = _RANDOM[8'h67][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_118 = _RANDOM[8'h67][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_119 = _RANDOM[8'h67][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_120 = _RANDOM[8'h67][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_121 = _RANDOM[8'h67][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_122 = _RANDOM[8'h67][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_123 = _RANDOM[8'h67][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_124 = _RANDOM[8'h67][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_125 = _RANDOM[8'h67][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_126 = _RANDOM[8'h67][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_127 = _RANDOM[8'h68][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_128 = _RANDOM[8'h68][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_129 = _RANDOM[8'h68][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_130 = _RANDOM[8'h68][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_131 = _RANDOM[8'h68][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_132 = _RANDOM[8'h68][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_133 = _RANDOM[8'h68][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_134 = _RANDOM[8'h68][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_135 = _RANDOM[8'h68][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_136 = _RANDOM[8'h68][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_137 = _RANDOM[8'h68][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_138 = _RANDOM[8'h68][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_139 = _RANDOM[8'h68][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_140 = _RANDOM[8'h68][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_141 = _RANDOM[8'h68][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_142 = _RANDOM[8'h68][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_143 = _RANDOM[8'h68][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_144 = _RANDOM[8'h68][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_145 = _RANDOM[8'h68][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_146 = _RANDOM[8'h68][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_147 = _RANDOM[8'h68][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_148 = _RANDOM[8'h68][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_149 = _RANDOM[8'h68][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_150 = _RANDOM[8'h68][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_151 = _RANDOM[8'h68][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_152 = _RANDOM[8'h68][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_153 = _RANDOM[8'h68][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_154 = _RANDOM[8'h68][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_155 = _RANDOM[8'h68][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_156 = _RANDOM[8'h68][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_157 = _RANDOM[8'h68][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_158 = _RANDOM[8'h68][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_159 = _RANDOM[8'h69][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_160 = _RANDOM[8'h69][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_161 = _RANDOM[8'h69][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_162 = _RANDOM[8'h69][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_163 = _RANDOM[8'h69][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_164 = _RANDOM[8'h69][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_165 = _RANDOM[8'h69][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_166 = _RANDOM[8'h69][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_167 = _RANDOM[8'h69][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_168 = _RANDOM[8'h69][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_169 = _RANDOM[8'h69][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_170 = _RANDOM[8'h69][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_171 = _RANDOM[8'h69][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_172 = _RANDOM[8'h69][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_173 = _RANDOM[8'h69][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_174 = _RANDOM[8'h69][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_175 = _RANDOM[8'h69][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_176 = _RANDOM[8'h69][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_177 = _RANDOM[8'h69][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_178 = _RANDOM[8'h69][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_179 = _RANDOM[8'h69][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_180 = _RANDOM[8'h69][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_181 = _RANDOM[8'h69][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_182 = _RANDOM[8'h69][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_183 = _RANDOM[8'h69][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_184 = _RANDOM[8'h69][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_185 = _RANDOM[8'h69][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_186 = _RANDOM[8'h69][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_187 = _RANDOM[8'h69][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_188 = _RANDOM[8'h69][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_189 = _RANDOM[8'h69][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_190 = _RANDOM[8'h69][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_191 = _RANDOM[8'h6A][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_192 = _RANDOM[8'h6A][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_193 = _RANDOM[8'h6A][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_194 = _RANDOM[8'h6A][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_195 = _RANDOM[8'h6A][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_196 = _RANDOM[8'h6A][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_197 = _RANDOM[8'h6A][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_198 = _RANDOM[8'h6A][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_199 = _RANDOM[8'h6A][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_200 = _RANDOM[8'h6A][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_201 = _RANDOM[8'h6A][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_202 = _RANDOM[8'h6A][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_203 = _RANDOM[8'h6A][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_204 = _RANDOM[8'h6A][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_205 = _RANDOM[8'h6A][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_206 = _RANDOM[8'h6A][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_207 = _RANDOM[8'h6A][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_208 = _RANDOM[8'h6A][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_209 = _RANDOM[8'h6A][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_210 = _RANDOM[8'h6A][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_211 = _RANDOM[8'h6A][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_212 = _RANDOM[8'h6A][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_213 = _RANDOM[8'h6A][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_214 = _RANDOM[8'h6A][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_215 = _RANDOM[8'h6A][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_216 = _RANDOM[8'h6A][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_217 = _RANDOM[8'h6A][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_218 = _RANDOM[8'h6A][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_219 = _RANDOM[8'h6A][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_220 = _RANDOM[8'h6A][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_221 = _RANDOM[8'h6A][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_222 = _RANDOM[8'h6A][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_223 = _RANDOM[8'h6B][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_224 = _RANDOM[8'h6B][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_225 = _RANDOM[8'h6B][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_226 = _RANDOM[8'h6B][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_227 = _RANDOM[8'h6B][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_228 = _RANDOM[8'h6B][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_229 = _RANDOM[8'h6B][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_230 = _RANDOM[8'h6B][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_231 = _RANDOM[8'h6B][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_232 = _RANDOM[8'h6B][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_233 = _RANDOM[8'h6B][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_234 = _RANDOM[8'h6B][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_235 = _RANDOM[8'h6B][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_236 = _RANDOM[8'h6B][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_237 = _RANDOM[8'h6B][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_238 = _RANDOM[8'h6B][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_239 = _RANDOM[8'h6B][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_240 = _RANDOM[8'h6B][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_241 = _RANDOM[8'h6B][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_242 = _RANDOM[8'h6B][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_243 = _RANDOM[8'h6B][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_244 = _RANDOM[8'h6B][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_245 = _RANDOM[8'h6B][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_246 = _RANDOM[8'h6B][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_247 = _RANDOM[8'h6B][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_248 = _RANDOM[8'h6B][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_249 = _RANDOM[8'h6B][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_250 = _RANDOM[8'h6B][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_251 = _RANDOM[8'h6B][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_252 = _RANDOM[8'h6B][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_253 = _RANDOM[8'h6B][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_254 = _RANDOM[8'h6B][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
ghv_255 = _RANDOM[8'h6C][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20
|
|
s0_ghist_ptr_reg_dup_0_flag = _RANDOM[8'h6C][1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63
|
|
s0_ghist_ptr_reg_dup_0_value = _RANDOM[8'h6C][9:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63
|
|
s0_ghist_ptr_reg_dup_1_flag = _RANDOM[8'h6C][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63
|
|
s0_ghist_ptr_reg_dup_1_value = _RANDOM[8'h6C][18:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63
|
|
s0_ghist_ptr_reg_dup_2_flag = _RANDOM[8'h6C][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63
|
|
s0_ghist_ptr_reg_dup_2_value = _RANDOM[8'h6C][27:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63
|
|
s0_ghist_ptr_reg_dup_3_flag = _RANDOM[8'h6C][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63
|
|
s0_ghist_ptr_reg_dup_3_value = {_RANDOM[8'h6C][31:29], _RANDOM[8'h6D][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :311:20, :322:63
|
|
s1_ghist_ptr_dup_0_flag = _RANDOM[8'h6D][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35
|
|
s1_ghist_ptr_dup_0_value = _RANDOM[8'h6D][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35
|
|
s1_ghist_ptr_dup_1_flag = _RANDOM[8'h6D][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35
|
|
s1_ghist_ptr_dup_1_value = _RANDOM[8'h6D][22:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35
|
|
s1_ghist_ptr_dup_2_flag = _RANDOM[8'h6D][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35
|
|
s1_ghist_ptr_dup_2_value = _RANDOM[8'h6D][31:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63, :323:35
|
|
s1_ghist_ptr_dup_3_flag = _RANDOM[8'h6E][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35
|
|
s1_ghist_ptr_dup_3_value = _RANDOM[8'h6E][8:1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35
|
|
s2_ghist_ptr_dup_0_flag = _RANDOM[8'h6E][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35
|
|
s2_ghist_ptr_dup_0_value = _RANDOM[8'h6E][17:10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35
|
|
s2_ghist_ptr_dup_1_flag = _RANDOM[8'h6E][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35
|
|
s2_ghist_ptr_dup_1_value = _RANDOM[8'h6E][26:19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35
|
|
s2_ghist_ptr_dup_2_flag = _RANDOM[8'h6E][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35
|
|
s2_ghist_ptr_dup_2_value = {_RANDOM[8'h6E][31:28], _RANDOM[8'h6F][3:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, :324:35
|
|
s2_ghist_ptr_dup_3_flag = _RANDOM[8'h6F][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35
|
|
s2_ghist_ptr_dup_3_value = _RANDOM[8'h6F][12:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35
|
|
s3_ghist_ptr_dup_0_flag = _RANDOM[8'h6F][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, :325:35
|
|
s3_ghist_ptr_dup_0_value = _RANDOM[8'h6F][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, :325:35
|
|
s3_ghist_ptr_dup_1_flag = _RANDOM[8'h6F][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, :325:35
|
|
s3_ghist_ptr_dup_1_value = _RANDOM[8'h6F][30:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, :325:35
|
|
s3_ghist_ptr_dup_2_flag = _RANDOM[8'h6F][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, :325:35
|
|
s3_ghist_ptr_dup_2_value = _RANDOM[8'h70][7:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35
|
|
s3_ghist_ptr_dup_3_flag = _RANDOM[8'h70][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35
|
|
s3_ghist_ptr_dup_3_value = _RANDOM[8'h70][16:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35
|
|
do_redirect_dup_3_valid = _RANDOM[8'h70][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, :350:40
|
|
do_redirect_dup_3_bits_level = _RANDOM[8'h71][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_pc =
|
|
{_RANDOM[8'h71][31:9], _RANDOM[8'h72][15:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_pd_isRVC = _RANDOM[8'h72][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_pd_isCall = _RANDOM[8'h72][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_pd_isRet = _RANDOM[8'h72][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_ssp = _RANDOM[8'h72][25:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_sctr = _RANDOM[8'h72][27:26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_TOSW_flag = _RANDOM[8'h72][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_TOSW_value =
|
|
{_RANDOM[8'h72][31:29], _RANDOM[8'h73][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_TOSR_flag = _RANDOM[8'h73][2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_TOSR_value = _RANDOM[8'h73][7:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_NOS_flag = _RANDOM[8'h73][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_NOS_value = _RANDOM[8'h73][13:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist =
|
|
_RANDOM[8'h74][31:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist =
|
|
_RANDOM[8'h75][10:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist =
|
|
_RANDOM[8'h75][17:11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist =
|
|
_RANDOM[8'h75][25:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist =
|
|
{_RANDOM[8'h75][31:26], _RANDOM[8'h76][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist =
|
|
_RANDOM[8'h76][6:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist =
|
|
_RANDOM[8'h76][14:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist =
|
|
_RANDOM[8'h76][23:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist =
|
|
_RANDOM[8'h76][30:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist =
|
|
{_RANDOM[8'h76][31], _RANDOM[8'h77][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist =
|
|
_RANDOM[8'h77][13:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist =
|
|
_RANDOM[8'h77][22:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist =
|
|
_RANDOM[8'h77][29:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist =
|
|
{_RANDOM[8'h77][31:30], _RANDOM[8'h78][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist =
|
|
_RANDOM[8'h78][13:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist =
|
|
_RANDOM[8'h78][21:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist =
|
|
{_RANDOM[8'h78][31:22], _RANDOM[8'h79][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist =
|
|
_RANDOM[8'h79][8:1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 = _RANDOM[8'h79][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 = _RANDOM[8'h79][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 = _RANDOM[8'h79][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3 = _RANDOM[8'h79][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 = _RANDOM[8'h79][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 = _RANDOM[8'h79][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2 = _RANDOM[8'h79][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 = _RANDOM[8'h79][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 = _RANDOM[8'h79][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 = _RANDOM[8'h79][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3 = _RANDOM[8'h79][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 = _RANDOM[8'h79][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 = _RANDOM[8'h79][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
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|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 = _RANDOM[8'h79][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
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|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3 = _RANDOM[8'h79][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
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|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 = _RANDOM[8'h79][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
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|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 = _RANDOM[8'h79][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
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|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 = _RANDOM[8'h79][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3 = _RANDOM[8'h79][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 = _RANDOM[8'h79][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
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|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 = _RANDOM[8'h79][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 = _RANDOM[8'h79][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
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do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3 = _RANDOM[8'h7A][0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
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do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH = _RANDOM[8'h7A][3:1]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
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do_redirect_dup_3_bits_cfiUpdate_histPtr_flag = _RANDOM[8'h7A][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
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do_redirect_dup_3_bits_cfiUpdate_histPtr_value = _RANDOM[8'h7A][16:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
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|
do_redirect_dup_3_bits_cfiUpdate_target =
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{_RANDOM[8'h7B][31:9], _RANDOM[8'h7C][15:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
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|
do_redirect_dup_3_bits_cfiUpdate_taken = _RANDOM[8'h7C][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
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thisBrNumOH_dup_shiftAmount = _RANDOM[8'h7C][19:18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
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do_redirect_dup_3_bits_cfiUpdate_addIntoHist = _RANDOM[8'h7C][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
previous_s1_pred_info_hit_0 = _RANDOM[8'h7F][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
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|
previous_s1_pred_info_hit_1 = _RANDOM[8'h7F][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
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|
previous_s1_pred_info_hit_2 = _RANDOM[8'h7F][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
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|
previous_s1_pred_info_hit_3 = _RANDOM[8'h7F][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_target_0 = {_RANDOM[8'h7F][31:7], _RANDOM[8'h80][13:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_target_1 = {_RANDOM[8'h80][31:14], _RANDOM[8'h81][20:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_target_2 = {_RANDOM[8'h81][31:21], _RANDOM[8'h82][27:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_target_3 =
|
|
{_RANDOM[8'h82][31:28], _RANDOM[8'h83], _RANDOM[8'h84][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_0_0 = _RANDOM[8'h84][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_0_1 = _RANDOM[8'h84][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_0_2 = _RANDOM[8'h84][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_1_0 = _RANDOM[8'h84][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_1_1 = _RANDOM[8'h84][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_1_2 = _RANDOM[8'h84][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_2_0 = _RANDOM[8'h84][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_2_1 = _RANDOM[8'h84][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_2_2 = _RANDOM[8'h84][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_3_0 = _RANDOM[8'h84][12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_3_1 = _RANDOM[8'h84][13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_3_2 = _RANDOM[8'h84][14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_taken_0 = _RANDOM[8'h84][15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_taken_1 = _RANDOM[8'h84][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_taken_2 = _RANDOM[8'h84][17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_taken_3 = _RANDOM[8'h84][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_takenMask_0_0 = _RANDOM[8'h84][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_takenMask_0_1 = _RANDOM[8'h84][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_takenMask_1_0 = _RANDOM[8'h84][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_takenMask_1_1 = _RANDOM[8'h84][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_takenMask_2_0 = _RANDOM[8'h84][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_takenMask_2_1 = _RANDOM[8'h84][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_takenMask_3_0 = _RANDOM[8'h84][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_takenMask_3_1 = _RANDOM[8'h84][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_cfiIndex_0 = _RANDOM[8'h84][30:27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_cfiIndex_1 = {_RANDOM[8'h84][31], _RANDOM[8'h85][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_cfiIndex_2 = _RANDOM[8'h85][6:3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s1_pred_info_cfiIndex_3 = _RANDOM[8'h85][10:7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40
|
|
previous_s2_pred_pc_0 = {_RANDOM[8'h85][31:11], _RANDOM[8'h86][17:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :600:40, :673:35
|
|
previous_s2_pred_pc_1 = {_RANDOM[8'h86][31:18], _RANDOM[8'h87][24:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_pc_2 = {_RANDOM[8'h87][31:25], _RANDOM[8'h88]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_pc_3 = {_RANDOM[8'h89], _RANDOM[8'h8A][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_0_br_taken_mask_0 = _RANDOM[8'h8A][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_0_br_taken_mask_1 = _RANDOM[8'h8A][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_0_slot_valids_0 = _RANDOM[8'h8A][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_0_slot_valids_1 = _RANDOM[8'h8A][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_0_targets_0 =
|
|
{_RANDOM[8'h8A][31:26], _RANDOM[8'h8B], _RANDOM[8'h8C][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_0_targets_1 =
|
|
{_RANDOM[8'h8C][31:1], _RANDOM[8'h8D][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_0_fallThroughAddr =
|
|
{_RANDOM[8'h8E][31:23], _RANDOM[8'h8F][29:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_0_is_br_sharing = _RANDOM[8'h90][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_0_hit = _RANDOM[8'h90][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_1_br_taken_mask_0 = _RANDOM[8'h90][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_1_br_taken_mask_1 = _RANDOM[8'h90][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_1_slot_valids_0 = _RANDOM[8'h90][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_1_slot_valids_1 = _RANDOM[8'h90][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_1_targets_0 =
|
|
{_RANDOM[8'h90][31:10], _RANDOM[8'h91][16:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_1_targets_1 =
|
|
{_RANDOM[8'h91][31:17], _RANDOM[8'h92][23:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_1_fallThroughAddr =
|
|
{_RANDOM[8'h94][31:7], _RANDOM[8'h95][13:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_1_is_br_sharing = _RANDOM[8'h95][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_1_hit = _RANDOM[8'h95][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_2_br_taken_mask_0 = _RANDOM[8'h95][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_2_br_taken_mask_1 = _RANDOM[8'h95][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_2_slot_valids_0 = _RANDOM[8'h95][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_2_slot_valids_1 = _RANDOM[8'h95][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_2_targets_0 =
|
|
{_RANDOM[8'h95][31:26], _RANDOM[8'h96], _RANDOM[8'h97][0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_2_targets_1 =
|
|
{_RANDOM[8'h97][31:1], _RANDOM[8'h98][7:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_2_fallThroughAddr =
|
|
{_RANDOM[8'h99][31:23], _RANDOM[8'h9A][29:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_2_is_br_sharing = _RANDOM[8'h9B][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_2_hit = _RANDOM[8'h9B][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_3_br_taken_mask_0 = _RANDOM[8'h9B][6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_3_br_taken_mask_1 = _RANDOM[8'h9B][7]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_3_slot_valids_0 = _RANDOM[8'h9B][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_3_slot_valids_1 = _RANDOM[8'h9B][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_3_targets_0 =
|
|
{_RANDOM[8'h9B][31:10], _RANDOM[8'h9C][16:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_3_targets_1 =
|
|
{_RANDOM[8'h9C][31:17], _RANDOM[8'h9D][23:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_3_fallThroughAddr =
|
|
{_RANDOM[8'h9F][31:7], _RANDOM[8'hA0][13:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_3_is_br_sharing = _RANDOM[8'hA0][20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
previous_s2_pred_full_pred_3_hit = _RANDOM[8'hA0][21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35
|
|
s2_ftq_idx_flag = _RANDOM[8'hA0][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35, :708:29
|
|
s2_ftq_idx_value = _RANDOM[8'hA0][28:23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35, :708:29
|
|
s3_ftq_idx_flag = _RANDOM[8'hA0][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35, :709:29
|
|
s3_ftq_idx_value = {_RANDOM[8'hA0][31:30], _RANDOM[8'hA1][3:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :673:35, :709:29
|
|
predictors_io_update_REG_valid = _RANDOM[8'hA1][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :709:29, :727:34
|
|
predictors_io_update_REG_bits_pc = {_RANDOM[8'hA1][31:5], _RANDOM[8'hA2][11:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :709:29, :727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_17_folded_hist =
|
|
_RANDOM[8'hA2][22:12]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_16_folded_hist =
|
|
{_RANDOM[8'hA2][31:23], _RANDOM[8'hA3][1:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_15_folded_hist =
|
|
_RANDOM[8'hA3][8:2]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_14_folded_hist =
|
|
_RANDOM[8'hA3][16:9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_13_folded_hist =
|
|
_RANDOM[8'hA3][25:17]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_12_folded_hist =
|
|
_RANDOM[8'hA3][29:26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_11_folded_hist =
|
|
{_RANDOM[8'hA3][31:30], _RANDOM[8'hA4][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_10_folded_hist =
|
|
_RANDOM[8'hA4][14:6]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_9_folded_hist =
|
|
_RANDOM[8'hA4][21:15]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_8_folded_hist =
|
|
_RANDOM[8'hA4][29:22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_7_folded_hist =
|
|
{_RANDOM[8'hA4][31:30], _RANDOM[8'hA5][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_6_folded_hist =
|
|
_RANDOM[8'hA5][13:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_5_folded_hist =
|
|
_RANDOM[8'hA5][20:14]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_4_folded_hist =
|
|
_RANDOM[8'hA5][28:21]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_3_folded_hist =
|
|
{_RANDOM[8'hA5][31:29], _RANDOM[8'hA6][4:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_2_folded_hist =
|
|
_RANDOM[8'hA6][12:5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_spec_info_folded_hist_hist_1_folded_hist =
|
|
_RANDOM[8'hA6][23:13]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_valid = _RANDOM[8'hAA][3]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_brSlots_0_offset = _RANDOM[8'hAA][7:4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_brSlots_0_lower = _RANDOM[8'hAA][19:8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_brSlots_0_tarStat = _RANDOM[8'hAA][21:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_brSlots_0_sharing = _RANDOM[8'hAA][22]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_brSlots_0_valid = _RANDOM[8'hAA][23]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_tailSlot_offset = _RANDOM[8'hAA][27:24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_tailSlot_lower =
|
|
{_RANDOM[8'hAA][31:28], _RANDOM[8'hAB][15:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_tailSlot_tarStat = _RANDOM[8'hAB][17:16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_tailSlot_sharing = _RANDOM[8'hAB][18]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_tailSlot_valid = _RANDOM[8'hAB][19]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_pftAddr = _RANDOM[8'hAB][23:20]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_carry = _RANDOM[8'hAB][24]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_isCall = _RANDOM[8'hAB][25]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_isRet = _RANDOM[8'hAB][26]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_isJalr = _RANDOM[8'hAB][27]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_last_may_be_rvi_call = _RANDOM[8'hAB][28]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_always_taken_0 = _RANDOM[8'hAB][29]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_ftb_entry_always_taken_1 = _RANDOM[8'hAB][30]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_cfi_idx_valid = _RANDOM[8'hAB][31]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_cfi_idx_bits = _RANDOM[8'hAC][3:0]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_br_taken_mask_0 = _RANDOM[8'hAC][4]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_br_taken_mask_1 = _RANDOM[8'hAC][5]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_jmp_taken = _RANDOM[8'hAC][8]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_mispred_mask_0 = _RANDOM[8'hAC][9]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_mispred_mask_1 = _RANDOM[8'hAC][10]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_mispred_mask_2 = _RANDOM[8'hAC][11]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_old_entry = _RANDOM[8'hAC][16]; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_meta =
|
|
{_RANDOM[8'hAC][31:17],
|
|
_RANDOM[8'hAD],
|
|
_RANDOM[8'hAE],
|
|
_RANDOM[8'hAF],
|
|
_RANDOM[8'hB0],
|
|
_RANDOM[8'hB1],
|
|
_RANDOM[8'hB2],
|
|
_RANDOM[8'hB3][11:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
predictors_io_update_REG_bits_full_target =
|
|
{_RANDOM[8'hB3][31:12], _RANDOM[8'hB4][18:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :727:34
|
|
`endif // RANDOMIZE_REG_INIT
|
|
if (reset) begin // src/main/scala/xiangshan/frontend/BPU.scala:221:7
|
|
s1_valid_dup_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65
|
|
s2_valid_dup_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65
|
|
s3_valid_dup_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :271:65
|
|
s0_folded_gh_reg_dup_1_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_1_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_1_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_2_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_2_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s0_folded_gh_reg_dup_3_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:{63,84}
|
|
s0_folded_gh_reg_dup_3_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :285:63
|
|
s1_folded_gh_dup_1_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35
|
|
s1_folded_gh_dup_1_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_1_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_1_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_2_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_2_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_2_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_2_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35
|
|
s1_folded_gh_dup_2_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
|
s1_folded_gh_dup_2_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
|
s1_folded_gh_dup_2_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
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s1_folded_gh_dup_2_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
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s1_folded_gh_dup_2_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
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s1_folded_gh_dup_2_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
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s1_folded_gh_dup_2_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
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s1_folded_gh_dup_2_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
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s1_folded_gh_dup_2_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
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s1_folded_gh_dup_2_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
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s1_folded_gh_dup_2_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
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s1_folded_gh_dup_2_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
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s1_folded_gh_dup_3_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
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s1_folded_gh_dup_3_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
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s1_folded_gh_dup_3_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
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s1_folded_gh_dup_3_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
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s1_folded_gh_dup_3_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
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s1_folded_gh_dup_3_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35
|
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s1_folded_gh_dup_3_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
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s1_folded_gh_dup_3_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
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s1_folded_gh_dup_3_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
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s1_folded_gh_dup_3_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
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s1_folded_gh_dup_3_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
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s1_folded_gh_dup_3_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
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s1_folded_gh_dup_3_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
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s1_folded_gh_dup_3_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
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s1_folded_gh_dup_3_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
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s1_folded_gh_dup_3_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
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s1_folded_gh_dup_3_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35
|
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s1_folded_gh_dup_3_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35
|
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s2_folded_gh_dup_1_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35
|
|
s2_folded_gh_dup_1_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_1_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_1_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35
|
|
s2_folded_gh_dup_2_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_2_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_2_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :287:35
|
|
s2_folded_gh_dup_3_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s2_folded_gh_dup_3_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :287:35
|
|
s2_folded_gh_dup_3_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :287:35
|
|
s3_folded_gh_dup_1_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35
|
|
s3_folded_gh_dup_1_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_1_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_1_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35
|
|
s3_folded_gh_dup_2_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_2_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_2_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :288:35
|
|
s3_folded_gh_dup_3_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
|
|
s3_folded_gh_dup_3_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
s3_folded_gh_dup_3_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
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s3_folded_gh_dup_3_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
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s3_folded_gh_dup_3_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :288:35
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s3_folded_gh_dup_3_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
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s0_last_br_num_oh_reg_dup_1 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76
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s0_last_br_num_oh_reg_dup_2 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76
|
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s0_last_br_num_oh_reg_dup_3 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:291:73, :292:76
|
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s1_last_br_num_oh_dup_1 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76}
|
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s1_last_br_num_oh_dup_2 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76}
|
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s1_last_br_num_oh_dup_3 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:{40,76}
|
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s2_last_br_num_oh_dup_1 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40
|
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s2_last_br_num_oh_dup_2 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40
|
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s2_last_br_num_oh_dup_3 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :293:40
|
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s3_last_br_num_oh_dup_1 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40
|
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s3_last_br_num_oh_dup_2 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40
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s3_last_br_num_oh_dup_3 = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :294:40
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|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :297:85
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :298:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :299:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :300:46
|
|
ghv_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_4 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_5 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_6 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_7 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_8 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_9 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_10 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_11 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_12 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_13 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_14 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_15 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_16 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_17 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_18 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_19 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_20 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_21 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_22 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_23 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_24 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_25 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_26 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_27 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_28 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_29 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_30 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_31 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_32 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_33 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_34 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_35 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_36 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_37 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_38 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_39 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_40 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_41 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_42 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_43 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_44 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_45 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_46 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_47 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_48 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_49 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_50 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_51 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_52 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_53 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_54 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_55 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_56 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_57 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_58 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_59 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_60 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_61 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_62 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_63 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_64 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_65 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_66 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_67 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_68 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_69 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_70 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_71 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_72 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_73 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_74 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_75 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_76 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_77 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_78 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_79 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_80 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_81 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_82 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_83 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_84 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_85 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_86 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_87 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_88 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_89 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_90 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_91 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_92 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_93 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_94 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_95 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_96 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_97 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_98 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_99 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_100 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_101 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_102 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_103 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_104 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_105 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_106 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_107 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_108 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_109 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_110 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_111 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_112 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_113 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_114 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_115 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_116 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_117 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_118 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_119 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_120 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_121 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_122 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_123 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_124 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_125 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_126 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_127 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_128 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_129 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_130 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_131 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_132 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_133 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_134 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_135 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_136 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_137 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_138 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_139 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_140 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_141 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_142 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_143 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_144 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_145 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_146 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_147 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_148 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_149 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_150 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_151 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_152 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_153 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_154 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_155 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_156 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_157 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_158 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_159 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_160 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_161 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_162 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_163 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_164 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_165 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_166 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_167 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_168 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_169 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_170 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_171 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_172 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_173 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_174 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_175 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_176 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_177 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_178 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_179 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_180 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_181 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_182 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_183 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_184 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_185 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_186 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_187 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_188 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_189 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_190 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_191 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_192 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_193 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_194 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_195 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_196 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_197 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_198 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_199 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_200 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_201 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_202 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_203 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_204 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_205 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_206 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_207 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_208 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_209 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_210 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_211 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_212 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_213 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_214 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_215 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_216 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_217 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_218 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_219 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_220 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_221 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_222 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_223 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_224 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_225 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_226 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_227 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_228 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_229 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_230 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_231 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_232 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_233 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_234 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_235 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_236 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_237 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_238 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_239 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_240 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_241 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_242 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_243 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_244 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_245 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_246 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_247 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_248 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_249 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_250 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_251 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_252 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_253 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_254 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
ghv_255 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :311:20
|
|
s0_ghist_ptr_reg_dup_0_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63
|
|
s0_ghist_ptr_reg_dup_0_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63
|
|
s0_ghist_ptr_reg_dup_1_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63
|
|
s0_ghist_ptr_reg_dup_1_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63
|
|
s0_ghist_ptr_reg_dup_2_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63
|
|
s0_ghist_ptr_reg_dup_2_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63
|
|
s0_ghist_ptr_reg_dup_3_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :322:63
|
|
s0_ghist_ptr_reg_dup_3_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :322:63
|
|
s1_ghist_ptr_dup_0_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35
|
|
s1_ghist_ptr_dup_0_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35
|
|
s1_ghist_ptr_dup_1_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35
|
|
s1_ghist_ptr_dup_1_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35
|
|
s1_ghist_ptr_dup_2_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35
|
|
s1_ghist_ptr_dup_2_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35
|
|
s1_ghist_ptr_dup_3_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :323:35
|
|
s1_ghist_ptr_dup_3_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35
|
|
s2_ghist_ptr_dup_0_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35
|
|
s2_ghist_ptr_dup_0_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35
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s2_ghist_ptr_dup_1_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35
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s2_ghist_ptr_dup_1_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35
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s2_ghist_ptr_dup_2_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35
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s2_ghist_ptr_dup_2_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35
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s2_ghist_ptr_dup_3_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :324:35
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s2_ghist_ptr_dup_3_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35
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s3_ghist_ptr_dup_0_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35
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s3_ghist_ptr_dup_0_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35
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s3_ghist_ptr_dup_1_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35
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s3_ghist_ptr_dup_1_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35
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s3_ghist_ptr_dup_2_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35
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s3_ghist_ptr_dup_2_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35
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s3_ghist_ptr_dup_3_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :325:35
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s3_ghist_ptr_dup_3_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35
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do_redirect_dup_3_valid = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
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do_redirect_dup_3_bits_level = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
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do_redirect_dup_3_bits_cfiUpdate_pc = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40
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do_redirect_dup_3_bits_cfiUpdate_pd_isRVC = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
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do_redirect_dup_3_bits_cfiUpdate_pd_isCall = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
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do_redirect_dup_3_bits_cfiUpdate_pd_isRet = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
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do_redirect_dup_3_bits_cfiUpdate_ssp = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
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do_redirect_dup_3_bits_cfiUpdate_sctr = 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40
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do_redirect_dup_3_bits_cfiUpdate_TOSW_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
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do_redirect_dup_3_bits_cfiUpdate_TOSW_value = 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40
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do_redirect_dup_3_bits_cfiUpdate_TOSR_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
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do_redirect_dup_3_bits_cfiUpdate_TOSR_value = 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40
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do_redirect_dup_3_bits_cfiUpdate_NOS_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
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do_redirect_dup_3_bits_cfiUpdate_NOS_value = 5'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40
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do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_17_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
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do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_16_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_15_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_14_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_13_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_12_folded_hist = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_11_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_10_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_9_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_8_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_7_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_6_folded_hist = 9'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_5_folded_hist = 7'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_4_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_3_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_2_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_1_folded_hist = 11'h0; // src/main/scala/xiangshan/frontend/BPU.scala:285:84, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_folded_hist_hist_0_folded_hist = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_5_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_4_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_3_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_2_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_1_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_afhob_afhob_0_bits_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_lastBrNumOH = 3'h0; // src/main/scala/xiangshan/frontend/BPU.scala:292:76, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_flag = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_histPtr_value = 8'h0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_target = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_taken = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
thisBrNumOH_dup_shiftAmount = 2'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :350:40
|
|
do_redirect_dup_3_bits_cfiUpdate_addIntoHist = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :350:40
|
|
previous_s1_pred_info_hit_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_hit_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_hit_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_hit_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_target_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40
|
|
previous_s1_pred_info_target_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40
|
|
previous_s1_pred_info_target_2 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40
|
|
previous_s1_pred_info_target_3 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_0_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_0_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_0_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_1_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_1_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_1_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_2_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_2_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_2_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_3_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_3_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_lastBrPosOH_3_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_taken_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_taken_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_taken_2 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_taken_3 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_takenMask_0_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_takenMask_0_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_takenMask_1_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_takenMask_1_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_takenMask_2_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_takenMask_2_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_takenMask_3_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_takenMask_3_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_cfiIndex_0 = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_cfiIndex_1 = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_cfiIndex_2 = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s1_pred_info_cfiIndex_3 = 4'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :600:40
|
|
previous_s2_pred_pc_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_pc_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_pc_2 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_pc_3 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_0_br_taken_mask_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_0_br_taken_mask_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_0_slot_valids_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_0_slot_valids_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_0_targets_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_0_targets_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_0_fallThroughAddr = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_0_is_br_sharing = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_0_hit = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_1_br_taken_mask_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_1_br_taken_mask_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_1_slot_valids_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_1_slot_valids_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_1_targets_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_1_targets_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_1_fallThroughAddr = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_1_is_br_sharing = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_1_hit = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_2_br_taken_mask_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_2_br_taken_mask_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_2_slot_valids_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_2_slot_valids_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_2_targets_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_2_targets_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_2_fallThroughAddr = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_2_is_br_sharing = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_2_hit = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_3_br_taken_mask_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_3_br_taken_mask_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_3_slot_valids_0 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_3_slot_valids_1 = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_3_targets_0 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_3_targets_1 = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_3_fallThroughAddr = 39'h0; // src/main/scala/xiangshan/frontend/BPU.scala:343:53, :673:35
|
|
previous_s2_pred_full_pred_3_is_br_sharing = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
previous_s2_pred_full_pred_3_hit = 1'h0; // src/main/scala/xiangshan/frontend/BPU.scala:229:73, :673:35
|
|
end
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/BPU.scala:221:7
|
|
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/BPU.scala:221:7
|
|
`endif // FIRRTL_AFTER_INITIAL
|
|
`endif // ENABLE_INITIAL_REG_
|
|
DelayN_1 ctrl_delay ( // utility/src/main/scala/utility/Hold.scala:97:23
|
|
.clock (clock),
|
|
.io_in_ubtb_enable (io_ctrl_ubtb_enable),
|
|
.io_in_btb_enable (io_ctrl_btb_enable),
|
|
.io_in_tage_enable (io_ctrl_tage_enable),
|
|
.io_in_sc_enable (io_ctrl_sc_enable),
|
|
.io_in_ras_enable (io_ctrl_ras_enable),
|
|
.io_out_ubtb_enable (_ctrl_delay_io_out_ubtb_enable),
|
|
.io_out_btb_enable (_ctrl_delay_io_out_btb_enable),
|
|
.io_out_tage_enable (_ctrl_delay_io_out_tage_enable),
|
|
.io_out_sc_enable (_ctrl_delay_io_out_sc_enable),
|
|
.io_out_ras_enable (_ctrl_delay_io_out_ras_enable)
|
|
);
|
|
Composer predictors ( // src/main/scala/xiangshan/frontend/BPU.scala:225:26
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_reset_vector (io_reset_vector),
|
|
.io_in_bits_s0_pc_0 (_s0_pc_dup_0_ppm_out_res), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_s0_pc_1 (_s0_pc_dup_1_ppm_out_res), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_s0_pc_2 (_s0_pc_dup_2_ppm_out_res), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_s0_pc_3 (_s0_pc_dup_3_ppm_out_res), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_1_hist_17_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_1_hist_16_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_1_hist_15_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_1_hist_14_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_1_hist_9_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_1_hist_8_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_1_hist_7_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_1_hist_5_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_1_hist_4_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_1_hist_3_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_1_hist_1_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_3_hist_14_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_3_hist_13_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_3_hist_12_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_3_hist_11_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_3_hist_10_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_3_hist_6_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_3_hist_4_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_3_hist_3_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_in_bits_folded_hist_3_hist_2_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist), // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.io_out_s1_pc_0
|
|
(_predictors_io_out_s1_pc_0),
|
|
.io_out_s1_pc_1
|
|
(_predictors_io_out_s1_pc_1),
|
|
.io_out_s1_pc_2
|
|
(_predictors_io_out_s1_pc_2),
|
|
.io_out_s1_pc_3
|
|
(_predictors_io_out_s1_pc_3),
|
|
.io_out_s1_full_pred_0_br_taken_mask_0
|
|
(_predictors_io_out_s1_full_pred_0_br_taken_mask_0),
|
|
.io_out_s1_full_pred_0_br_taken_mask_1
|
|
(_predictors_io_out_s1_full_pred_0_br_taken_mask_1),
|
|
.io_out_s1_full_pred_0_slot_valids_0
|
|
(_predictors_io_out_s1_full_pred_0_slot_valids_0),
|
|
.io_out_s1_full_pred_0_slot_valids_1
|
|
(_predictors_io_out_s1_full_pred_0_slot_valids_1),
|
|
.io_out_s1_full_pred_0_targets_0
|
|
(_predictors_io_out_s1_full_pred_0_targets_0),
|
|
.io_out_s1_full_pred_0_targets_1
|
|
(_predictors_io_out_s1_full_pred_0_targets_1),
|
|
.io_out_s1_full_pred_0_offsets_0
|
|
(_predictors_io_out_s1_full_pred_0_offsets_0),
|
|
.io_out_s1_full_pred_0_offsets_1
|
|
(_predictors_io_out_s1_full_pred_0_offsets_1),
|
|
.io_out_s1_full_pred_0_fallThroughAddr
|
|
(_predictors_io_out_s1_full_pred_0_fallThroughAddr),
|
|
.io_out_s1_full_pred_0_is_br_sharing
|
|
(_predictors_io_out_s1_full_pred_0_is_br_sharing),
|
|
.io_out_s1_full_pred_0_hit
|
|
(_predictors_io_out_s1_full_pred_0_hit),
|
|
.io_out_s1_full_pred_1_br_taken_mask_0
|
|
(_predictors_io_out_s1_full_pred_1_br_taken_mask_0),
|
|
.io_out_s1_full_pred_1_br_taken_mask_1
|
|
(_predictors_io_out_s1_full_pred_1_br_taken_mask_1),
|
|
.io_out_s1_full_pred_1_slot_valids_0
|
|
(_predictors_io_out_s1_full_pred_1_slot_valids_0),
|
|
.io_out_s1_full_pred_1_slot_valids_1
|
|
(_predictors_io_out_s1_full_pred_1_slot_valids_1),
|
|
.io_out_s1_full_pred_1_targets_0
|
|
(_predictors_io_out_s1_full_pred_1_targets_0),
|
|
.io_out_s1_full_pred_1_targets_1
|
|
(_predictors_io_out_s1_full_pred_1_targets_1),
|
|
.io_out_s1_full_pred_1_offsets_0
|
|
(_predictors_io_out_s1_full_pred_1_offsets_0),
|
|
.io_out_s1_full_pred_1_offsets_1
|
|
(_predictors_io_out_s1_full_pred_1_offsets_1),
|
|
.io_out_s1_full_pred_1_fallThroughAddr
|
|
(_predictors_io_out_s1_full_pred_1_fallThroughAddr),
|
|
.io_out_s1_full_pred_1_is_br_sharing
|
|
(_predictors_io_out_s1_full_pred_1_is_br_sharing),
|
|
.io_out_s1_full_pred_1_hit
|
|
(_predictors_io_out_s1_full_pred_1_hit),
|
|
.io_out_s1_full_pred_2_br_taken_mask_0
|
|
(_predictors_io_out_s1_full_pred_2_br_taken_mask_0),
|
|
.io_out_s1_full_pred_2_br_taken_mask_1
|
|
(_predictors_io_out_s1_full_pred_2_br_taken_mask_1),
|
|
.io_out_s1_full_pred_2_slot_valids_0
|
|
(_predictors_io_out_s1_full_pred_2_slot_valids_0),
|
|
.io_out_s1_full_pred_2_slot_valids_1
|
|
(_predictors_io_out_s1_full_pred_2_slot_valids_1),
|
|
.io_out_s1_full_pred_2_targets_0
|
|
(_predictors_io_out_s1_full_pred_2_targets_0),
|
|
.io_out_s1_full_pred_2_targets_1
|
|
(_predictors_io_out_s1_full_pred_2_targets_1),
|
|
.io_out_s1_full_pred_2_offsets_0
|
|
(_predictors_io_out_s1_full_pred_2_offsets_0),
|
|
.io_out_s1_full_pred_2_offsets_1
|
|
(_predictors_io_out_s1_full_pred_2_offsets_1),
|
|
.io_out_s1_full_pred_2_fallThroughAddr
|
|
(_predictors_io_out_s1_full_pred_2_fallThroughAddr),
|
|
.io_out_s1_full_pred_2_is_br_sharing
|
|
(_predictors_io_out_s1_full_pred_2_is_br_sharing),
|
|
.io_out_s1_full_pred_2_hit
|
|
(_predictors_io_out_s1_full_pred_2_hit),
|
|
.io_out_s1_full_pred_3_br_taken_mask_0
|
|
(_predictors_io_out_s1_full_pred_3_br_taken_mask_0),
|
|
.io_out_s1_full_pred_3_br_taken_mask_1
|
|
(_predictors_io_out_s1_full_pred_3_br_taken_mask_1),
|
|
.io_out_s1_full_pred_3_slot_valids_0
|
|
(_predictors_io_out_s1_full_pred_3_slot_valids_0),
|
|
.io_out_s1_full_pred_3_slot_valids_1
|
|
(_predictors_io_out_s1_full_pred_3_slot_valids_1),
|
|
.io_out_s1_full_pred_3_targets_0
|
|
(_predictors_io_out_s1_full_pred_3_targets_0),
|
|
.io_out_s1_full_pred_3_targets_1
|
|
(_predictors_io_out_s1_full_pred_3_targets_1),
|
|
.io_out_s1_full_pred_3_offsets_0
|
|
(_predictors_io_out_s1_full_pred_3_offsets_0),
|
|
.io_out_s1_full_pred_3_offsets_1
|
|
(_predictors_io_out_s1_full_pred_3_offsets_1),
|
|
.io_out_s1_full_pred_3_fallThroughAddr
|
|
(_predictors_io_out_s1_full_pred_3_fallThroughAddr),
|
|
.io_out_s1_full_pred_3_fallThroughErr
|
|
(io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughErr),
|
|
.io_out_s1_full_pred_3_is_br_sharing
|
|
(_predictors_io_out_s1_full_pred_3_is_br_sharing),
|
|
.io_out_s1_full_pred_3_hit
|
|
(_predictors_io_out_s1_full_pred_3_hit),
|
|
.io_out_s2_pc_0
|
|
(_predictors_io_out_s2_pc_0),
|
|
.io_out_s2_pc_1
|
|
(_predictors_io_out_s2_pc_1),
|
|
.io_out_s2_pc_2
|
|
(_predictors_io_out_s2_pc_2),
|
|
.io_out_s2_pc_3
|
|
(_predictors_io_out_s2_pc_3),
|
|
.io_out_s2_full_pred_0_br_taken_mask_0
|
|
(_predictors_io_out_s2_full_pred_0_br_taken_mask_0),
|
|
.io_out_s2_full_pred_0_br_taken_mask_1
|
|
(_predictors_io_out_s2_full_pred_0_br_taken_mask_1),
|
|
.io_out_s2_full_pred_0_slot_valids_0
|
|
(_predictors_io_out_s2_full_pred_0_slot_valids_0),
|
|
.io_out_s2_full_pred_0_slot_valids_1
|
|
(_predictors_io_out_s2_full_pred_0_slot_valids_1),
|
|
.io_out_s2_full_pred_0_targets_0
|
|
(_predictors_io_out_s2_full_pred_0_targets_0),
|
|
.io_out_s2_full_pred_0_targets_1
|
|
(_predictors_io_out_s2_full_pred_0_targets_1),
|
|
.io_out_s2_full_pred_0_offsets_0
|
|
(_predictors_io_out_s2_full_pred_0_offsets_0),
|
|
.io_out_s2_full_pred_0_offsets_1
|
|
(_predictors_io_out_s2_full_pred_0_offsets_1),
|
|
.io_out_s2_full_pred_0_fallThroughAddr
|
|
(_predictors_io_out_s2_full_pred_0_fallThroughAddr),
|
|
.io_out_s2_full_pred_0_is_br_sharing
|
|
(_predictors_io_out_s2_full_pred_0_is_br_sharing),
|
|
.io_out_s2_full_pred_0_hit
|
|
(_predictors_io_out_s2_full_pred_0_hit),
|
|
.io_out_s2_full_pred_1_br_taken_mask_0
|
|
(_predictors_io_out_s2_full_pred_1_br_taken_mask_0),
|
|
.io_out_s2_full_pred_1_br_taken_mask_1
|
|
(_predictors_io_out_s2_full_pred_1_br_taken_mask_1),
|
|
.io_out_s2_full_pred_1_slot_valids_0
|
|
(_predictors_io_out_s2_full_pred_1_slot_valids_0),
|
|
.io_out_s2_full_pred_1_slot_valids_1
|
|
(_predictors_io_out_s2_full_pred_1_slot_valids_1),
|
|
.io_out_s2_full_pred_1_targets_0
|
|
(_predictors_io_out_s2_full_pred_1_targets_0),
|
|
.io_out_s2_full_pred_1_targets_1
|
|
(_predictors_io_out_s2_full_pred_1_targets_1),
|
|
.io_out_s2_full_pred_1_offsets_0
|
|
(_predictors_io_out_s2_full_pred_1_offsets_0),
|
|
.io_out_s2_full_pred_1_offsets_1
|
|
(_predictors_io_out_s2_full_pred_1_offsets_1),
|
|
.io_out_s2_full_pred_1_fallThroughAddr
|
|
(_predictors_io_out_s2_full_pred_1_fallThroughAddr),
|
|
.io_out_s2_full_pred_1_is_br_sharing
|
|
(_predictors_io_out_s2_full_pred_1_is_br_sharing),
|
|
.io_out_s2_full_pred_1_hit
|
|
(_predictors_io_out_s2_full_pred_1_hit),
|
|
.io_out_s2_full_pred_2_br_taken_mask_0
|
|
(_predictors_io_out_s2_full_pred_2_br_taken_mask_0),
|
|
.io_out_s2_full_pred_2_br_taken_mask_1
|
|
(_predictors_io_out_s2_full_pred_2_br_taken_mask_1),
|
|
.io_out_s2_full_pred_2_slot_valids_0
|
|
(_predictors_io_out_s2_full_pred_2_slot_valids_0),
|
|
.io_out_s2_full_pred_2_slot_valids_1
|
|
(_predictors_io_out_s2_full_pred_2_slot_valids_1),
|
|
.io_out_s2_full_pred_2_targets_0
|
|
(_predictors_io_out_s2_full_pred_2_targets_0),
|
|
.io_out_s2_full_pred_2_targets_1
|
|
(_predictors_io_out_s2_full_pred_2_targets_1),
|
|
.io_out_s2_full_pred_2_offsets_0
|
|
(_predictors_io_out_s2_full_pred_2_offsets_0),
|
|
.io_out_s2_full_pred_2_offsets_1
|
|
(_predictors_io_out_s2_full_pred_2_offsets_1),
|
|
.io_out_s2_full_pred_2_fallThroughAddr
|
|
(_predictors_io_out_s2_full_pred_2_fallThroughAddr),
|
|
.io_out_s2_full_pred_2_is_br_sharing
|
|
(_predictors_io_out_s2_full_pred_2_is_br_sharing),
|
|
.io_out_s2_full_pred_2_hit
|
|
(_predictors_io_out_s2_full_pred_2_hit),
|
|
.io_out_s2_full_pred_3_br_taken_mask_0
|
|
(_predictors_io_out_s2_full_pred_3_br_taken_mask_0),
|
|
.io_out_s2_full_pred_3_br_taken_mask_1
|
|
(_predictors_io_out_s2_full_pred_3_br_taken_mask_1),
|
|
.io_out_s2_full_pred_3_slot_valids_0
|
|
(_predictors_io_out_s2_full_pred_3_slot_valids_0),
|
|
.io_out_s2_full_pred_3_slot_valids_1
|
|
(_predictors_io_out_s2_full_pred_3_slot_valids_1),
|
|
.io_out_s2_full_pred_3_targets_0
|
|
(_predictors_io_out_s2_full_pred_3_targets_0),
|
|
.io_out_s2_full_pred_3_targets_1
|
|
(_predictors_io_out_s2_full_pred_3_targets_1),
|
|
.io_out_s2_full_pred_3_offsets_0
|
|
(_predictors_io_out_s2_full_pred_3_offsets_0),
|
|
.io_out_s2_full_pred_3_offsets_1
|
|
(_predictors_io_out_s2_full_pred_3_offsets_1),
|
|
.io_out_s2_full_pred_3_fallThroughAddr
|
|
(_predictors_io_out_s2_full_pred_3_fallThroughAddr),
|
|
.io_out_s2_full_pred_3_fallThroughErr
|
|
(io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughErr),
|
|
.io_out_s2_full_pred_3_is_br_sharing
|
|
(_predictors_io_out_s2_full_pred_3_is_br_sharing),
|
|
.io_out_s2_full_pred_3_hit
|
|
(_predictors_io_out_s2_full_pred_3_hit),
|
|
.io_out_s3_pc_0
|
|
(_predictors_io_out_s3_pc_0),
|
|
.io_out_s3_pc_1
|
|
(_predictors_io_out_s3_pc_1),
|
|
.io_out_s3_pc_2
|
|
(_predictors_io_out_s3_pc_2),
|
|
.io_out_s3_pc_3
|
|
(_predictors_io_out_s3_pc_3),
|
|
.io_out_s3_full_pred_0_br_taken_mask_0
|
|
(_predictors_io_out_s3_full_pred_0_br_taken_mask_0),
|
|
.io_out_s3_full_pred_0_br_taken_mask_1
|
|
(_predictors_io_out_s3_full_pred_0_br_taken_mask_1),
|
|
.io_out_s3_full_pred_0_slot_valids_0
|
|
(_predictors_io_out_s3_full_pred_0_slot_valids_0),
|
|
.io_out_s3_full_pred_0_slot_valids_1
|
|
(_predictors_io_out_s3_full_pred_0_slot_valids_1),
|
|
.io_out_s3_full_pred_0_targets_0
|
|
(_predictors_io_out_s3_full_pred_0_targets_0),
|
|
.io_out_s3_full_pred_0_targets_1
|
|
(_predictors_io_out_s3_full_pred_0_targets_1),
|
|
.io_out_s3_full_pred_0_fallThroughAddr
|
|
(_predictors_io_out_s3_full_pred_0_fallThroughAddr),
|
|
.io_out_s3_full_pred_0_fallThroughErr
|
|
(_predictors_io_out_s3_full_pred_0_fallThroughErr),
|
|
.io_out_s3_full_pred_0_is_br_sharing
|
|
(_predictors_io_out_s3_full_pred_0_is_br_sharing),
|
|
.io_out_s3_full_pred_0_hit
|
|
(_predictors_io_out_s3_full_pred_0_hit),
|
|
.io_out_s3_full_pred_1_br_taken_mask_0
|
|
(_predictors_io_out_s3_full_pred_1_br_taken_mask_0),
|
|
.io_out_s3_full_pred_1_br_taken_mask_1
|
|
(_predictors_io_out_s3_full_pred_1_br_taken_mask_1),
|
|
.io_out_s3_full_pred_1_slot_valids_0
|
|
(_predictors_io_out_s3_full_pred_1_slot_valids_0),
|
|
.io_out_s3_full_pred_1_slot_valids_1
|
|
(_predictors_io_out_s3_full_pred_1_slot_valids_1),
|
|
.io_out_s3_full_pred_1_targets_0
|
|
(_predictors_io_out_s3_full_pred_1_targets_0),
|
|
.io_out_s3_full_pred_1_targets_1
|
|
(_predictors_io_out_s3_full_pred_1_targets_1),
|
|
.io_out_s3_full_pred_1_fallThroughAddr
|
|
(_predictors_io_out_s3_full_pred_1_fallThroughAddr),
|
|
.io_out_s3_full_pred_1_fallThroughErr
|
|
(_predictors_io_out_s3_full_pred_1_fallThroughErr),
|
|
.io_out_s3_full_pred_1_is_br_sharing
|
|
(_predictors_io_out_s3_full_pred_1_is_br_sharing),
|
|
.io_out_s3_full_pred_1_hit
|
|
(_predictors_io_out_s3_full_pred_1_hit),
|
|
.io_out_s3_full_pred_2_br_taken_mask_0
|
|
(_predictors_io_out_s3_full_pred_2_br_taken_mask_0),
|
|
.io_out_s3_full_pred_2_br_taken_mask_1
|
|
(_predictors_io_out_s3_full_pred_2_br_taken_mask_1),
|
|
.io_out_s3_full_pred_2_slot_valids_0
|
|
(_predictors_io_out_s3_full_pred_2_slot_valids_0),
|
|
.io_out_s3_full_pred_2_slot_valids_1
|
|
(_predictors_io_out_s3_full_pred_2_slot_valids_1),
|
|
.io_out_s3_full_pred_2_targets_0
|
|
(_predictors_io_out_s3_full_pred_2_targets_0),
|
|
.io_out_s3_full_pred_2_targets_1
|
|
(_predictors_io_out_s3_full_pred_2_targets_1),
|
|
.io_out_s3_full_pred_2_fallThroughAddr
|
|
(_predictors_io_out_s3_full_pred_2_fallThroughAddr),
|
|
.io_out_s3_full_pred_2_fallThroughErr
|
|
(_predictors_io_out_s3_full_pred_2_fallThroughErr),
|
|
.io_out_s3_full_pred_2_is_br_sharing
|
|
(_predictors_io_out_s3_full_pred_2_is_br_sharing),
|
|
.io_out_s3_full_pred_2_hit
|
|
(_predictors_io_out_s3_full_pred_2_hit),
|
|
.io_out_s3_full_pred_3_br_taken_mask_0
|
|
(_predictors_io_out_s3_full_pred_3_br_taken_mask_0),
|
|
.io_out_s3_full_pred_3_br_taken_mask_1
|
|
(_predictors_io_out_s3_full_pred_3_br_taken_mask_1),
|
|
.io_out_s3_full_pred_3_slot_valids_0
|
|
(_predictors_io_out_s3_full_pred_3_slot_valids_0),
|
|
.io_out_s3_full_pred_3_slot_valids_1
|
|
(_predictors_io_out_s3_full_pred_3_slot_valids_1),
|
|
.io_out_s3_full_pred_3_targets_0
|
|
(_predictors_io_out_s3_full_pred_3_targets_0),
|
|
.io_out_s3_full_pred_3_targets_1
|
|
(_predictors_io_out_s3_full_pred_3_targets_1),
|
|
.io_out_s3_full_pred_3_offsets_0
|
|
(io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_0),
|
|
.io_out_s3_full_pred_3_offsets_1
|
|
(io_bpu_to_ftq_resp_bits_s3_full_pred_3_offsets_1),
|
|
.io_out_s3_full_pred_3_fallThroughAddr
|
|
(_predictors_io_out_s3_full_pred_3_fallThroughAddr),
|
|
.io_out_s3_full_pred_3_fallThroughErr
|
|
(_predictors_io_out_s3_full_pred_3_fallThroughErr),
|
|
.io_out_s3_full_pred_3_is_br_sharing
|
|
(_predictors_io_out_s3_full_pred_3_is_br_sharing),
|
|
.io_out_s3_full_pred_3_hit
|
|
(_predictors_io_out_s3_full_pred_3_hit),
|
|
.io_out_last_stage_meta
|
|
(io_bpu_to_ftq_resp_bits_last_stage_meta),
|
|
.io_out_last_stage_spec_info_ssp
|
|
(io_bpu_to_ftq_resp_bits_last_stage_spec_info_ssp),
|
|
.io_out_last_stage_spec_info_sctr
|
|
(io_bpu_to_ftq_resp_bits_last_stage_spec_info_sctr),
|
|
.io_out_last_stage_spec_info_TOSW_flag
|
|
(io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_flag),
|
|
.io_out_last_stage_spec_info_TOSW_value
|
|
(io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSW_value),
|
|
.io_out_last_stage_spec_info_TOSR_flag
|
|
(io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_flag),
|
|
.io_out_last_stage_spec_info_TOSR_value
|
|
(io_bpu_to_ftq_resp_bits_last_stage_spec_info_TOSR_value),
|
|
.io_out_last_stage_spec_info_NOS_flag
|
|
(io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_flag),
|
|
.io_out_last_stage_spec_info_NOS_value
|
|
(io_bpu_to_ftq_resp_bits_last_stage_spec_info_NOS_value),
|
|
.io_out_last_stage_spec_info_topAddr
|
|
(io_bpu_to_ftq_resp_bits_last_stage_spec_info_topAddr),
|
|
.io_out_last_stage_ftb_entry_valid
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_valid),
|
|
.io_out_last_stage_ftb_entry_brSlots_0_offset
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_offset),
|
|
.io_out_last_stage_ftb_entry_brSlots_0_lower
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_lower),
|
|
.io_out_last_stage_ftb_entry_brSlots_0_tarStat
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_tarStat),
|
|
.io_out_last_stage_ftb_entry_brSlots_0_sharing
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_sharing),
|
|
.io_out_last_stage_ftb_entry_brSlots_0_valid
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_brSlots_0_valid),
|
|
.io_out_last_stage_ftb_entry_tailSlot_offset
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_offset),
|
|
.io_out_last_stage_ftb_entry_tailSlot_lower
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_lower),
|
|
.io_out_last_stage_ftb_entry_tailSlot_tarStat
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_tarStat),
|
|
.io_out_last_stage_ftb_entry_tailSlot_sharing
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_sharing),
|
|
.io_out_last_stage_ftb_entry_tailSlot_valid
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_tailSlot_valid),
|
|
.io_out_last_stage_ftb_entry_pftAddr
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_pftAddr),
|
|
.io_out_last_stage_ftb_entry_carry
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_carry),
|
|
.io_out_last_stage_ftb_entry_isCall
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isCall),
|
|
.io_out_last_stage_ftb_entry_isRet
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isRet),
|
|
.io_out_last_stage_ftb_entry_isJalr
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_isJalr),
|
|
.io_out_last_stage_ftb_entry_last_may_be_rvi_call
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_last_may_be_rvi_call),
|
|
.io_out_last_stage_ftb_entry_always_taken_0
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_0),
|
|
.io_out_last_stage_ftb_entry_always_taken_1
|
|
(io_bpu_to_ftq_resp_bits_last_stage_ftb_entry_always_taken_1),
|
|
.io_ctrl_ubtb_enable
|
|
(_ctrl_delay_io_out_ubtb_enable), // utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_ctrl_btb_enable
|
|
(_ctrl_delay_io_out_btb_enable), // utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_ctrl_tage_enable
|
|
(_ctrl_delay_io_out_tage_enable), // utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_ctrl_sc_enable
|
|
(_ctrl_delay_io_out_sc_enable), // utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_ctrl_ras_enable
|
|
(_ctrl_delay_io_out_ras_enable), // utility/src/main/scala/utility/Hold.scala:97:23
|
|
.io_s0_fire_0 (s0_fire_dup_0), // src/main/scala/xiangshan/frontend/BPU.scala:367:36
|
|
.io_s0_fire_1 (s0_fire_dup_1), // src/main/scala/xiangshan/frontend/BPU.scala:367:36
|
|
.io_s0_fire_2 (s0_fire_dup_2), // src/main/scala/xiangshan/frontend/BPU.scala:367:36
|
|
.io_s0_fire_3 (s0_fire_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:367:36
|
|
.io_s1_fire_0 (s1_fire_dup_0), // src/main/scala/xiangshan/frontend/BPU.scala:374:60
|
|
.io_s1_fire_1 (s1_fire_dup_1), // src/main/scala/xiangshan/frontend/BPU.scala:374:60
|
|
.io_s1_fire_2 (s1_fire_dup_2), // src/main/scala/xiangshan/frontend/BPU.scala:374:60
|
|
.io_s1_fire_3 (s1_fire_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:374:60
|
|
.io_s2_fire_0 (s2_valid_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:271:65
|
|
.io_s2_fire_1 (s2_valid_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:271:65
|
|
.io_s2_fire_2 (s2_valid_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:271:65
|
|
.io_s2_fire_3 (s2_valid_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:271:65
|
|
.io_s3_fire_2 (s3_valid_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:271:65
|
|
.io_s3_redirect_2 (s3_redirect_dup_2), // src/main/scala/xiangshan/frontend/BPU.scala:684:28
|
|
.io_s1_ready (_predictors_io_s1_ready),
|
|
.io_update_valid
|
|
(predictors_io_update_REG_valid), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_pc
|
|
(predictors_io_update_REG_bits_pc), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_spec_info_folded_hist_hist_17_folded_hist
|
|
(predictors_io_update_REG_bits_spec_info_folded_hist_hist_17_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_spec_info_folded_hist_hist_16_folded_hist
|
|
(predictors_io_update_REG_bits_spec_info_folded_hist_hist_16_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_spec_info_folded_hist_hist_15_folded_hist
|
|
(predictors_io_update_REG_bits_spec_info_folded_hist_hist_15_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_spec_info_folded_hist_hist_14_folded_hist
|
|
(predictors_io_update_REG_bits_spec_info_folded_hist_hist_14_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_spec_info_folded_hist_hist_13_folded_hist
|
|
(predictors_io_update_REG_bits_spec_info_folded_hist_hist_13_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_spec_info_folded_hist_hist_12_folded_hist
|
|
(predictors_io_update_REG_bits_spec_info_folded_hist_hist_12_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_spec_info_folded_hist_hist_11_folded_hist
|
|
(predictors_io_update_REG_bits_spec_info_folded_hist_hist_11_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_spec_info_folded_hist_hist_10_folded_hist
|
|
(predictors_io_update_REG_bits_spec_info_folded_hist_hist_10_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_spec_info_folded_hist_hist_9_folded_hist
|
|
(predictors_io_update_REG_bits_spec_info_folded_hist_hist_9_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_spec_info_folded_hist_hist_8_folded_hist
|
|
(predictors_io_update_REG_bits_spec_info_folded_hist_hist_8_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_spec_info_folded_hist_hist_7_folded_hist
|
|
(predictors_io_update_REG_bits_spec_info_folded_hist_hist_7_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_spec_info_folded_hist_hist_6_folded_hist
|
|
(predictors_io_update_REG_bits_spec_info_folded_hist_hist_6_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_spec_info_folded_hist_hist_5_folded_hist
|
|
(predictors_io_update_REG_bits_spec_info_folded_hist_hist_5_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_spec_info_folded_hist_hist_4_folded_hist
|
|
(predictors_io_update_REG_bits_spec_info_folded_hist_hist_4_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_spec_info_folded_hist_hist_3_folded_hist
|
|
(predictors_io_update_REG_bits_spec_info_folded_hist_hist_3_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_spec_info_folded_hist_hist_2_folded_hist
|
|
(predictors_io_update_REG_bits_spec_info_folded_hist_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_spec_info_folded_hist_hist_1_folded_hist
|
|
(predictors_io_update_REG_bits_spec_info_folded_hist_hist_1_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_valid
|
|
(predictors_io_update_REG_bits_ftb_entry_valid), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_brSlots_0_offset
|
|
(predictors_io_update_REG_bits_ftb_entry_brSlots_0_offset), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_brSlots_0_lower
|
|
(predictors_io_update_REG_bits_ftb_entry_brSlots_0_lower), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_brSlots_0_tarStat
|
|
(predictors_io_update_REG_bits_ftb_entry_brSlots_0_tarStat), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_brSlots_0_sharing
|
|
(predictors_io_update_REG_bits_ftb_entry_brSlots_0_sharing), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_brSlots_0_valid
|
|
(predictors_io_update_REG_bits_ftb_entry_brSlots_0_valid), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_tailSlot_offset
|
|
(predictors_io_update_REG_bits_ftb_entry_tailSlot_offset), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_tailSlot_lower
|
|
(predictors_io_update_REG_bits_ftb_entry_tailSlot_lower), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_tailSlot_tarStat
|
|
(predictors_io_update_REG_bits_ftb_entry_tailSlot_tarStat), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_tailSlot_sharing
|
|
(predictors_io_update_REG_bits_ftb_entry_tailSlot_sharing), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_tailSlot_valid
|
|
(predictors_io_update_REG_bits_ftb_entry_tailSlot_valid), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_pftAddr
|
|
(predictors_io_update_REG_bits_ftb_entry_pftAddr), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_carry
|
|
(predictors_io_update_REG_bits_ftb_entry_carry), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_isCall
|
|
(predictors_io_update_REG_bits_ftb_entry_isCall), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_isRet
|
|
(predictors_io_update_REG_bits_ftb_entry_isRet), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_isJalr
|
|
(predictors_io_update_REG_bits_ftb_entry_isJalr), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_last_may_be_rvi_call
|
|
(predictors_io_update_REG_bits_ftb_entry_last_may_be_rvi_call), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_always_taken_0
|
|
(predictors_io_update_REG_bits_ftb_entry_always_taken_0), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_ftb_entry_always_taken_1
|
|
(predictors_io_update_REG_bits_ftb_entry_always_taken_1), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_cfi_idx_valid
|
|
(predictors_io_update_REG_bits_cfi_idx_valid), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_cfi_idx_bits
|
|
(predictors_io_update_REG_bits_cfi_idx_bits), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_br_taken_mask_0
|
|
(predictors_io_update_REG_bits_br_taken_mask_0), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_br_taken_mask_1
|
|
(predictors_io_update_REG_bits_br_taken_mask_1), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_jmp_taken
|
|
(predictors_io_update_REG_bits_jmp_taken), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_mispred_mask_0
|
|
(predictors_io_update_REG_bits_mispred_mask_0), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_mispred_mask_1
|
|
(predictors_io_update_REG_bits_mispred_mask_1), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_mispred_mask_2
|
|
(predictors_io_update_REG_bits_mispred_mask_2), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_old_entry
|
|
(predictors_io_update_REG_bits_old_entry), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_meta
|
|
(predictors_io_update_REG_bits_meta), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_update_bits_full_target
|
|
(predictors_io_update_REG_bits_full_target), // src/main/scala/xiangshan/frontend/BPU.scala:727:34
|
|
.io_redirect_valid (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.io_redirect_bits_level
|
|
(do_redirect_dup_3_bits_level), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.io_redirect_bits_cfiUpdate_pc
|
|
(do_redirect_dup_3_bits_cfiUpdate_pc), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.io_redirect_bits_cfiUpdate_pd_isRVC
|
|
(do_redirect_dup_3_bits_cfiUpdate_pd_isRVC), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.io_redirect_bits_cfiUpdate_pd_isCall
|
|
(do_redirect_dup_3_bits_cfiUpdate_pd_isCall), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.io_redirect_bits_cfiUpdate_pd_isRet
|
|
(do_redirect_dup_3_bits_cfiUpdate_pd_isRet), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.io_redirect_bits_cfiUpdate_ssp
|
|
(do_redirect_dup_3_bits_cfiUpdate_ssp), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.io_redirect_bits_cfiUpdate_sctr
|
|
(do_redirect_dup_3_bits_cfiUpdate_sctr), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.io_redirect_bits_cfiUpdate_TOSW_flag
|
|
(do_redirect_dup_3_bits_cfiUpdate_TOSW_flag), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.io_redirect_bits_cfiUpdate_TOSW_value
|
|
(do_redirect_dup_3_bits_cfiUpdate_TOSW_value), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.io_redirect_bits_cfiUpdate_TOSR_flag
|
|
(do_redirect_dup_3_bits_cfiUpdate_TOSR_flag), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.io_redirect_bits_cfiUpdate_TOSR_value
|
|
(do_redirect_dup_3_bits_cfiUpdate_TOSR_value), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.io_redirect_bits_cfiUpdate_NOS_flag
|
|
(do_redirect_dup_3_bits_cfiUpdate_NOS_flag), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.io_redirect_bits_cfiUpdate_NOS_value
|
|
(do_redirect_dup_3_bits_cfiUpdate_NOS_value) // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
);
|
|
DelayN_2 reset_vector_delay ( // utility/src/main/scala/utility/Hold.scala:97:23
|
|
.clock (clock),
|
|
.io_in (io_reset_vector),
|
|
.io_out (_reset_vector_delay_io_out)
|
|
);
|
|
PriorityMuxModule s0_pc_dup_0_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_target_sel
|
|
(s2_redirect_dup_0 & ~s3_redirect_dup_0 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_target_src
|
|
((_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
? _predictors_io_out_s2_full_pred_0_targets_0
|
|
: 39'h0)
|
|
| (~_selVecOH_T_66 & _GEN_21 & _predictors_io_out_s2_full_pred_0_hit
|
|
? _predictors_io_out_s2_full_pred_0_targets_1
|
|
: 39'h0)
|
|
| ({_GEN_21, _selVecOH_T_66} == 2'h0 & _predictors_io_out_s2_full_pred_0_hit
|
|
? _predictors_io_out_s2_full_pred_0_fallThroughAddr
|
|
: 39'h0)
|
|
| (_predictors_io_out_s2_full_pred_0_hit
|
|
? 39'h0
|
|
: _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_0_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47
|
|
.s1_target_sel
|
|
(s1_valid_dup_3 & ~s2_redirect_dup_0 & ~s3_redirect_dup_0
|
|
& ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_target_src
|
|
((_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
? _predictors_io_out_s1_full_pred_0_targets_0
|
|
: 39'h0)
|
|
| (~_cfiIndex_bits_WIRE_18_0 & s1_pred_info_takenMask_0_1
|
|
& _predictors_io_out_s1_full_pred_0_hit
|
|
? _predictors_io_out_s1_full_pred_0_targets_1
|
|
: 39'h0)
|
|
| ({s1_pred_info_takenMask_0_1, _cfiIndex_bits_WIRE_18_0} == 2'h0
|
|
& _predictors_io_out_s1_full_pred_0_hit
|
|
? _predictors_io_out_s1_full_pred_0_fallThroughAddr
|
|
: 39'h0) | _GEN_4), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25
|
|
.s3_target_sel (s3_redirect_dup_0 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_target_src
|
|
((_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
? _predictors_io_out_s3_full_pred_0_targets_0
|
|
: 39'h0)
|
|
| (~_selVecOH_T_98 & _GEN_32 & _predictors_io_out_s3_full_pred_0_hit
|
|
? _predictors_io_out_s3_full_pred_0_targets_1
|
|
: 39'h0)
|
|
| ({_GEN_32, _selVecOH_T_98} == 2'h0 & _predictors_io_out_s3_full_pred_0_hit
|
|
? _predictors_io_out_s3_full_pred_0_fallThroughAddr
|
|
: 39'h0)
|
|
| (_predictors_io_out_s3_full_pred_0_hit
|
|
? 39'h0
|
|
: _s3_redirect_on_target_dup_WIRE_1_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47
|
|
.redirect_target_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.redirect_target_src (do_redirect_dup_3_bits_cfiUpdate_target), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.stallPC_src (s0_pc_reg_dup_0), // src/main/scala/xiangshan/frontend/BPU.scala:276:49
|
|
.out_res (_s0_pc_dup_0_ppm_out_res)
|
|
);
|
|
PriorityMuxModule s0_pc_dup_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_target_sel
|
|
(s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_target_src
|
|
((_selVecOH_T_74 & _predictors_io_out_s2_full_pred_1_hit
|
|
? _predictors_io_out_s2_full_pred_1_targets_0
|
|
: 39'h0)
|
|
| (~_selVecOH_T_74 & _GEN_22 & _predictors_io_out_s2_full_pred_1_hit
|
|
? _predictors_io_out_s2_full_pred_1_targets_1
|
|
: 39'h0)
|
|
| ({_GEN_22, _selVecOH_T_74} == 2'h0 & _predictors_io_out_s2_full_pred_1_hit
|
|
? _predictors_io_out_s2_full_pred_1_fallThroughAddr
|
|
: 39'h0)
|
|
| (_predictors_io_out_s2_full_pred_1_hit
|
|
? 39'h0
|
|
: _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_1_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47
|
|
.s1_target_sel
|
|
(s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1
|
|
& ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_target_src
|
|
((_cfiIndex_bits_WIRE_22_0 & _predictors_io_out_s1_full_pred_1_hit
|
|
? _predictors_io_out_s1_full_pred_1_targets_0
|
|
: 39'h0)
|
|
| (~_cfiIndex_bits_WIRE_22_0 & s1_pred_info_takenMask_1_1
|
|
& _predictors_io_out_s1_full_pred_1_hit
|
|
? _predictors_io_out_s1_full_pred_1_targets_1
|
|
: 39'h0)
|
|
| ({s1_pred_info_takenMask_1_1, _cfiIndex_bits_WIRE_22_0} == 2'h0
|
|
& _predictors_io_out_s1_full_pred_1_hit
|
|
? _predictors_io_out_s1_full_pred_1_fallThroughAddr
|
|
: 39'h0) | _GEN_5), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25
|
|
.s3_target_sel (s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_target_src
|
|
((_selVecOH_T_106 & _predictors_io_out_s3_full_pred_1_hit
|
|
? _predictors_io_out_s3_full_pred_1_targets_0
|
|
: 39'h0)
|
|
| (~_selVecOH_T_106 & _GEN_33 & _predictors_io_out_s3_full_pred_1_hit
|
|
? _predictors_io_out_s3_full_pred_1_targets_1
|
|
: 39'h0)
|
|
| ({_GEN_33, _selVecOH_T_106} == 2'h0 & _predictors_io_out_s3_full_pred_1_hit
|
|
? _predictors_io_out_s3_full_pred_1_fallThroughAddr
|
|
: 39'h0)
|
|
| (_predictors_io_out_s3_full_pred_1_hit
|
|
? 39'h0
|
|
: _s3_redirect_on_target_dup_WIRE_4_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47
|
|
.redirect_target_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.redirect_target_src (do_redirect_dup_3_bits_cfiUpdate_target), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.stallPC_src (s0_pc_reg_dup_1), // src/main/scala/xiangshan/frontend/BPU.scala:276:49
|
|
.out_res (_s0_pc_dup_1_ppm_out_res)
|
|
);
|
|
PriorityMuxModule s0_pc_dup_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_target_sel
|
|
(s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_target_src
|
|
((_selVecOH_T_82 & _predictors_io_out_s2_full_pred_2_hit
|
|
? _predictors_io_out_s2_full_pred_2_targets_0
|
|
: 39'h0)
|
|
| (~_selVecOH_T_82 & _GEN_23 & _predictors_io_out_s2_full_pred_2_hit
|
|
? _predictors_io_out_s2_full_pred_2_targets_1
|
|
: 39'h0)
|
|
| ({_GEN_23, _selVecOH_T_82} == 2'h0 & _predictors_io_out_s2_full_pred_2_hit
|
|
? _predictors_io_out_s2_full_pred_2_fallThroughAddr
|
|
: 39'h0)
|
|
| (_predictors_io_out_s2_full_pred_2_hit
|
|
? 39'h0
|
|
: _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_2_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47
|
|
.s1_target_sel
|
|
(s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2
|
|
& ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_target_src
|
|
((_cfiIndex_bits_WIRE_26_0 & _predictors_io_out_s1_full_pred_2_hit
|
|
? _predictors_io_out_s1_full_pred_2_targets_0
|
|
: 39'h0)
|
|
| (~_cfiIndex_bits_WIRE_26_0 & s1_pred_info_takenMask_2_1
|
|
& _predictors_io_out_s1_full_pred_2_hit
|
|
? _predictors_io_out_s1_full_pred_2_targets_1
|
|
: 39'h0)
|
|
| ({s1_pred_info_takenMask_2_1, _cfiIndex_bits_WIRE_26_0} == 2'h0
|
|
& _predictors_io_out_s1_full_pred_2_hit
|
|
? _predictors_io_out_s1_full_pred_2_fallThroughAddr
|
|
: 39'h0) | _GEN_6), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25
|
|
.s3_target_sel (s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_target_src
|
|
((_selVecOH_T_114 & _predictors_io_out_s3_full_pred_2_hit
|
|
? _predictors_io_out_s3_full_pred_2_targets_0
|
|
: 39'h0)
|
|
| (~_selVecOH_T_114 & _GEN_34 & _predictors_io_out_s3_full_pred_2_hit
|
|
? _predictors_io_out_s3_full_pred_2_targets_1
|
|
: 39'h0)
|
|
| ({_GEN_34, _selVecOH_T_114} == 2'h0 & _predictors_io_out_s3_full_pred_2_hit
|
|
? _predictors_io_out_s3_full_pred_2_fallThroughAddr
|
|
: 39'h0)
|
|
| (_predictors_io_out_s3_full_pred_2_hit
|
|
? 39'h0
|
|
: _s3_redirect_on_target_dup_WIRE_7_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47
|
|
.redirect_target_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.redirect_target_src (do_redirect_dup_3_bits_cfiUpdate_target), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.stallPC_src (s0_pc_reg_dup_2), // src/main/scala/xiangshan/frontend/BPU.scala:276:49
|
|
.out_res (_s0_pc_dup_2_ppm_out_res)
|
|
);
|
|
PriorityMuxModule s0_pc_dup_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_target_sel
|
|
(s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_target_src
|
|
((_selVecOH_T_90 & _predictors_io_out_s2_full_pred_3_hit
|
|
? _predictors_io_out_s2_full_pred_3_targets_0
|
|
: 39'h0)
|
|
| (~_selVecOH_T_90 & _GEN_24 & _predictors_io_out_s2_full_pred_3_hit
|
|
? _predictors_io_out_s2_full_pred_3_targets_1
|
|
: 39'h0)
|
|
| ({_GEN_24, _selVecOH_T_90} == 2'h0 & _predictors_io_out_s2_full_pred_3_hit
|
|
? _predictors_io_out_s2_full_pred_3_fallThroughAddr
|
|
: 39'h0)
|
|
| (_predictors_io_out_s2_full_pred_3_hit
|
|
? 39'h0
|
|
: _s2_redirect_s1_last_pred_vec_dup_targetDiffVec_WIRE_4_3_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47
|
|
.s1_target_sel
|
|
(s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3
|
|
& ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_target_src
|
|
((_cfiIndex_bits_WIRE_30_0 & _predictors_io_out_s1_full_pred_3_hit
|
|
? _predictors_io_out_s1_full_pred_3_targets_0
|
|
: 39'h0)
|
|
| (~_cfiIndex_bits_WIRE_30_0 & s1_pred_info_takenMask_3_1
|
|
& _predictors_io_out_s1_full_pred_3_hit
|
|
? _predictors_io_out_s1_full_pred_3_targets_1
|
|
: 39'h0)
|
|
| ({s1_pred_info_takenMask_3_1, _cfiIndex_bits_WIRE_30_0} == 2'h0
|
|
& _predictors_io_out_s1_full_pred_3_hit
|
|
? _predictors_io_out_s1_full_pred_3_fallThroughAddr
|
|
: 39'h0) | _GEN_7), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25
|
|
.s3_target_sel (s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_target_src
|
|
((_selVecOH_T_122 & _predictors_io_out_s3_full_pred_3_hit
|
|
? _predictors_io_out_s3_full_pred_3_targets_0
|
|
: 39'h0)
|
|
| (~_selVecOH_T_122 & _GEN_35 & _predictors_io_out_s3_full_pred_3_hit
|
|
? _predictors_io_out_s3_full_pred_3_targets_1
|
|
: 39'h0)
|
|
| ({_GEN_35, _selVecOH_T_122} == 2'h0 & _predictors_io_out_s3_full_pred_3_hit
|
|
? _predictors_io_out_s3_full_pred_3_fallThroughAddr
|
|
: 39'h0)
|
|
| (_predictors_io_out_s3_full_pred_3_hit
|
|
? 39'h0
|
|
: _s3_redirect_on_target_dup_WIRE_10_3)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :343:53, src/main/scala/xiangshan/frontend/FrontendBundle.scala:420:{51,97}, :421:{21,28,32}, :458:69, :459:25, :505:47
|
|
.redirect_target_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.redirect_target_src (do_redirect_dup_3_bits_cfiUpdate_target), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.stallPC_src (s0_pc_reg_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:276:49
|
|
.out_res (_s0_pc_dup_3_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_4 s0_folded_gh_dup_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_FGH_sel
|
|
(s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_FGH_src_hist_17_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_17_folded_hist : 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_17_folded_hist[9],
|
|
s2_folded_gh_dup_1_hist_17_folded_hist[8:0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0
|
|
^ s2_folded_gh_dup_1_hist_17_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3)
|
|
^ s2_folded_gh_dup_1_hist_17_folded_hist[8],
|
|
s2_folded_gh_dup_1_hist_17_folded_hist[7:0],
|
|
s2_folded_gh_dup_1_hist_17_folded_hist[10],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_1[0]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_17_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_16_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_16_folded_hist : 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {s2_folded_gh_dup_1_hist_16_folded_hist[9],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_16_folded_hist[8],
|
|
s2_folded_gh_dup_1_hist_16_folded_hist[7:0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0
|
|
^ s2_folded_gh_dup_1_hist_16_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_16_folded_hist[8],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3)
|
|
^ s2_folded_gh_dup_1_hist_16_folded_hist[7],
|
|
s2_folded_gh_dup_1_hist_16_folded_hist[6:0],
|
|
s2_folded_gh_dup_1_hist_16_folded_hist[10],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1
|
|
^ s2_folded_gh_dup_1_hist_16_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_15_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_15_folded_hist : 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_15_folded_hist[5],
|
|
s2_folded_gh_dup_1_hist_15_folded_hist[4:0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0
|
|
^ s2_folded_gh_dup_1_hist_15_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3)
|
|
^ s2_folded_gh_dup_1_hist_15_folded_hist[4],
|
|
s2_folded_gh_dup_1_hist_15_folded_hist[3:0],
|
|
s2_folded_gh_dup_1_hist_15_folded_hist[6],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_1[0]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_15_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_14_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_14_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {s2_folded_gh_dup_1_hist_14_folded_hist[6:0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {s2_folded_gh_dup_1_hist_14_folded_hist[5:0],
|
|
1'h0,
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.s2_FGH_src_hist_13_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_13_folded_hist : 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {s2_folded_gh_dup_1_hist_13_folded_hist[7:4],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_13_folded_hist[3],
|
|
s2_folded_gh_dup_1_hist_13_folded_hist[2:0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0
|
|
^ s2_folded_gh_dup_1_hist_13_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {s2_folded_gh_dup_1_hist_13_folded_hist[6:4],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_13_folded_hist[3],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3)
|
|
^ s2_folded_gh_dup_1_hist_13_folded_hist[2],
|
|
s2_folded_gh_dup_1_hist_13_folded_hist[1:0],
|
|
s2_folded_gh_dup_1_hist_13_folded_hist[8],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1
|
|
^ s2_folded_gh_dup_1_hist_13_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_12_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_12_folded_hist : 4'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {s2_folded_gh_dup_1_hist_12_folded_hist[2:0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0}
|
|
: 4'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {s2_folded_gh_dup_1_hist_12_folded_hist[1:0],
|
|
1'h0,
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1}
|
|
: 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.s2_FGH_src_hist_11_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_11_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {s2_folded_gh_dup_1_hist_11_folded_hist[6:2],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_11_folded_hist[1],
|
|
s2_folded_gh_dup_1_hist_11_folded_hist[0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0
|
|
^ s2_folded_gh_dup_1_hist_11_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {s2_folded_gh_dup_1_hist_11_folded_hist[5:2],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_11_folded_hist[1],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3)
|
|
^ s2_folded_gh_dup_1_hist_11_folded_hist[0],
|
|
s2_folded_gh_dup_1_hist_11_folded_hist[7],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1
|
|
^ s2_folded_gh_dup_1_hist_11_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_10_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_10_folded_hist : 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {s2_folded_gh_dup_1_hist_10_folded_hist[7:5],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_10_folded_hist[4],
|
|
s2_folded_gh_dup_1_hist_10_folded_hist[3:0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0
|
|
^ s2_folded_gh_dup_1_hist_10_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {s2_folded_gh_dup_1_hist_10_folded_hist[6:5],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_10_folded_hist[4],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3)
|
|
^ s2_folded_gh_dup_1_hist_10_folded_hist[3],
|
|
s2_folded_gh_dup_1_hist_10_folded_hist[2:0],
|
|
s2_folded_gh_dup_1_hist_10_folded_hist[8],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1
|
|
^ s2_folded_gh_dup_1_hist_10_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_9_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_9_folded_hist : 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {s2_folded_gh_dup_1_hist_9_folded_hist[5:4],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_9_folded_hist[3],
|
|
s2_folded_gh_dup_1_hist_9_folded_hist[2:0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0
|
|
^ s2_folded_gh_dup_1_hist_9_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {s2_folded_gh_dup_1_hist_9_folded_hist[4],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_9_folded_hist[3],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3)
|
|
^ s2_folded_gh_dup_1_hist_9_folded_hist[2],
|
|
s2_folded_gh_dup_1_hist_9_folded_hist[1:0],
|
|
s2_folded_gh_dup_1_hist_9_folded_hist[6],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1
|
|
^ s2_folded_gh_dup_1_hist_9_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_8_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_8_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_8_folded_hist[6],
|
|
s2_folded_gh_dup_1_hist_8_folded_hist[5:0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0
|
|
^ s2_folded_gh_dup_1_hist_8_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3)
|
|
^ s2_folded_gh_dup_1_hist_8_folded_hist[5],
|
|
s2_folded_gh_dup_1_hist_8_folded_hist[4:0],
|
|
s2_folded_gh_dup_1_hist_8_folded_hist[7],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_1[0]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_8_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_7_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_7_folded_hist : 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {s2_folded_gh_dup_1_hist_7_folded_hist[5:1],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_7_folded_hist[0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0
|
|
^ s2_folded_gh_dup_1_hist_7_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {s2_folded_gh_dup_1_hist_7_folded_hist[4:1],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_7_folded_hist[0],
|
|
1'h0,
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1
|
|
^ s2_folded_gh_dup_1_hist_7_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_6_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_6_folded_hist : 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {s2_folded_gh_dup_1_hist_6_folded_hist[7],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_6_folded_hist[6],
|
|
s2_folded_gh_dup_1_hist_6_folded_hist[5:0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0
|
|
^ s2_folded_gh_dup_1_hist_6_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_6_folded_hist[6],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3)
|
|
^ s2_folded_gh_dup_1_hist_6_folded_hist[5],
|
|
s2_folded_gh_dup_1_hist_6_folded_hist[4:0],
|
|
s2_folded_gh_dup_1_hist_6_folded_hist[8],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1
|
|
^ s2_folded_gh_dup_1_hist_6_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_5_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_5_folded_hist : 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {s2_folded_gh_dup_1_hist_5_folded_hist[5:0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0
|
|
^ (s2_last_br_num_oh_dup_1[0]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_5_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {s2_folded_gh_dup_1_hist_5_folded_hist[4:0],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_5_folded_hist[6],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_1[0]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3)
|
|
^ s2_folded_gh_dup_1_hist_5_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_4_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_4_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {s2_folded_gh_dup_1_hist_4_folded_hist[6:5],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_4_folded_hist[4],
|
|
s2_folded_gh_dup_1_hist_4_folded_hist[3:0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0
|
|
^ s2_folded_gh_dup_1_hist_4_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {s2_folded_gh_dup_1_hist_4_folded_hist[5],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_4_folded_hist[4],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3)
|
|
^ s2_folded_gh_dup_1_hist_4_folded_hist[3],
|
|
s2_folded_gh_dup_1_hist_4_folded_hist[2:0],
|
|
s2_folded_gh_dup_1_hist_4_folded_hist[7],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1
|
|
^ s2_folded_gh_dup_1_hist_4_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_3_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_3_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {s2_folded_gh_dup_1_hist_3_folded_hist[6:0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0
|
|
^ (s2_last_br_num_oh_dup_1[0]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_3_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {s2_folded_gh_dup_1_hist_3_folded_hist[5:0],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_3_folded_hist[7],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_1[0]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3)
|
|
^ s2_folded_gh_dup_1_hist_3_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_2_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_2_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {s2_folded_gh_dup_1_hist_2_folded_hist[6:0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0
|
|
^ (s2_last_br_num_oh_dup_1[0]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_2_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {s2_folded_gh_dup_1_hist_2_folded_hist[5:0],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_2_folded_hist[7],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_1[0]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3)
|
|
^ s2_folded_gh_dup_1_hist_2_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_1_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_1_folded_hist : 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {s2_folded_gh_dup_1_hist_1_folded_hist[9:2],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_1_folded_hist[1],
|
|
s2_folded_gh_dup_1_hist_1_folded_hist[0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0
|
|
^ s2_folded_gh_dup_1_hist_1_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {s2_folded_gh_dup_1_hist_1_folded_hist[8:2],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_1_hist_1_folded_hist[1],
|
|
(s2_last_br_num_oh_dup_1[0] & s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_1[1]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2
|
|
| s2_last_br_num_oh_dup_1[2]
|
|
& s2_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3)
|
|
^ s2_folded_gh_dup_1_hist_1_folded_hist[0],
|
|
s2_folded_gh_dup_1_hist_1_folded_hist[10],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1
|
|
^ s2_folded_gh_dup_1_hist_1_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_0_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_1_0 ? s2_folded_gh_dup_1_hist_0_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_1
|
|
? {s2_folded_gh_dup_1_hist_0_folded_hist[6:0],
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_0}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_1_2
|
|
? {s2_folded_gh_dup_1_hist_0_folded_hist[5:0],
|
|
1'h0,
|
|
_predictors_io_out_s2_full_pred_1_br_taken_mask_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.s1_FGH_sel
|
|
(s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1
|
|
& ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_FGH_src_hist_17_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_17_folded_hist : 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_17_folded_hist[9],
|
|
s1_folded_gh_dup_1_hist_17_folded_hist[8:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0
|
|
^ s1_folded_gh_dup_1_hist_17_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3)
|
|
^ s1_folded_gh_dup_1_hist_17_folded_hist[8],
|
|
s1_folded_gh_dup_1_hist_17_folded_hist[7:0],
|
|
s1_folded_gh_dup_1_hist_17_folded_hist[10],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1
|
|
^ (s1_last_br_num_oh_dup_1[0]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_17_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_16_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_16_folded_hist : 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {s1_folded_gh_dup_1_hist_16_folded_hist[9],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_16_folded_hist[8],
|
|
s1_folded_gh_dup_1_hist_16_folded_hist[7:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0
|
|
^ s1_folded_gh_dup_1_hist_16_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_16_folded_hist[8],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3)
|
|
^ s1_folded_gh_dup_1_hist_16_folded_hist[7],
|
|
s1_folded_gh_dup_1_hist_16_folded_hist[6:0],
|
|
s1_folded_gh_dup_1_hist_16_folded_hist[10],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1
|
|
^ s1_folded_gh_dup_1_hist_16_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_15_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_15_folded_hist : 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_15_folded_hist[5],
|
|
s1_folded_gh_dup_1_hist_15_folded_hist[4:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0
|
|
^ s1_folded_gh_dup_1_hist_15_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3)
|
|
^ s1_folded_gh_dup_1_hist_15_folded_hist[4],
|
|
s1_folded_gh_dup_1_hist_15_folded_hist[3:0],
|
|
s1_folded_gh_dup_1_hist_15_folded_hist[6],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1
|
|
^ (s1_last_br_num_oh_dup_1[0]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_15_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_14_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0
|
|
? {s1_folded_gh_dup_1_hist_14_folded_hist[7:1],
|
|
s1_folded_gh_dup_1_hist_14_folded_hist[0]
|
|
| _s1_possible_predicted_fhs_dup_T_271}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {s1_folded_gh_dup_1_hist_14_folded_hist[6:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {s1_folded_gh_dup_1_hist_14_folded_hist[5:0],
|
|
1'h0,
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97
|
|
.s1_FGH_src_hist_13_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_13_folded_hist : 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {s1_folded_gh_dup_1_hist_13_folded_hist[7:4],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_13_folded_hist[3],
|
|
s1_folded_gh_dup_1_hist_13_folded_hist[2:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0
|
|
^ s1_folded_gh_dup_1_hist_13_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {s1_folded_gh_dup_1_hist_13_folded_hist[6:4],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_13_folded_hist[3],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3)
|
|
^ s1_folded_gh_dup_1_hist_13_folded_hist[2],
|
|
s1_folded_gh_dup_1_hist_13_folded_hist[1:0],
|
|
s1_folded_gh_dup_1_hist_13_folded_hist[8],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1
|
|
^ s1_folded_gh_dup_1_hist_13_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_12_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0
|
|
? {s1_folded_gh_dup_1_hist_12_folded_hist[3:1],
|
|
s1_folded_gh_dup_1_hist_12_folded_hist[0]
|
|
| _s1_possible_predicted_fhs_dup_T_271}
|
|
: 4'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {s1_folded_gh_dup_1_hist_12_folded_hist[2:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0}
|
|
: 4'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {s1_folded_gh_dup_1_hist_12_folded_hist[1:0],
|
|
1'h0,
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1}
|
|
: 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97
|
|
.s1_FGH_src_hist_11_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_11_folded_hist : 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {s1_folded_gh_dup_1_hist_11_folded_hist[6:2],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_11_folded_hist[1],
|
|
s1_folded_gh_dup_1_hist_11_folded_hist[0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0
|
|
^ s1_folded_gh_dup_1_hist_11_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {s1_folded_gh_dup_1_hist_11_folded_hist[5:2],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_11_folded_hist[1],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3)
|
|
^ s1_folded_gh_dup_1_hist_11_folded_hist[0],
|
|
s1_folded_gh_dup_1_hist_11_folded_hist[7],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1
|
|
^ s1_folded_gh_dup_1_hist_11_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_10_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_10_folded_hist : 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {s1_folded_gh_dup_1_hist_10_folded_hist[7:5],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_10_folded_hist[4],
|
|
s1_folded_gh_dup_1_hist_10_folded_hist[3:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0
|
|
^ s1_folded_gh_dup_1_hist_10_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {s1_folded_gh_dup_1_hist_10_folded_hist[6:5],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_10_folded_hist[4],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3)
|
|
^ s1_folded_gh_dup_1_hist_10_folded_hist[3],
|
|
s1_folded_gh_dup_1_hist_10_folded_hist[2:0],
|
|
s1_folded_gh_dup_1_hist_10_folded_hist[8],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1
|
|
^ s1_folded_gh_dup_1_hist_10_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_9_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_9_folded_hist : 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {s1_folded_gh_dup_1_hist_9_folded_hist[5:4],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_9_folded_hist[3],
|
|
s1_folded_gh_dup_1_hist_9_folded_hist[2:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0
|
|
^ s1_folded_gh_dup_1_hist_9_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {s1_folded_gh_dup_1_hist_9_folded_hist[4],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_9_folded_hist[3],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3)
|
|
^ s1_folded_gh_dup_1_hist_9_folded_hist[2],
|
|
s1_folded_gh_dup_1_hist_9_folded_hist[1:0],
|
|
s1_folded_gh_dup_1_hist_9_folded_hist[6],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1
|
|
^ s1_folded_gh_dup_1_hist_9_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_8_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_8_folded_hist : 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_8_folded_hist[6],
|
|
s1_folded_gh_dup_1_hist_8_folded_hist[5:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0
|
|
^ s1_folded_gh_dup_1_hist_8_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3)
|
|
^ s1_folded_gh_dup_1_hist_8_folded_hist[5],
|
|
s1_folded_gh_dup_1_hist_8_folded_hist[4:0],
|
|
s1_folded_gh_dup_1_hist_8_folded_hist[7],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1
|
|
^ (s1_last_br_num_oh_dup_1[0]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_8_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_7_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_7_folded_hist : 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {s1_folded_gh_dup_1_hist_7_folded_hist[5:1],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_7_folded_hist[0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0
|
|
^ s1_folded_gh_dup_1_hist_7_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {s1_folded_gh_dup_1_hist_7_folded_hist[4:1],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_7_folded_hist[0],
|
|
1'h0,
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1
|
|
^ s1_folded_gh_dup_1_hist_7_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_6_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_6_folded_hist : 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {s1_folded_gh_dup_1_hist_6_folded_hist[7],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_6_folded_hist[6],
|
|
s1_folded_gh_dup_1_hist_6_folded_hist[5:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0
|
|
^ s1_folded_gh_dup_1_hist_6_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_6_folded_hist[6],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3)
|
|
^ s1_folded_gh_dup_1_hist_6_folded_hist[5],
|
|
s1_folded_gh_dup_1_hist_6_folded_hist[4:0],
|
|
s1_folded_gh_dup_1_hist_6_folded_hist[8],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1
|
|
^ s1_folded_gh_dup_1_hist_6_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_5_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_5_folded_hist : 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {s1_folded_gh_dup_1_hist_5_folded_hist[5:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0
|
|
^ (s1_last_br_num_oh_dup_1[0]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_5_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {s1_folded_gh_dup_1_hist_5_folded_hist[4:0],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_5_folded_hist[6],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1
|
|
^ (s1_last_br_num_oh_dup_1[0]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3)
|
|
^ s1_folded_gh_dup_1_hist_5_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_4_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_4_folded_hist : 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {s1_folded_gh_dup_1_hist_4_folded_hist[6:5],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_4_folded_hist[4],
|
|
s1_folded_gh_dup_1_hist_4_folded_hist[3:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0
|
|
^ s1_folded_gh_dup_1_hist_4_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {s1_folded_gh_dup_1_hist_4_folded_hist[5],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_4_folded_hist[4],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3)
|
|
^ s1_folded_gh_dup_1_hist_4_folded_hist[3],
|
|
s1_folded_gh_dup_1_hist_4_folded_hist[2:0],
|
|
s1_folded_gh_dup_1_hist_4_folded_hist[7],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1
|
|
^ s1_folded_gh_dup_1_hist_4_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_3_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_3_folded_hist : 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {s1_folded_gh_dup_1_hist_3_folded_hist[6:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0
|
|
^ (s1_last_br_num_oh_dup_1[0]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_3_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {s1_folded_gh_dup_1_hist_3_folded_hist[5:0],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_3_folded_hist[7],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1
|
|
^ (s1_last_br_num_oh_dup_1[0]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3)
|
|
^ s1_folded_gh_dup_1_hist_3_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_2_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_2_folded_hist : 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {s1_folded_gh_dup_1_hist_2_folded_hist[6:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0
|
|
^ (s1_last_br_num_oh_dup_1[0]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_2_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {s1_folded_gh_dup_1_hist_2_folded_hist[5:0],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_2_folded_hist[7],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1
|
|
^ (s1_last_br_num_oh_dup_1[0]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3)
|
|
^ s1_folded_gh_dup_1_hist_2_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_1_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0 ? s1_folded_gh_dup_1_hist_1_folded_hist : 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {s1_folded_gh_dup_1_hist_1_folded_hist[9:2],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_1_folded_hist[1],
|
|
s1_folded_gh_dup_1_hist_1_folded_hist[0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0
|
|
^ s1_folded_gh_dup_1_hist_1_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {s1_folded_gh_dup_1_hist_1_folded_hist[8:2],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_1_hist_1_folded_hist[1],
|
|
(s1_last_br_num_oh_dup_1[0] & s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_1[1]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2
|
|
| s1_last_br_num_oh_dup_1[2]
|
|
& s1_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3)
|
|
^ s1_folded_gh_dup_1_hist_1_folded_hist[0],
|
|
s1_folded_gh_dup_1_hist_1_folded_hist[10],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1
|
|
^ s1_folded_gh_dup_1_hist_1_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_0_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_1_0
|
|
? {s1_folded_gh_dup_1_hist_0_folded_hist[7:1],
|
|
s1_folded_gh_dup_1_hist_0_folded_hist[0]
|
|
| _s1_possible_predicted_fhs_dup_T_271}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_1
|
|
? {s1_folded_gh_dup_1_hist_0_folded_hist[6:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_4_0}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_1_2
|
|
? {s1_folded_gh_dup_1_hist_0_folded_hist[5:0],
|
|
1'h0,
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_5_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97
|
|
.s3_FGH_sel (s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_FGH_src_hist_17_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_17_folded_hist : 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_17_folded_hist[9],
|
|
s3_folded_gh_dup_1_hist_17_folded_hist[8:0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0
|
|
^ s3_folded_gh_dup_1_hist_17_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3)
|
|
^ s3_folded_gh_dup_1_hist_17_folded_hist[8],
|
|
s3_folded_gh_dup_1_hist_17_folded_hist[7:0],
|
|
s3_folded_gh_dup_1_hist_17_folded_hist[10],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_1[0]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_17_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_16_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_16_folded_hist : 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {s3_folded_gh_dup_1_hist_16_folded_hist[9],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_16_folded_hist[8],
|
|
s3_folded_gh_dup_1_hist_16_folded_hist[7:0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0
|
|
^ s3_folded_gh_dup_1_hist_16_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_16_folded_hist[8],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3)
|
|
^ s3_folded_gh_dup_1_hist_16_folded_hist[7],
|
|
s3_folded_gh_dup_1_hist_16_folded_hist[6:0],
|
|
s3_folded_gh_dup_1_hist_16_folded_hist[10],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1
|
|
^ s3_folded_gh_dup_1_hist_16_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_15_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_15_folded_hist : 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_15_folded_hist[5],
|
|
s3_folded_gh_dup_1_hist_15_folded_hist[4:0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0
|
|
^ s3_folded_gh_dup_1_hist_15_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3)
|
|
^ s3_folded_gh_dup_1_hist_15_folded_hist[4],
|
|
s3_folded_gh_dup_1_hist_15_folded_hist[3:0],
|
|
s3_folded_gh_dup_1_hist_15_folded_hist[6],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_1[0]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_15_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_14_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_14_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {s3_folded_gh_dup_1_hist_14_folded_hist[6:0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {s3_folded_gh_dup_1_hist_14_folded_hist[5:0],
|
|
1'h0,
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.s3_FGH_src_hist_13_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_13_folded_hist : 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {s3_folded_gh_dup_1_hist_13_folded_hist[7:4],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_13_folded_hist[3],
|
|
s3_folded_gh_dup_1_hist_13_folded_hist[2:0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0
|
|
^ s3_folded_gh_dup_1_hist_13_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {s3_folded_gh_dup_1_hist_13_folded_hist[6:4],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_13_folded_hist[3],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3)
|
|
^ s3_folded_gh_dup_1_hist_13_folded_hist[2],
|
|
s3_folded_gh_dup_1_hist_13_folded_hist[1:0],
|
|
s3_folded_gh_dup_1_hist_13_folded_hist[8],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1
|
|
^ s3_folded_gh_dup_1_hist_13_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_12_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_12_folded_hist : 4'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {s3_folded_gh_dup_1_hist_12_folded_hist[2:0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0}
|
|
: 4'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {s3_folded_gh_dup_1_hist_12_folded_hist[1:0],
|
|
1'h0,
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1}
|
|
: 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.s3_FGH_src_hist_11_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_11_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {s3_folded_gh_dup_1_hist_11_folded_hist[6:2],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_11_folded_hist[1],
|
|
s3_folded_gh_dup_1_hist_11_folded_hist[0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0
|
|
^ s3_folded_gh_dup_1_hist_11_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {s3_folded_gh_dup_1_hist_11_folded_hist[5:2],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_11_folded_hist[1],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_1
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_2
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_0_bits_3)
|
|
^ s3_folded_gh_dup_1_hist_11_folded_hist[0],
|
|
s3_folded_gh_dup_1_hist_11_folded_hist[7],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1
|
|
^ s3_folded_gh_dup_1_hist_11_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_10_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_10_folded_hist : 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {s3_folded_gh_dup_1_hist_10_folded_hist[7:5],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_10_folded_hist[4],
|
|
s3_folded_gh_dup_1_hist_10_folded_hist[3:0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0
|
|
^ s3_folded_gh_dup_1_hist_10_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {s3_folded_gh_dup_1_hist_10_folded_hist[6:5],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_10_folded_hist[4],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3)
|
|
^ s3_folded_gh_dup_1_hist_10_folded_hist[3],
|
|
s3_folded_gh_dup_1_hist_10_folded_hist[2:0],
|
|
s3_folded_gh_dup_1_hist_10_folded_hist[8],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1
|
|
^ s3_folded_gh_dup_1_hist_10_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_9_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_9_folded_hist : 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {s3_folded_gh_dup_1_hist_9_folded_hist[5:4],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_9_folded_hist[3],
|
|
s3_folded_gh_dup_1_hist_9_folded_hist[2:0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0
|
|
^ s3_folded_gh_dup_1_hist_9_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {s3_folded_gh_dup_1_hist_9_folded_hist[4],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_9_folded_hist[3],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3)
|
|
^ s3_folded_gh_dup_1_hist_9_folded_hist[2],
|
|
s3_folded_gh_dup_1_hist_9_folded_hist[1:0],
|
|
s3_folded_gh_dup_1_hist_9_folded_hist[6],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1
|
|
^ s3_folded_gh_dup_1_hist_9_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_8_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_8_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_8_folded_hist[6],
|
|
s3_folded_gh_dup_1_hist_8_folded_hist[5:0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0
|
|
^ s3_folded_gh_dup_1_hist_8_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3)
|
|
^ s3_folded_gh_dup_1_hist_8_folded_hist[5],
|
|
s3_folded_gh_dup_1_hist_8_folded_hist[4:0],
|
|
s3_folded_gh_dup_1_hist_8_folded_hist[7],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_1[0]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_8_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_7_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_7_folded_hist : 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {s3_folded_gh_dup_1_hist_7_folded_hist[5:1],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_7_folded_hist[0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0
|
|
^ s3_folded_gh_dup_1_hist_7_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {s3_folded_gh_dup_1_hist_7_folded_hist[4:1],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_4_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_7_folded_hist[0],
|
|
1'h0,
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1
|
|
^ s3_folded_gh_dup_1_hist_7_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_6_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_6_folded_hist : 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {s3_folded_gh_dup_1_hist_6_folded_hist[7],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_6_folded_hist[6],
|
|
s3_folded_gh_dup_1_hist_6_folded_hist[5:0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0
|
|
^ s3_folded_gh_dup_1_hist_6_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_6_folded_hist[6],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3)
|
|
^ s3_folded_gh_dup_1_hist_6_folded_hist[5],
|
|
s3_folded_gh_dup_1_hist_6_folded_hist[4:0],
|
|
s3_folded_gh_dup_1_hist_6_folded_hist[8],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1
|
|
^ s3_folded_gh_dup_1_hist_6_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_5_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_5_folded_hist : 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {s3_folded_gh_dup_1_hist_5_folded_hist[5:0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0
|
|
^ (s3_last_br_num_oh_dup_1[0]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_5_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {s3_folded_gh_dup_1_hist_5_folded_hist[4:0],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_5_folded_hist[6],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_1[0]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_2
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_5_bits_3)
|
|
^ s3_folded_gh_dup_1_hist_5_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_4_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_4_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {s3_folded_gh_dup_1_hist_4_folded_hist[6:5],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_4_folded_hist[4],
|
|
s3_folded_gh_dup_1_hist_4_folded_hist[3:0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0
|
|
^ s3_folded_gh_dup_1_hist_4_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {s3_folded_gh_dup_1_hist_4_folded_hist[5],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_4_folded_hist[4],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3)
|
|
^ s3_folded_gh_dup_1_hist_4_folded_hist[3],
|
|
s3_folded_gh_dup_1_hist_4_folded_hist[2:0],
|
|
s3_folded_gh_dup_1_hist_4_folded_hist[7],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1
|
|
^ s3_folded_gh_dup_1_hist_4_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_3_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_3_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {s3_folded_gh_dup_1_hist_3_folded_hist[6:0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0
|
|
^ (s3_last_br_num_oh_dup_1[0]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_3_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {s3_folded_gh_dup_1_hist_3_folded_hist[5:0],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_3_folded_hist[7],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_1[0]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_2
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_2_bits_3)
|
|
^ s3_folded_gh_dup_1_hist_3_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_2_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_2_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {s3_folded_gh_dup_1_hist_2_folded_hist[6:0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0
|
|
^ (s3_last_br_num_oh_dup_1[0]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_2_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {s3_folded_gh_dup_1_hist_2_folded_hist[5:0],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_2_folded_hist[7],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_1[0]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_2
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_3_bits_3)
|
|
^ s3_folded_gh_dup_1_hist_2_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_1_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_1_folded_hist : 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {s3_folded_gh_dup_1_hist_1_folded_hist[9:2],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_1_folded_hist[1],
|
|
s3_folded_gh_dup_1_hist_1_folded_hist[0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0
|
|
^ s3_folded_gh_dup_1_hist_1_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {s3_folded_gh_dup_1_hist_1_folded_hist[8:2],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_1_hist_1_folded_hist[1],
|
|
(s3_last_br_num_oh_dup_1[0] & s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_1[1]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_2
|
|
| s3_last_br_num_oh_dup_1[2]
|
|
& s3_ahead_fh_oldest_bits_dup_1_afhob_1_bits_3)
|
|
^ s3_folded_gh_dup_1_hist_1_folded_hist[0],
|
|
s3_folded_gh_dup_1_hist_1_folded_hist[10],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1
|
|
^ s3_folded_gh_dup_1_hist_1_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_0_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_1_0 ? s3_folded_gh_dup_1_hist_0_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_1
|
|
? {s3_folded_gh_dup_1_hist_0_folded_hist[6:0],
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_0}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_1_2
|
|
? {s3_folded_gh_dup_1_hist_0_folded_hist[5:0],
|
|
1'h0,
|
|
_predictors_io_out_s3_full_pred_1_br_taken_mask_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.redirect_FGHT_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.redirect_FGHT_src_hist_17_folded_hist (_GEN_45[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_16_folded_hist (_GEN_46[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_15_folded_hist (_GEN_47[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_14_folded_hist (_GEN_48[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_13_folded_hist (_GEN_49[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_12_folded_hist (_GEN_50[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_11_folded_hist (_GEN_51[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_10_folded_hist (_GEN_52[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_9_folded_hist (_GEN_53[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_8_folded_hist (_GEN_54[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_7_folded_hist (_GEN_55[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_6_folded_hist (_GEN_56[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_5_folded_hist (_GEN_57[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_4_folded_hist (_GEN_58[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_3_folded_hist (_GEN_59[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_2_folded_hist (_GEN_60[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_1_folded_hist (_GEN_61[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_0_folded_hist (_GEN_62[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.stallFGH_src_hist_17_folded_hist (s0_folded_gh_reg_dup_1_hist_17_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_16_folded_hist (s0_folded_gh_reg_dup_1_hist_16_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_15_folded_hist (s0_folded_gh_reg_dup_1_hist_15_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_14_folded_hist (s0_folded_gh_reg_dup_1_hist_14_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_13_folded_hist (s0_folded_gh_reg_dup_1_hist_13_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_12_folded_hist (s0_folded_gh_reg_dup_1_hist_12_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_11_folded_hist (s0_folded_gh_reg_dup_1_hist_11_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_10_folded_hist (s0_folded_gh_reg_dup_1_hist_10_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_9_folded_hist (s0_folded_gh_reg_dup_1_hist_9_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_8_folded_hist (s0_folded_gh_reg_dup_1_hist_8_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_7_folded_hist (s0_folded_gh_reg_dup_1_hist_7_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_6_folded_hist (s0_folded_gh_reg_dup_1_hist_6_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_5_folded_hist (s0_folded_gh_reg_dup_1_hist_5_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_4_folded_hist (s0_folded_gh_reg_dup_1_hist_4_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_3_folded_hist (s0_folded_gh_reg_dup_1_hist_3_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_2_folded_hist (s0_folded_gh_reg_dup_1_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_1_folded_hist (s0_folded_gh_reg_dup_1_hist_1_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_0_folded_hist (s0_folded_gh_reg_dup_1_hist_0_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.out_res_hist_17_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_17_folded_hist),
|
|
.out_res_hist_16_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_16_folded_hist),
|
|
.out_res_hist_15_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_15_folded_hist),
|
|
.out_res_hist_14_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_14_folded_hist),
|
|
.out_res_hist_13_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_13_folded_hist),
|
|
.out_res_hist_12_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_12_folded_hist),
|
|
.out_res_hist_11_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_11_folded_hist),
|
|
.out_res_hist_10_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_10_folded_hist),
|
|
.out_res_hist_9_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_9_folded_hist),
|
|
.out_res_hist_8_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_8_folded_hist),
|
|
.out_res_hist_7_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_7_folded_hist),
|
|
.out_res_hist_6_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_6_folded_hist),
|
|
.out_res_hist_5_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_5_folded_hist),
|
|
.out_res_hist_4_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_4_folded_hist),
|
|
.out_res_hist_3_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_3_folded_hist),
|
|
.out_res_hist_2_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_2_folded_hist),
|
|
.out_res_hist_1_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_1_folded_hist),
|
|
.out_res_hist_0_folded_hist
|
|
(_s0_folded_gh_dup_1_ppm_out_res_hist_0_folded_hist)
|
|
);
|
|
PriorityMuxModule_4 s0_folded_gh_dup_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_FGH_sel
|
|
(s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_FGH_src_hist_17_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_17_folded_hist : 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_17_folded_hist[9],
|
|
s2_folded_gh_dup_2_hist_17_folded_hist[8:0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0
|
|
^ s2_folded_gh_dup_2_hist_17_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3)
|
|
^ s2_folded_gh_dup_2_hist_17_folded_hist[8],
|
|
s2_folded_gh_dup_2_hist_17_folded_hist[7:0],
|
|
s2_folded_gh_dup_2_hist_17_folded_hist[10],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_2[0]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_17_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_16_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_16_folded_hist : 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {s2_folded_gh_dup_2_hist_16_folded_hist[9],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_16_folded_hist[8],
|
|
s2_folded_gh_dup_2_hist_16_folded_hist[7:0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0
|
|
^ s2_folded_gh_dup_2_hist_16_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_16_folded_hist[8],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3)
|
|
^ s2_folded_gh_dup_2_hist_16_folded_hist[7],
|
|
s2_folded_gh_dup_2_hist_16_folded_hist[6:0],
|
|
s2_folded_gh_dup_2_hist_16_folded_hist[10],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1
|
|
^ s2_folded_gh_dup_2_hist_16_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_15_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_15_folded_hist : 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_15_folded_hist[5],
|
|
s2_folded_gh_dup_2_hist_15_folded_hist[4:0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0
|
|
^ s2_folded_gh_dup_2_hist_15_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3)
|
|
^ s2_folded_gh_dup_2_hist_15_folded_hist[4],
|
|
s2_folded_gh_dup_2_hist_15_folded_hist[3:0],
|
|
s2_folded_gh_dup_2_hist_15_folded_hist[6],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_2[0]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_15_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_14_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_14_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {s2_folded_gh_dup_2_hist_14_folded_hist[6:0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {s2_folded_gh_dup_2_hist_14_folded_hist[5:0],
|
|
1'h0,
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.s2_FGH_src_hist_13_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_13_folded_hist : 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {s2_folded_gh_dup_2_hist_13_folded_hist[7:4],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_13_folded_hist[3],
|
|
s2_folded_gh_dup_2_hist_13_folded_hist[2:0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0
|
|
^ s2_folded_gh_dup_2_hist_13_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {s2_folded_gh_dup_2_hist_13_folded_hist[6:4],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_13_folded_hist[3],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3)
|
|
^ s2_folded_gh_dup_2_hist_13_folded_hist[2],
|
|
s2_folded_gh_dup_2_hist_13_folded_hist[1:0],
|
|
s2_folded_gh_dup_2_hist_13_folded_hist[8],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1
|
|
^ s2_folded_gh_dup_2_hist_13_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_12_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_12_folded_hist : 4'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {s2_folded_gh_dup_2_hist_12_folded_hist[2:0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0}
|
|
: 4'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {s2_folded_gh_dup_2_hist_12_folded_hist[1:0],
|
|
1'h0,
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1}
|
|
: 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.s2_FGH_src_hist_11_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_11_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {s2_folded_gh_dup_2_hist_11_folded_hist[6:2],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_11_folded_hist[1],
|
|
s2_folded_gh_dup_2_hist_11_folded_hist[0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0
|
|
^ s2_folded_gh_dup_2_hist_11_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {s2_folded_gh_dup_2_hist_11_folded_hist[5:2],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_11_folded_hist[1],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3)
|
|
^ s2_folded_gh_dup_2_hist_11_folded_hist[0],
|
|
s2_folded_gh_dup_2_hist_11_folded_hist[7],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1
|
|
^ s2_folded_gh_dup_2_hist_11_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_10_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_10_folded_hist : 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {s2_folded_gh_dup_2_hist_10_folded_hist[7:5],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_10_folded_hist[4],
|
|
s2_folded_gh_dup_2_hist_10_folded_hist[3:0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0
|
|
^ s2_folded_gh_dup_2_hist_10_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {s2_folded_gh_dup_2_hist_10_folded_hist[6:5],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_10_folded_hist[4],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3)
|
|
^ s2_folded_gh_dup_2_hist_10_folded_hist[3],
|
|
s2_folded_gh_dup_2_hist_10_folded_hist[2:0],
|
|
s2_folded_gh_dup_2_hist_10_folded_hist[8],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1
|
|
^ s2_folded_gh_dup_2_hist_10_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_9_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_9_folded_hist : 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {s2_folded_gh_dup_2_hist_9_folded_hist[5:4],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_9_folded_hist[3],
|
|
s2_folded_gh_dup_2_hist_9_folded_hist[2:0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0
|
|
^ s2_folded_gh_dup_2_hist_9_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {s2_folded_gh_dup_2_hist_9_folded_hist[4],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_9_folded_hist[3],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3)
|
|
^ s2_folded_gh_dup_2_hist_9_folded_hist[2],
|
|
s2_folded_gh_dup_2_hist_9_folded_hist[1:0],
|
|
s2_folded_gh_dup_2_hist_9_folded_hist[6],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1
|
|
^ s2_folded_gh_dup_2_hist_9_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_8_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_8_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_8_folded_hist[6],
|
|
s2_folded_gh_dup_2_hist_8_folded_hist[5:0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0
|
|
^ s2_folded_gh_dup_2_hist_8_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3)
|
|
^ s2_folded_gh_dup_2_hist_8_folded_hist[5],
|
|
s2_folded_gh_dup_2_hist_8_folded_hist[4:0],
|
|
s2_folded_gh_dup_2_hist_8_folded_hist[7],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_2[0]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_8_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_7_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_7_folded_hist : 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {s2_folded_gh_dup_2_hist_7_folded_hist[5:1],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_7_folded_hist[0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0
|
|
^ s2_folded_gh_dup_2_hist_7_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {s2_folded_gh_dup_2_hist_7_folded_hist[4:1],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_7_folded_hist[0],
|
|
1'h0,
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1
|
|
^ s2_folded_gh_dup_2_hist_7_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_6_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_6_folded_hist : 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {s2_folded_gh_dup_2_hist_6_folded_hist[7],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_6_folded_hist[6],
|
|
s2_folded_gh_dup_2_hist_6_folded_hist[5:0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0
|
|
^ s2_folded_gh_dup_2_hist_6_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_6_folded_hist[6],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3)
|
|
^ s2_folded_gh_dup_2_hist_6_folded_hist[5],
|
|
s2_folded_gh_dup_2_hist_6_folded_hist[4:0],
|
|
s2_folded_gh_dup_2_hist_6_folded_hist[8],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1
|
|
^ s2_folded_gh_dup_2_hist_6_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_5_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_5_folded_hist : 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {s2_folded_gh_dup_2_hist_5_folded_hist[5:0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0
|
|
^ (s2_last_br_num_oh_dup_2[0]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_5_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {s2_folded_gh_dup_2_hist_5_folded_hist[4:0],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_5_folded_hist[6],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_2[0]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3)
|
|
^ s2_folded_gh_dup_2_hist_5_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_4_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_4_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {s2_folded_gh_dup_2_hist_4_folded_hist[6:5],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_4_folded_hist[4],
|
|
s2_folded_gh_dup_2_hist_4_folded_hist[3:0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0
|
|
^ s2_folded_gh_dup_2_hist_4_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {s2_folded_gh_dup_2_hist_4_folded_hist[5],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_4_folded_hist[4],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3)
|
|
^ s2_folded_gh_dup_2_hist_4_folded_hist[3],
|
|
s2_folded_gh_dup_2_hist_4_folded_hist[2:0],
|
|
s2_folded_gh_dup_2_hist_4_folded_hist[7],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1
|
|
^ s2_folded_gh_dup_2_hist_4_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_3_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_3_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {s2_folded_gh_dup_2_hist_3_folded_hist[6:0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0
|
|
^ (s2_last_br_num_oh_dup_2[0]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_3_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {s2_folded_gh_dup_2_hist_3_folded_hist[5:0],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_3_folded_hist[7],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_2[0]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3)
|
|
^ s2_folded_gh_dup_2_hist_3_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_2_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_2_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {s2_folded_gh_dup_2_hist_2_folded_hist[6:0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0
|
|
^ (s2_last_br_num_oh_dup_2[0]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_2_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {s2_folded_gh_dup_2_hist_2_folded_hist[5:0],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_2_folded_hist[7],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_2[0]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3)
|
|
^ s2_folded_gh_dup_2_hist_2_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_1_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_1_folded_hist : 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {s2_folded_gh_dup_2_hist_1_folded_hist[9:2],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_1_folded_hist[1],
|
|
s2_folded_gh_dup_2_hist_1_folded_hist[0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0
|
|
^ s2_folded_gh_dup_2_hist_1_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {s2_folded_gh_dup_2_hist_1_folded_hist[8:2],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_2_hist_1_folded_hist[1],
|
|
(s2_last_br_num_oh_dup_2[0] & s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_2[1]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2
|
|
| s2_last_br_num_oh_dup_2[2]
|
|
& s2_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3)
|
|
^ s2_folded_gh_dup_2_hist_1_folded_hist[0],
|
|
s2_folded_gh_dup_2_hist_1_folded_hist[10],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1
|
|
^ s2_folded_gh_dup_2_hist_1_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_0_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_2_0 ? s2_folded_gh_dup_2_hist_0_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_1
|
|
? {s2_folded_gh_dup_2_hist_0_folded_hist[6:0],
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_0}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_2_2
|
|
? {s2_folded_gh_dup_2_hist_0_folded_hist[5:0],
|
|
1'h0,
|
|
_predictors_io_out_s2_full_pred_2_br_taken_mask_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.s1_FGH_sel
|
|
(s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2
|
|
& ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_FGH_src_hist_17_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_17_folded_hist : 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_17_folded_hist[9],
|
|
s1_folded_gh_dup_2_hist_17_folded_hist[8:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0
|
|
^ s1_folded_gh_dup_2_hist_17_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3)
|
|
^ s1_folded_gh_dup_2_hist_17_folded_hist[8],
|
|
s1_folded_gh_dup_2_hist_17_folded_hist[7:0],
|
|
s1_folded_gh_dup_2_hist_17_folded_hist[10],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1
|
|
^ (s1_last_br_num_oh_dup_2[0]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_17_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_16_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_16_folded_hist : 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {s1_folded_gh_dup_2_hist_16_folded_hist[9],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_16_folded_hist[8],
|
|
s1_folded_gh_dup_2_hist_16_folded_hist[7:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0
|
|
^ s1_folded_gh_dup_2_hist_16_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_16_folded_hist[8],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3)
|
|
^ s1_folded_gh_dup_2_hist_16_folded_hist[7],
|
|
s1_folded_gh_dup_2_hist_16_folded_hist[6:0],
|
|
s1_folded_gh_dup_2_hist_16_folded_hist[10],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1
|
|
^ s1_folded_gh_dup_2_hist_16_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_15_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_15_folded_hist : 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_15_folded_hist[5],
|
|
s1_folded_gh_dup_2_hist_15_folded_hist[4:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0
|
|
^ s1_folded_gh_dup_2_hist_15_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3)
|
|
^ s1_folded_gh_dup_2_hist_15_folded_hist[4],
|
|
s1_folded_gh_dup_2_hist_15_folded_hist[3:0],
|
|
s1_folded_gh_dup_2_hist_15_folded_hist[6],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1
|
|
^ (s1_last_br_num_oh_dup_2[0]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_15_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_14_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0
|
|
? {s1_folded_gh_dup_2_hist_14_folded_hist[7:1],
|
|
s1_folded_gh_dup_2_hist_14_folded_hist[0]
|
|
| _s1_possible_predicted_fhs_dup_T_274}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {s1_folded_gh_dup_2_hist_14_folded_hist[6:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {s1_folded_gh_dup_2_hist_14_folded_hist[5:0],
|
|
1'h0,
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97
|
|
.s1_FGH_src_hist_13_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_13_folded_hist : 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {s1_folded_gh_dup_2_hist_13_folded_hist[7:4],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_13_folded_hist[3],
|
|
s1_folded_gh_dup_2_hist_13_folded_hist[2:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0
|
|
^ s1_folded_gh_dup_2_hist_13_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {s1_folded_gh_dup_2_hist_13_folded_hist[6:4],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_13_folded_hist[3],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3)
|
|
^ s1_folded_gh_dup_2_hist_13_folded_hist[2],
|
|
s1_folded_gh_dup_2_hist_13_folded_hist[1:0],
|
|
s1_folded_gh_dup_2_hist_13_folded_hist[8],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1
|
|
^ s1_folded_gh_dup_2_hist_13_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_12_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0
|
|
? {s1_folded_gh_dup_2_hist_12_folded_hist[3:1],
|
|
s1_folded_gh_dup_2_hist_12_folded_hist[0]
|
|
| _s1_possible_predicted_fhs_dup_T_274}
|
|
: 4'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {s1_folded_gh_dup_2_hist_12_folded_hist[2:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0}
|
|
: 4'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {s1_folded_gh_dup_2_hist_12_folded_hist[1:0],
|
|
1'h0,
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1}
|
|
: 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97
|
|
.s1_FGH_src_hist_11_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_11_folded_hist : 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {s1_folded_gh_dup_2_hist_11_folded_hist[6:2],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_11_folded_hist[1],
|
|
s1_folded_gh_dup_2_hist_11_folded_hist[0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0
|
|
^ s1_folded_gh_dup_2_hist_11_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {s1_folded_gh_dup_2_hist_11_folded_hist[5:2],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_11_folded_hist[1],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3)
|
|
^ s1_folded_gh_dup_2_hist_11_folded_hist[0],
|
|
s1_folded_gh_dup_2_hist_11_folded_hist[7],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1
|
|
^ s1_folded_gh_dup_2_hist_11_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_10_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_10_folded_hist : 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {s1_folded_gh_dup_2_hist_10_folded_hist[7:5],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_10_folded_hist[4],
|
|
s1_folded_gh_dup_2_hist_10_folded_hist[3:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0
|
|
^ s1_folded_gh_dup_2_hist_10_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {s1_folded_gh_dup_2_hist_10_folded_hist[6:5],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_10_folded_hist[4],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3)
|
|
^ s1_folded_gh_dup_2_hist_10_folded_hist[3],
|
|
s1_folded_gh_dup_2_hist_10_folded_hist[2:0],
|
|
s1_folded_gh_dup_2_hist_10_folded_hist[8],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1
|
|
^ s1_folded_gh_dup_2_hist_10_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_9_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_9_folded_hist : 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {s1_folded_gh_dup_2_hist_9_folded_hist[5:4],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_9_folded_hist[3],
|
|
s1_folded_gh_dup_2_hist_9_folded_hist[2:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0
|
|
^ s1_folded_gh_dup_2_hist_9_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {s1_folded_gh_dup_2_hist_9_folded_hist[4],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_9_folded_hist[3],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3)
|
|
^ s1_folded_gh_dup_2_hist_9_folded_hist[2],
|
|
s1_folded_gh_dup_2_hist_9_folded_hist[1:0],
|
|
s1_folded_gh_dup_2_hist_9_folded_hist[6],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1
|
|
^ s1_folded_gh_dup_2_hist_9_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_8_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_8_folded_hist : 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_8_folded_hist[6],
|
|
s1_folded_gh_dup_2_hist_8_folded_hist[5:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0
|
|
^ s1_folded_gh_dup_2_hist_8_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3)
|
|
^ s1_folded_gh_dup_2_hist_8_folded_hist[5],
|
|
s1_folded_gh_dup_2_hist_8_folded_hist[4:0],
|
|
s1_folded_gh_dup_2_hist_8_folded_hist[7],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1
|
|
^ (s1_last_br_num_oh_dup_2[0]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_8_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_7_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_7_folded_hist : 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {s1_folded_gh_dup_2_hist_7_folded_hist[5:1],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_7_folded_hist[0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0
|
|
^ s1_folded_gh_dup_2_hist_7_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {s1_folded_gh_dup_2_hist_7_folded_hist[4:1],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_7_folded_hist[0],
|
|
1'h0,
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1
|
|
^ s1_folded_gh_dup_2_hist_7_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_6_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_6_folded_hist : 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {s1_folded_gh_dup_2_hist_6_folded_hist[7],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_6_folded_hist[6],
|
|
s1_folded_gh_dup_2_hist_6_folded_hist[5:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0
|
|
^ s1_folded_gh_dup_2_hist_6_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_6_folded_hist[6],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3)
|
|
^ s1_folded_gh_dup_2_hist_6_folded_hist[5],
|
|
s1_folded_gh_dup_2_hist_6_folded_hist[4:0],
|
|
s1_folded_gh_dup_2_hist_6_folded_hist[8],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1
|
|
^ s1_folded_gh_dup_2_hist_6_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_5_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_5_folded_hist : 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {s1_folded_gh_dup_2_hist_5_folded_hist[5:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0
|
|
^ (s1_last_br_num_oh_dup_2[0]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_5_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {s1_folded_gh_dup_2_hist_5_folded_hist[4:0],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_5_folded_hist[6],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1
|
|
^ (s1_last_br_num_oh_dup_2[0]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3)
|
|
^ s1_folded_gh_dup_2_hist_5_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_4_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_4_folded_hist : 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {s1_folded_gh_dup_2_hist_4_folded_hist[6:5],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_4_folded_hist[4],
|
|
s1_folded_gh_dup_2_hist_4_folded_hist[3:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0
|
|
^ s1_folded_gh_dup_2_hist_4_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {s1_folded_gh_dup_2_hist_4_folded_hist[5],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_4_folded_hist[4],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3)
|
|
^ s1_folded_gh_dup_2_hist_4_folded_hist[3],
|
|
s1_folded_gh_dup_2_hist_4_folded_hist[2:0],
|
|
s1_folded_gh_dup_2_hist_4_folded_hist[7],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1
|
|
^ s1_folded_gh_dup_2_hist_4_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_3_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_3_folded_hist : 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {s1_folded_gh_dup_2_hist_3_folded_hist[6:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0
|
|
^ (s1_last_br_num_oh_dup_2[0]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_3_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {s1_folded_gh_dup_2_hist_3_folded_hist[5:0],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_3_folded_hist[7],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1
|
|
^ (s1_last_br_num_oh_dup_2[0]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3)
|
|
^ s1_folded_gh_dup_2_hist_3_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_2_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_2_folded_hist : 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {s1_folded_gh_dup_2_hist_2_folded_hist[6:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0
|
|
^ (s1_last_br_num_oh_dup_2[0]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_2_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {s1_folded_gh_dup_2_hist_2_folded_hist[5:0],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_2_folded_hist[7],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1
|
|
^ (s1_last_br_num_oh_dup_2[0]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3)
|
|
^ s1_folded_gh_dup_2_hist_2_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_1_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0 ? s1_folded_gh_dup_2_hist_1_folded_hist : 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {s1_folded_gh_dup_2_hist_1_folded_hist[9:2],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_1_folded_hist[1],
|
|
s1_folded_gh_dup_2_hist_1_folded_hist[0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0
|
|
^ s1_folded_gh_dup_2_hist_1_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {s1_folded_gh_dup_2_hist_1_folded_hist[8:2],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_2_hist_1_folded_hist[1],
|
|
(s1_last_br_num_oh_dup_2[0] & s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_2[1]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2
|
|
| s1_last_br_num_oh_dup_2[2]
|
|
& s1_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3)
|
|
^ s1_folded_gh_dup_2_hist_1_folded_hist[0],
|
|
s1_folded_gh_dup_2_hist_1_folded_hist[10],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1
|
|
^ s1_folded_gh_dup_2_hist_1_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_0_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_2_0
|
|
? {s1_folded_gh_dup_2_hist_0_folded_hist[7:1],
|
|
s1_folded_gh_dup_2_hist_0_folded_hist[0]
|
|
| _s1_possible_predicted_fhs_dup_T_274}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_1
|
|
? {s1_folded_gh_dup_2_hist_0_folded_hist[6:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_7_0}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_2_2
|
|
? {s1_folded_gh_dup_2_hist_0_folded_hist[5:0],
|
|
1'h0,
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_8_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97
|
|
.s3_FGH_sel (s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_FGH_src_hist_17_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_17_folded_hist : 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_17_folded_hist[9],
|
|
s3_folded_gh_dup_2_hist_17_folded_hist[8:0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0
|
|
^ s3_folded_gh_dup_2_hist_17_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3)
|
|
^ s3_folded_gh_dup_2_hist_17_folded_hist[8],
|
|
s3_folded_gh_dup_2_hist_17_folded_hist[7:0],
|
|
s3_folded_gh_dup_2_hist_17_folded_hist[10],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_2[0]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_17_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_16_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_16_folded_hist : 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {s3_folded_gh_dup_2_hist_16_folded_hist[9],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_16_folded_hist[8],
|
|
s3_folded_gh_dup_2_hist_16_folded_hist[7:0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0
|
|
^ s3_folded_gh_dup_2_hist_16_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_16_folded_hist[8],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3)
|
|
^ s3_folded_gh_dup_2_hist_16_folded_hist[7],
|
|
s3_folded_gh_dup_2_hist_16_folded_hist[6:0],
|
|
s3_folded_gh_dup_2_hist_16_folded_hist[10],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1
|
|
^ s3_folded_gh_dup_2_hist_16_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_15_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_15_folded_hist : 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_15_folded_hist[5],
|
|
s3_folded_gh_dup_2_hist_15_folded_hist[4:0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0
|
|
^ s3_folded_gh_dup_2_hist_15_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3)
|
|
^ s3_folded_gh_dup_2_hist_15_folded_hist[4],
|
|
s3_folded_gh_dup_2_hist_15_folded_hist[3:0],
|
|
s3_folded_gh_dup_2_hist_15_folded_hist[6],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_2[0]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_15_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_14_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_14_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {s3_folded_gh_dup_2_hist_14_folded_hist[6:0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {s3_folded_gh_dup_2_hist_14_folded_hist[5:0],
|
|
1'h0,
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.s3_FGH_src_hist_13_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_13_folded_hist : 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {s3_folded_gh_dup_2_hist_13_folded_hist[7:4],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_13_folded_hist[3],
|
|
s3_folded_gh_dup_2_hist_13_folded_hist[2:0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0
|
|
^ s3_folded_gh_dup_2_hist_13_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {s3_folded_gh_dup_2_hist_13_folded_hist[6:4],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_13_folded_hist[3],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3)
|
|
^ s3_folded_gh_dup_2_hist_13_folded_hist[2],
|
|
s3_folded_gh_dup_2_hist_13_folded_hist[1:0],
|
|
s3_folded_gh_dup_2_hist_13_folded_hist[8],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1
|
|
^ s3_folded_gh_dup_2_hist_13_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_12_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_12_folded_hist : 4'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {s3_folded_gh_dup_2_hist_12_folded_hist[2:0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0}
|
|
: 4'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {s3_folded_gh_dup_2_hist_12_folded_hist[1:0],
|
|
1'h0,
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1}
|
|
: 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.s3_FGH_src_hist_11_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_11_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {s3_folded_gh_dup_2_hist_11_folded_hist[6:2],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_11_folded_hist[1],
|
|
s3_folded_gh_dup_2_hist_11_folded_hist[0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0
|
|
^ s3_folded_gh_dup_2_hist_11_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {s3_folded_gh_dup_2_hist_11_folded_hist[5:2],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_11_folded_hist[1],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3)
|
|
^ s3_folded_gh_dup_2_hist_11_folded_hist[0],
|
|
s3_folded_gh_dup_2_hist_11_folded_hist[7],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1
|
|
^ s3_folded_gh_dup_2_hist_11_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_10_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_10_folded_hist : 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {s3_folded_gh_dup_2_hist_10_folded_hist[7:5],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_10_folded_hist[4],
|
|
s3_folded_gh_dup_2_hist_10_folded_hist[3:0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0
|
|
^ s3_folded_gh_dup_2_hist_10_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {s3_folded_gh_dup_2_hist_10_folded_hist[6:5],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_10_folded_hist[4],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3)
|
|
^ s3_folded_gh_dup_2_hist_10_folded_hist[3],
|
|
s3_folded_gh_dup_2_hist_10_folded_hist[2:0],
|
|
s3_folded_gh_dup_2_hist_10_folded_hist[8],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1
|
|
^ s3_folded_gh_dup_2_hist_10_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_9_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_9_folded_hist : 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {s3_folded_gh_dup_2_hist_9_folded_hist[5:4],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_9_folded_hist[3],
|
|
s3_folded_gh_dup_2_hist_9_folded_hist[2:0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0
|
|
^ s3_folded_gh_dup_2_hist_9_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {s3_folded_gh_dup_2_hist_9_folded_hist[4],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_9_folded_hist[3],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3)
|
|
^ s3_folded_gh_dup_2_hist_9_folded_hist[2],
|
|
s3_folded_gh_dup_2_hist_9_folded_hist[1:0],
|
|
s3_folded_gh_dup_2_hist_9_folded_hist[6],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1
|
|
^ s3_folded_gh_dup_2_hist_9_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_8_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_8_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_8_folded_hist[6],
|
|
s3_folded_gh_dup_2_hist_8_folded_hist[5:0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0
|
|
^ s3_folded_gh_dup_2_hist_8_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3)
|
|
^ s3_folded_gh_dup_2_hist_8_folded_hist[5],
|
|
s3_folded_gh_dup_2_hist_8_folded_hist[4:0],
|
|
s3_folded_gh_dup_2_hist_8_folded_hist[7],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_2[0]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_8_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_7_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_7_folded_hist : 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {s3_folded_gh_dup_2_hist_7_folded_hist[5:1],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_7_folded_hist[0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0
|
|
^ s3_folded_gh_dup_2_hist_7_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {s3_folded_gh_dup_2_hist_7_folded_hist[4:1],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_7_folded_hist[0],
|
|
1'h0,
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1
|
|
^ s3_folded_gh_dup_2_hist_7_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_6_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_6_folded_hist : 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {s3_folded_gh_dup_2_hist_6_folded_hist[7],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_6_folded_hist[6],
|
|
s3_folded_gh_dup_2_hist_6_folded_hist[5:0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0
|
|
^ s3_folded_gh_dup_2_hist_6_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_6_folded_hist[6],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3)
|
|
^ s3_folded_gh_dup_2_hist_6_folded_hist[5],
|
|
s3_folded_gh_dup_2_hist_6_folded_hist[4:0],
|
|
s3_folded_gh_dup_2_hist_6_folded_hist[8],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1
|
|
^ s3_folded_gh_dup_2_hist_6_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_5_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_5_folded_hist : 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {s3_folded_gh_dup_2_hist_5_folded_hist[5:0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0
|
|
^ (s3_last_br_num_oh_dup_2[0]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_5_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {s3_folded_gh_dup_2_hist_5_folded_hist[4:0],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_5_folded_hist[6],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_2[0]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3)
|
|
^ s3_folded_gh_dup_2_hist_5_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_4_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_4_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {s3_folded_gh_dup_2_hist_4_folded_hist[6:5],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_4_folded_hist[4],
|
|
s3_folded_gh_dup_2_hist_4_folded_hist[3:0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0
|
|
^ s3_folded_gh_dup_2_hist_4_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {s3_folded_gh_dup_2_hist_4_folded_hist[5],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_4_folded_hist[4],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3)
|
|
^ s3_folded_gh_dup_2_hist_4_folded_hist[3],
|
|
s3_folded_gh_dup_2_hist_4_folded_hist[2:0],
|
|
s3_folded_gh_dup_2_hist_4_folded_hist[7],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1
|
|
^ s3_folded_gh_dup_2_hist_4_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_3_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_3_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {s3_folded_gh_dup_2_hist_3_folded_hist[6:0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0
|
|
^ (s3_last_br_num_oh_dup_2[0]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_3_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {s3_folded_gh_dup_2_hist_3_folded_hist[5:0],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_3_folded_hist[7],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_2[0]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3)
|
|
^ s3_folded_gh_dup_2_hist_3_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_2_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_2_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {s3_folded_gh_dup_2_hist_2_folded_hist[6:0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0
|
|
^ (s3_last_br_num_oh_dup_2[0]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_2_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {s3_folded_gh_dup_2_hist_2_folded_hist[5:0],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_2_folded_hist[7],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_2[0]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3)
|
|
^ s3_folded_gh_dup_2_hist_2_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_1_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_1_folded_hist : 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {s3_folded_gh_dup_2_hist_1_folded_hist[9:2],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_1_folded_hist[1],
|
|
s3_folded_gh_dup_2_hist_1_folded_hist[0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0
|
|
^ s3_folded_gh_dup_2_hist_1_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {s3_folded_gh_dup_2_hist_1_folded_hist[8:2],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_2_hist_1_folded_hist[1],
|
|
(s3_last_br_num_oh_dup_2[0] & s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_2[1]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2
|
|
| s3_last_br_num_oh_dup_2[2]
|
|
& s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3)
|
|
^ s3_folded_gh_dup_2_hist_1_folded_hist[0],
|
|
s3_folded_gh_dup_2_hist_1_folded_hist[10],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1
|
|
^ s3_folded_gh_dup_2_hist_1_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_0_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_2_0 ? s3_folded_gh_dup_2_hist_0_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_1
|
|
? {s3_folded_gh_dup_2_hist_0_folded_hist[6:0],
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_0}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_2_2
|
|
? {s3_folded_gh_dup_2_hist_0_folded_hist[5:0],
|
|
1'h0,
|
|
_predictors_io_out_s3_full_pred_2_br_taken_mask_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.redirect_FGHT_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.redirect_FGHT_src_hist_17_folded_hist (_GEN_63[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_16_folded_hist (_GEN_64[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_15_folded_hist (_GEN_65[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_14_folded_hist (_GEN_66[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_13_folded_hist (_GEN_67[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_12_folded_hist (_GEN_68[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_11_folded_hist (_GEN_69[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_10_folded_hist (_GEN_70[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_9_folded_hist (_GEN_71[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_8_folded_hist (_GEN_72[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_7_folded_hist (_GEN_73[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_6_folded_hist (_GEN_74[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_5_folded_hist (_GEN_75[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_4_folded_hist (_GEN_76[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_3_folded_hist (_GEN_77[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_2_folded_hist (_GEN_78[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_1_folded_hist (_GEN_79[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_0_folded_hist (_GEN_80[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.stallFGH_src_hist_17_folded_hist (s0_folded_gh_reg_dup_2_hist_17_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_16_folded_hist (s0_folded_gh_reg_dup_2_hist_16_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_15_folded_hist (s0_folded_gh_reg_dup_2_hist_15_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_14_folded_hist (s0_folded_gh_reg_dup_2_hist_14_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_13_folded_hist (s0_folded_gh_reg_dup_2_hist_13_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_12_folded_hist (s0_folded_gh_reg_dup_2_hist_12_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_11_folded_hist (s0_folded_gh_reg_dup_2_hist_11_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_10_folded_hist (s0_folded_gh_reg_dup_2_hist_10_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_9_folded_hist (s0_folded_gh_reg_dup_2_hist_9_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_8_folded_hist (s0_folded_gh_reg_dup_2_hist_8_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_7_folded_hist (s0_folded_gh_reg_dup_2_hist_7_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_6_folded_hist (s0_folded_gh_reg_dup_2_hist_6_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_5_folded_hist (s0_folded_gh_reg_dup_2_hist_5_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_4_folded_hist (s0_folded_gh_reg_dup_2_hist_4_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_3_folded_hist (s0_folded_gh_reg_dup_2_hist_3_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_2_folded_hist (s0_folded_gh_reg_dup_2_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_1_folded_hist (s0_folded_gh_reg_dup_2_hist_1_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_0_folded_hist (s0_folded_gh_reg_dup_2_hist_0_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.out_res_hist_17_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_17_folded_hist),
|
|
.out_res_hist_16_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_16_folded_hist),
|
|
.out_res_hist_15_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_15_folded_hist),
|
|
.out_res_hist_14_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_14_folded_hist),
|
|
.out_res_hist_13_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_13_folded_hist),
|
|
.out_res_hist_12_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_12_folded_hist),
|
|
.out_res_hist_11_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_11_folded_hist),
|
|
.out_res_hist_10_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_10_folded_hist),
|
|
.out_res_hist_9_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_9_folded_hist),
|
|
.out_res_hist_8_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_8_folded_hist),
|
|
.out_res_hist_7_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_7_folded_hist),
|
|
.out_res_hist_6_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_6_folded_hist),
|
|
.out_res_hist_5_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_5_folded_hist),
|
|
.out_res_hist_4_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_4_folded_hist),
|
|
.out_res_hist_3_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_3_folded_hist),
|
|
.out_res_hist_2_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_2_folded_hist),
|
|
.out_res_hist_1_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_1_folded_hist),
|
|
.out_res_hist_0_folded_hist
|
|
(_s0_folded_gh_dup_2_ppm_out_res_hist_0_folded_hist)
|
|
);
|
|
PriorityMuxModule_4 s0_folded_gh_dup_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_FGH_sel
|
|
(s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_FGH_src_hist_17_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_17_folded_hist : 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_17_folded_hist[9],
|
|
s2_folded_gh_dup_3_hist_17_folded_hist[8:0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0
|
|
^ s2_folded_gh_dup_3_hist_17_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3)
|
|
^ s2_folded_gh_dup_3_hist_17_folded_hist[8],
|
|
s2_folded_gh_dup_3_hist_17_folded_hist[7:0],
|
|
s2_folded_gh_dup_3_hist_17_folded_hist[10],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_3[0]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_17_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_16_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_16_folded_hist : 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {s2_folded_gh_dup_3_hist_16_folded_hist[9],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_16_folded_hist[8],
|
|
s2_folded_gh_dup_3_hist_16_folded_hist[7:0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0
|
|
^ s2_folded_gh_dup_3_hist_16_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_16_folded_hist[8],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3)
|
|
^ s2_folded_gh_dup_3_hist_16_folded_hist[7],
|
|
s2_folded_gh_dup_3_hist_16_folded_hist[6:0],
|
|
s2_folded_gh_dup_3_hist_16_folded_hist[10],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1
|
|
^ s2_folded_gh_dup_3_hist_16_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_15_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_15_folded_hist : 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_15_folded_hist[5],
|
|
s2_folded_gh_dup_3_hist_15_folded_hist[4:0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0
|
|
^ s2_folded_gh_dup_3_hist_15_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3)
|
|
^ s2_folded_gh_dup_3_hist_15_folded_hist[4],
|
|
s2_folded_gh_dup_3_hist_15_folded_hist[3:0],
|
|
s2_folded_gh_dup_3_hist_15_folded_hist[6],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_3[0]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_15_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_14_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_14_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {s2_folded_gh_dup_3_hist_14_folded_hist[6:0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {s2_folded_gh_dup_3_hist_14_folded_hist[5:0],
|
|
1'h0,
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.s2_FGH_src_hist_13_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_13_folded_hist : 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {s2_folded_gh_dup_3_hist_13_folded_hist[7:4],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_13_folded_hist[3],
|
|
s2_folded_gh_dup_3_hist_13_folded_hist[2:0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0
|
|
^ s2_folded_gh_dup_3_hist_13_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {s2_folded_gh_dup_3_hist_13_folded_hist[6:4],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_13_folded_hist[3],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3)
|
|
^ s2_folded_gh_dup_3_hist_13_folded_hist[2],
|
|
s2_folded_gh_dup_3_hist_13_folded_hist[1:0],
|
|
s2_folded_gh_dup_3_hist_13_folded_hist[8],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1
|
|
^ s2_folded_gh_dup_3_hist_13_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_12_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_12_folded_hist : 4'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {s2_folded_gh_dup_3_hist_12_folded_hist[2:0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0}
|
|
: 4'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {s2_folded_gh_dup_3_hist_12_folded_hist[1:0],
|
|
1'h0,
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1}
|
|
: 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.s2_FGH_src_hist_11_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_11_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {s2_folded_gh_dup_3_hist_11_folded_hist[6:2],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_11_folded_hist[1],
|
|
s2_folded_gh_dup_3_hist_11_folded_hist[0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0
|
|
^ s2_folded_gh_dup_3_hist_11_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {s2_folded_gh_dup_3_hist_11_folded_hist[5:2],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_11_folded_hist[1],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3)
|
|
^ s2_folded_gh_dup_3_hist_11_folded_hist[0],
|
|
s2_folded_gh_dup_3_hist_11_folded_hist[7],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1
|
|
^ s2_folded_gh_dup_3_hist_11_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_10_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_10_folded_hist : 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {s2_folded_gh_dup_3_hist_10_folded_hist[7:5],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_10_folded_hist[4],
|
|
s2_folded_gh_dup_3_hist_10_folded_hist[3:0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0
|
|
^ s2_folded_gh_dup_3_hist_10_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {s2_folded_gh_dup_3_hist_10_folded_hist[6:5],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_10_folded_hist[4],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3)
|
|
^ s2_folded_gh_dup_3_hist_10_folded_hist[3],
|
|
s2_folded_gh_dup_3_hist_10_folded_hist[2:0],
|
|
s2_folded_gh_dup_3_hist_10_folded_hist[8],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1
|
|
^ s2_folded_gh_dup_3_hist_10_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_9_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_9_folded_hist : 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {s2_folded_gh_dup_3_hist_9_folded_hist[5:4],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_9_folded_hist[3],
|
|
s2_folded_gh_dup_3_hist_9_folded_hist[2:0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0
|
|
^ s2_folded_gh_dup_3_hist_9_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {s2_folded_gh_dup_3_hist_9_folded_hist[4],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_9_folded_hist[3],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3)
|
|
^ s2_folded_gh_dup_3_hist_9_folded_hist[2],
|
|
s2_folded_gh_dup_3_hist_9_folded_hist[1:0],
|
|
s2_folded_gh_dup_3_hist_9_folded_hist[6],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1
|
|
^ s2_folded_gh_dup_3_hist_9_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_8_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_8_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_8_folded_hist[6],
|
|
s2_folded_gh_dup_3_hist_8_folded_hist[5:0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0
|
|
^ s2_folded_gh_dup_3_hist_8_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3)
|
|
^ s2_folded_gh_dup_3_hist_8_folded_hist[5],
|
|
s2_folded_gh_dup_3_hist_8_folded_hist[4:0],
|
|
s2_folded_gh_dup_3_hist_8_folded_hist[7],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_3[0]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_8_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_7_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_7_folded_hist : 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {s2_folded_gh_dup_3_hist_7_folded_hist[5:1],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_7_folded_hist[0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0
|
|
^ s2_folded_gh_dup_3_hist_7_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {s2_folded_gh_dup_3_hist_7_folded_hist[4:1],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_7_folded_hist[0],
|
|
1'h0,
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1
|
|
^ s2_folded_gh_dup_3_hist_7_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_6_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_6_folded_hist : 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {s2_folded_gh_dup_3_hist_6_folded_hist[7],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_6_folded_hist[6],
|
|
s2_folded_gh_dup_3_hist_6_folded_hist[5:0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0
|
|
^ s2_folded_gh_dup_3_hist_6_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_6_folded_hist[6],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3)
|
|
^ s2_folded_gh_dup_3_hist_6_folded_hist[5],
|
|
s2_folded_gh_dup_3_hist_6_folded_hist[4:0],
|
|
s2_folded_gh_dup_3_hist_6_folded_hist[8],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1
|
|
^ s2_folded_gh_dup_3_hist_6_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_5_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_5_folded_hist : 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {s2_folded_gh_dup_3_hist_5_folded_hist[5:0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0
|
|
^ (s2_last_br_num_oh_dup_3[0]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_5_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {s2_folded_gh_dup_3_hist_5_folded_hist[4:0],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_5_folded_hist[6],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_3[0]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3)
|
|
^ s2_folded_gh_dup_3_hist_5_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_4_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_4_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {s2_folded_gh_dup_3_hist_4_folded_hist[6:5],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_4_folded_hist[4],
|
|
s2_folded_gh_dup_3_hist_4_folded_hist[3:0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0
|
|
^ s2_folded_gh_dup_3_hist_4_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {s2_folded_gh_dup_3_hist_4_folded_hist[5],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_4_folded_hist[4],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3)
|
|
^ s2_folded_gh_dup_3_hist_4_folded_hist[3],
|
|
s2_folded_gh_dup_3_hist_4_folded_hist[2:0],
|
|
s2_folded_gh_dup_3_hist_4_folded_hist[7],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1
|
|
^ s2_folded_gh_dup_3_hist_4_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_3_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_3_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {s2_folded_gh_dup_3_hist_3_folded_hist[6:0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0
|
|
^ (s2_last_br_num_oh_dup_3[0]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_3_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {s2_folded_gh_dup_3_hist_3_folded_hist[5:0],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_3_folded_hist[7],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_3[0]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3)
|
|
^ s2_folded_gh_dup_3_hist_3_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_2_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_2_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {s2_folded_gh_dup_3_hist_2_folded_hist[6:0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0
|
|
^ (s2_last_br_num_oh_dup_3[0]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_2_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {s2_folded_gh_dup_3_hist_2_folded_hist[5:0],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_2_folded_hist[7],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1
|
|
^ (s2_last_br_num_oh_dup_3[0]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3)
|
|
^ s2_folded_gh_dup_3_hist_2_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_1_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_1_folded_hist : 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {s2_folded_gh_dup_3_hist_1_folded_hist[9:2],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_1_folded_hist[1],
|
|
s2_folded_gh_dup_3_hist_1_folded_hist[0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0
|
|
^ s2_folded_gh_dup_3_hist_1_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {s2_folded_gh_dup_3_hist_1_folded_hist[8:2],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s2_folded_gh_dup_3_hist_1_folded_hist[1],
|
|
(s2_last_br_num_oh_dup_3[0] & s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s2_last_br_num_oh_dup_3[1]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2
|
|
| s2_last_br_num_oh_dup_3[2]
|
|
& s2_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3)
|
|
^ s2_folded_gh_dup_3_hist_1_folded_hist[0],
|
|
s2_folded_gh_dup_3_hist_1_folded_hist[10],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1
|
|
^ s2_folded_gh_dup_3_hist_1_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :287:35, :293:40, :299:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s2_FGH_src_hist_0_folded_hist
|
|
((_s2_predicted_fh_dup_WIRE_56_3_0 ? s2_folded_gh_dup_3_hist_0_folded_hist : 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_1
|
|
? {s2_folded_gh_dup_3_hist_0_folded_hist[6:0],
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0}
|
|
: 8'h0)
|
|
| (_s2_predicted_fh_dup_WIRE_56_3_2
|
|
? {s2_folded_gh_dup_3_hist_0_folded_hist[5:0],
|
|
1'h0,
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :287:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.s1_FGH_sel
|
|
(s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3
|
|
& ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_FGH_src_hist_17_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_17_folded_hist : 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_17_folded_hist[9],
|
|
s1_folded_gh_dup_3_hist_17_folded_hist[8:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0
|
|
^ s1_folded_gh_dup_3_hist_17_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3)
|
|
^ s1_folded_gh_dup_3_hist_17_folded_hist[8],
|
|
s1_folded_gh_dup_3_hist_17_folded_hist[7:0],
|
|
s1_folded_gh_dup_3_hist_17_folded_hist[10],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (s1_last_br_num_oh_dup_3[0]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_17_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_16_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_16_folded_hist : 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {s1_folded_gh_dup_3_hist_16_folded_hist[9],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_16_folded_hist[8],
|
|
s1_folded_gh_dup_3_hist_16_folded_hist[7:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0
|
|
^ s1_folded_gh_dup_3_hist_16_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_16_folded_hist[8],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3)
|
|
^ s1_folded_gh_dup_3_hist_16_folded_hist[7],
|
|
s1_folded_gh_dup_3_hist_16_folded_hist[6:0],
|
|
s1_folded_gh_dup_3_hist_16_folded_hist[10],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ s1_folded_gh_dup_3_hist_16_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_15_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_15_folded_hist : 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_15_folded_hist[5],
|
|
s1_folded_gh_dup_3_hist_15_folded_hist[4:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0
|
|
^ s1_folded_gh_dup_3_hist_15_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3)
|
|
^ s1_folded_gh_dup_3_hist_15_folded_hist[4],
|
|
s1_folded_gh_dup_3_hist_15_folded_hist[3:0],
|
|
s1_folded_gh_dup_3_hist_15_folded_hist[6],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (s1_last_br_num_oh_dup_3[0]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_15_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_14_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0
|
|
? {s1_folded_gh_dup_3_hist_14_folded_hist[7:1],
|
|
s1_folded_gh_dup_3_hist_14_folded_hist[0]
|
|
| _s1_possible_predicted_fhs_dup_T_277}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {s1_folded_gh_dup_3_hist_14_folded_hist[6:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {s1_folded_gh_dup_3_hist_14_folded_hist[5:0],
|
|
1'h0,
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97
|
|
.s1_FGH_src_hist_13_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_13_folded_hist : 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {s1_folded_gh_dup_3_hist_13_folded_hist[7:4],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_13_folded_hist[3],
|
|
s1_folded_gh_dup_3_hist_13_folded_hist[2:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0
|
|
^ s1_folded_gh_dup_3_hist_13_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {s1_folded_gh_dup_3_hist_13_folded_hist[6:4],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_13_folded_hist[3],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3)
|
|
^ s1_folded_gh_dup_3_hist_13_folded_hist[2],
|
|
s1_folded_gh_dup_3_hist_13_folded_hist[1:0],
|
|
s1_folded_gh_dup_3_hist_13_folded_hist[8],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ s1_folded_gh_dup_3_hist_13_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_12_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0
|
|
? {s1_folded_gh_dup_3_hist_12_folded_hist[3:1],
|
|
s1_folded_gh_dup_3_hist_12_folded_hist[0]
|
|
| _s1_possible_predicted_fhs_dup_T_277}
|
|
: 4'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {s1_folded_gh_dup_3_hist_12_folded_hist[2:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0}
|
|
: 4'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {s1_folded_gh_dup_3_hist_12_folded_hist[1:0],
|
|
1'h0,
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}
|
|
: 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97
|
|
.s1_FGH_src_hist_11_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_11_folded_hist : 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {s1_folded_gh_dup_3_hist_11_folded_hist[6:2],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_11_folded_hist[1],
|
|
s1_folded_gh_dup_3_hist_11_folded_hist[0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0
|
|
^ s1_folded_gh_dup_3_hist_11_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {s1_folded_gh_dup_3_hist_11_folded_hist[5:2],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_11_folded_hist[1],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3)
|
|
^ s1_folded_gh_dup_3_hist_11_folded_hist[0],
|
|
s1_folded_gh_dup_3_hist_11_folded_hist[7],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ s1_folded_gh_dup_3_hist_11_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_10_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_10_folded_hist : 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {s1_folded_gh_dup_3_hist_10_folded_hist[7:5],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_10_folded_hist[4],
|
|
s1_folded_gh_dup_3_hist_10_folded_hist[3:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0
|
|
^ s1_folded_gh_dup_3_hist_10_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {s1_folded_gh_dup_3_hist_10_folded_hist[6:5],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_10_folded_hist[4],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3)
|
|
^ s1_folded_gh_dup_3_hist_10_folded_hist[3],
|
|
s1_folded_gh_dup_3_hist_10_folded_hist[2:0],
|
|
s1_folded_gh_dup_3_hist_10_folded_hist[8],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ s1_folded_gh_dup_3_hist_10_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_9_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_9_folded_hist : 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {s1_folded_gh_dup_3_hist_9_folded_hist[5:4],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_9_folded_hist[3],
|
|
s1_folded_gh_dup_3_hist_9_folded_hist[2:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0
|
|
^ s1_folded_gh_dup_3_hist_9_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {s1_folded_gh_dup_3_hist_9_folded_hist[4],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_9_folded_hist[3],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3)
|
|
^ s1_folded_gh_dup_3_hist_9_folded_hist[2],
|
|
s1_folded_gh_dup_3_hist_9_folded_hist[1:0],
|
|
s1_folded_gh_dup_3_hist_9_folded_hist[6],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ s1_folded_gh_dup_3_hist_9_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_8_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_8_folded_hist : 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_8_folded_hist[6],
|
|
s1_folded_gh_dup_3_hist_8_folded_hist[5:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0
|
|
^ s1_folded_gh_dup_3_hist_8_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3)
|
|
^ s1_folded_gh_dup_3_hist_8_folded_hist[5],
|
|
s1_folded_gh_dup_3_hist_8_folded_hist[4:0],
|
|
s1_folded_gh_dup_3_hist_8_folded_hist[7],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (s1_last_br_num_oh_dup_3[0]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_8_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_7_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_7_folded_hist : 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {s1_folded_gh_dup_3_hist_7_folded_hist[5:1],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_7_folded_hist[0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0
|
|
^ s1_folded_gh_dup_3_hist_7_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {s1_folded_gh_dup_3_hist_7_folded_hist[4:1],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_7_folded_hist[0],
|
|
1'h0,
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ s1_folded_gh_dup_3_hist_7_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:229:73, :285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_6_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_6_folded_hist : 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {s1_folded_gh_dup_3_hist_6_folded_hist[7],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_6_folded_hist[6],
|
|
s1_folded_gh_dup_3_hist_6_folded_hist[5:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0
|
|
^ s1_folded_gh_dup_3_hist_6_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_6_folded_hist[6],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3)
|
|
^ s1_folded_gh_dup_3_hist_6_folded_hist[5],
|
|
s1_folded_gh_dup_3_hist_6_folded_hist[4:0],
|
|
s1_folded_gh_dup_3_hist_6_folded_hist[8],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ s1_folded_gh_dup_3_hist_6_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_5_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_5_folded_hist : 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {s1_folded_gh_dup_3_hist_5_folded_hist[5:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0
|
|
^ (s1_last_br_num_oh_dup_3[0]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_5_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {s1_folded_gh_dup_3_hist_5_folded_hist[4:0],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_5_folded_hist[6],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (s1_last_br_num_oh_dup_3[0]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3)
|
|
^ s1_folded_gh_dup_3_hist_5_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_4_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_4_folded_hist : 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {s1_folded_gh_dup_3_hist_4_folded_hist[6:5],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_4_folded_hist[4],
|
|
s1_folded_gh_dup_3_hist_4_folded_hist[3:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0
|
|
^ s1_folded_gh_dup_3_hist_4_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {s1_folded_gh_dup_3_hist_4_folded_hist[5],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_4_folded_hist[4],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3)
|
|
^ s1_folded_gh_dup_3_hist_4_folded_hist[3],
|
|
s1_folded_gh_dup_3_hist_4_folded_hist[2:0],
|
|
s1_folded_gh_dup_3_hist_4_folded_hist[7],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ s1_folded_gh_dup_3_hist_4_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_3_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_3_folded_hist : 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {s1_folded_gh_dup_3_hist_3_folded_hist[6:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0
|
|
^ (s1_last_br_num_oh_dup_3[0]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_3_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {s1_folded_gh_dup_3_hist_3_folded_hist[5:0],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_3_folded_hist[7],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (s1_last_br_num_oh_dup_3[0]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3)
|
|
^ s1_folded_gh_dup_3_hist_3_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_2_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_2_folded_hist : 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {s1_folded_gh_dup_3_hist_2_folded_hist[6:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0
|
|
^ (s1_last_br_num_oh_dup_3[0]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_2_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {s1_folded_gh_dup_3_hist_2_folded_hist[5:0],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_2_folded_hist[7],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ (s1_last_br_num_oh_dup_3[0]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3)
|
|
^ s1_folded_gh_dup_3_hist_2_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_1_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0 ? s1_folded_gh_dup_3_hist_1_folded_hist : 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {s1_folded_gh_dup_3_hist_1_folded_hist[9:2],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_1_folded_hist[1],
|
|
s1_folded_gh_dup_3_hist_1_folded_hist[0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0
|
|
^ s1_folded_gh_dup_3_hist_1_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {s1_folded_gh_dup_3_hist_1_folded_hist[8:2],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s1_folded_gh_dup_3_hist_1_folded_hist[1],
|
|
(s1_last_br_num_oh_dup_3[0] & s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s1_last_br_num_oh_dup_3[1]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2
|
|
| s1_last_br_num_oh_dup_3[2]
|
|
& s1_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3)
|
|
^ s1_folded_gh_dup_3_hist_1_folded_hist[0],
|
|
s1_folded_gh_dup_3_hist_1_folded_hist[10],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1
|
|
^ s1_folded_gh_dup_3_hist_1_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:285:84, :286:35, :292:40, :298:46, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s1_FGH_src_hist_0_folded_hist
|
|
((_s1_predicted_fh_dup_WIRE_56_3_0
|
|
? {s1_folded_gh_dup_3_hist_0_folded_hist[7:1],
|
|
s1_folded_gh_dup_3_hist_0_folded_hist[0]
|
|
| _s1_possible_predicted_fhs_dup_T_277}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_1
|
|
? {s1_folded_gh_dup_3_hist_0_folded_hist[6:0],
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_10_0}
|
|
: 8'h0)
|
|
| (_s1_predicted_fh_dup_WIRE_56_3_2
|
|
? {s1_folded_gh_dup_3_hist_0_folded_hist[5:0],
|
|
1'h0,
|
|
_s1_possible_predicted_fhs_dup_res_hist_17_new_folded_hist_newest_bits_masked_WIRE_11_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :229:73, :286:35, :474:41, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:{29,37}, :484:19, :488:97
|
|
.s3_FGH_sel (s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_FGH_src_hist_17_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_17_folded_hist : 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_17_folded_hist[9],
|
|
s3_folded_gh_dup_3_hist_17_folded_hist[8:0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0
|
|
^ s3_folded_gh_dup_3_hist_17_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3)
|
|
^ s3_folded_gh_dup_3_hist_17_folded_hist[8],
|
|
s3_folded_gh_dup_3_hist_17_folded_hist[7:0],
|
|
s3_folded_gh_dup_3_hist_17_folded_hist[10],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_3[0]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_17_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_16_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_16_folded_hist : 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {s3_folded_gh_dup_3_hist_16_folded_hist[9],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_16_folded_hist[8],
|
|
s3_folded_gh_dup_3_hist_16_folded_hist[7:0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0
|
|
^ s3_folded_gh_dup_3_hist_16_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_16_folded_hist[8],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3)
|
|
^ s3_folded_gh_dup_3_hist_16_folded_hist[7],
|
|
s3_folded_gh_dup_3_hist_16_folded_hist[6:0],
|
|
s3_folded_gh_dup_3_hist_16_folded_hist[10],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1
|
|
^ s3_folded_gh_dup_3_hist_16_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_15_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_15_folded_hist : 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_15_folded_hist[5],
|
|
s3_folded_gh_dup_3_hist_15_folded_hist[4:0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0
|
|
^ s3_folded_gh_dup_3_hist_15_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3)
|
|
^ s3_folded_gh_dup_3_hist_15_folded_hist[4],
|
|
s3_folded_gh_dup_3_hist_15_folded_hist[3:0],
|
|
s3_folded_gh_dup_3_hist_15_folded_hist[6],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_3[0]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_15_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_14_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_14_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {s3_folded_gh_dup_3_hist_14_folded_hist[6:0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {s3_folded_gh_dup_3_hist_14_folded_hist[5:0],
|
|
1'h0,
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.s3_FGH_src_hist_13_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_13_folded_hist : 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {s3_folded_gh_dup_3_hist_13_folded_hist[7:4],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_13_folded_hist[3],
|
|
s3_folded_gh_dup_3_hist_13_folded_hist[2:0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0
|
|
^ s3_folded_gh_dup_3_hist_13_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {s3_folded_gh_dup_3_hist_13_folded_hist[6:4],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_13_folded_hist[3],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3)
|
|
^ s3_folded_gh_dup_3_hist_13_folded_hist[2],
|
|
s3_folded_gh_dup_3_hist_13_folded_hist[1:0],
|
|
s3_folded_gh_dup_3_hist_13_folded_hist[8],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1
|
|
^ s3_folded_gh_dup_3_hist_13_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_12_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_12_folded_hist : 4'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {s3_folded_gh_dup_3_hist_12_folded_hist[2:0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0}
|
|
: 4'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {s3_folded_gh_dup_3_hist_12_folded_hist[1:0],
|
|
1'h0,
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1}
|
|
: 4'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.s3_FGH_src_hist_11_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_11_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {s3_folded_gh_dup_3_hist_11_folded_hist[6:2],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_11_folded_hist[1],
|
|
s3_folded_gh_dup_3_hist_11_folded_hist[0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0
|
|
^ s3_folded_gh_dup_3_hist_11_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {s3_folded_gh_dup_3_hist_11_folded_hist[5:2],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_11_folded_hist[1],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_1
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_2
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_0_bits_3)
|
|
^ s3_folded_gh_dup_3_hist_11_folded_hist[0],
|
|
s3_folded_gh_dup_3_hist_11_folded_hist[7],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1
|
|
^ s3_folded_gh_dup_3_hist_11_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_10_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_10_folded_hist : 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {s3_folded_gh_dup_3_hist_10_folded_hist[7:5],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_10_folded_hist[4],
|
|
s3_folded_gh_dup_3_hist_10_folded_hist[3:0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0
|
|
^ s3_folded_gh_dup_3_hist_10_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {s3_folded_gh_dup_3_hist_10_folded_hist[6:5],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_10_folded_hist[4],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3)
|
|
^ s3_folded_gh_dup_3_hist_10_folded_hist[3],
|
|
s3_folded_gh_dup_3_hist_10_folded_hist[2:0],
|
|
s3_folded_gh_dup_3_hist_10_folded_hist[8],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1
|
|
^ s3_folded_gh_dup_3_hist_10_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_9_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_9_folded_hist : 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {s3_folded_gh_dup_3_hist_9_folded_hist[5:4],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_9_folded_hist[3],
|
|
s3_folded_gh_dup_3_hist_9_folded_hist[2:0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0
|
|
^ s3_folded_gh_dup_3_hist_9_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {s3_folded_gh_dup_3_hist_9_folded_hist[4],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_9_folded_hist[3],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3)
|
|
^ s3_folded_gh_dup_3_hist_9_folded_hist[2],
|
|
s3_folded_gh_dup_3_hist_9_folded_hist[1:0],
|
|
s3_folded_gh_dup_3_hist_9_folded_hist[6],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1
|
|
^ s3_folded_gh_dup_3_hist_9_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_8_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_8_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_8_folded_hist[6],
|
|
s3_folded_gh_dup_3_hist_8_folded_hist[5:0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0
|
|
^ s3_folded_gh_dup_3_hist_8_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3)
|
|
^ s3_folded_gh_dup_3_hist_8_folded_hist[5],
|
|
s3_folded_gh_dup_3_hist_8_folded_hist[4:0],
|
|
s3_folded_gh_dup_3_hist_8_folded_hist[7],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_3[0]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_8_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_7_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_7_folded_hist : 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {s3_folded_gh_dup_3_hist_7_folded_hist[5:1],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_7_folded_hist[0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0
|
|
^ s3_folded_gh_dup_3_hist_7_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {s3_folded_gh_dup_3_hist_7_folded_hist[4:1],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_4_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_7_folded_hist[0],
|
|
1'h0,
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1
|
|
^ s3_folded_gh_dup_3_hist_7_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :229:73, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_6_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_6_folded_hist : 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {s3_folded_gh_dup_3_hist_6_folded_hist[7],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_6_folded_hist[6],
|
|
s3_folded_gh_dup_3_hist_6_folded_hist[5:0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0
|
|
^ s3_folded_gh_dup_3_hist_6_folded_hist[8]}
|
|
: 9'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_6_folded_hist[6],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3)
|
|
^ s3_folded_gh_dup_3_hist_6_folded_hist[5],
|
|
s3_folded_gh_dup_3_hist_6_folded_hist[4:0],
|
|
s3_folded_gh_dup_3_hist_6_folded_hist[8],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1
|
|
^ s3_folded_gh_dup_3_hist_6_folded_hist[7]}
|
|
: 9'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_5_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_5_folded_hist : 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {s3_folded_gh_dup_3_hist_5_folded_hist[5:0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0
|
|
^ (s3_last_br_num_oh_dup_3[0]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_5_folded_hist[6]}
|
|
: 7'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {s3_folded_gh_dup_3_hist_5_folded_hist[4:0],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_5_folded_hist[6],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_3[0]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_1
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_2
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_5_bits_3)
|
|
^ s3_folded_gh_dup_3_hist_5_folded_hist[5]}
|
|
: 7'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_4_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_4_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {s3_folded_gh_dup_3_hist_4_folded_hist[6:5],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_4_folded_hist[4],
|
|
s3_folded_gh_dup_3_hist_4_folded_hist[3:0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0
|
|
^ s3_folded_gh_dup_3_hist_4_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {s3_folded_gh_dup_3_hist_4_folded_hist[5],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_4_folded_hist[4],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3)
|
|
^ s3_folded_gh_dup_3_hist_4_folded_hist[3],
|
|
s3_folded_gh_dup_3_hist_4_folded_hist[2:0],
|
|
s3_folded_gh_dup_3_hist_4_folded_hist[7],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1
|
|
^ s3_folded_gh_dup_3_hist_4_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_3_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_3_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {s3_folded_gh_dup_3_hist_3_folded_hist[6:0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0
|
|
^ (s3_last_br_num_oh_dup_3[0]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_3_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {s3_folded_gh_dup_3_hist_3_folded_hist[5:0],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_3_folded_hist[7],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_3[0]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_1
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_2
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_2_bits_3)
|
|
^ s3_folded_gh_dup_3_hist_3_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_2_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_2_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {s3_folded_gh_dup_3_hist_2_folded_hist[6:0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0
|
|
^ (s3_last_br_num_oh_dup_3[0]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_2_folded_hist[7]}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {s3_folded_gh_dup_3_hist_2_folded_hist[5:0],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_2_folded_hist[7],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1
|
|
^ (s3_last_br_num_oh_dup_3[0]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_1
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_2
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_3_bits_3)
|
|
^ s3_folded_gh_dup_3_hist_2_folded_hist[6]}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_1_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_1_folded_hist : 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {s3_folded_gh_dup_3_hist_1_folded_hist[9:2],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_1_folded_hist[1],
|
|
s3_folded_gh_dup_3_hist_1_folded_hist[0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0
|
|
^ s3_folded_gh_dup_3_hist_1_folded_hist[10]}
|
|
: 11'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {s3_folded_gh_dup_3_hist_1_folded_hist[8:2],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_0
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2)
|
|
^ s3_folded_gh_dup_3_hist_1_folded_hist[1],
|
|
(s3_last_br_num_oh_dup_3[0] & s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_1
|
|
| s3_last_br_num_oh_dup_3[1]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_2
|
|
| s3_last_br_num_oh_dup_3[2]
|
|
& s3_ahead_fh_oldest_bits_dup_3_afhob_1_bits_3)
|
|
^ s3_folded_gh_dup_3_hist_1_folded_hist[0],
|
|
s3_folded_gh_dup_3_hist_1_folded_hist[10],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1
|
|
^ s3_folded_gh_dup_3_hist_1_folded_hist[9]}
|
|
: 11'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, :32:36, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :285:84, :288:35, :294:40, :300:46, src/main/scala/xiangshan/frontend/FrontendBundle.scala:231:30, :266:48, :268:11, :290:54, :484:19, :488:97
|
|
.s3_FGH_src_hist_0_folded_hist
|
|
((_s3_predicted_fh_dup_WIRE_56_3_0 ? s3_folded_gh_dup_3_hist_0_folded_hist : 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_1
|
|
? {s3_folded_gh_dup_3_hist_0_folded_hist[6:0],
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0}
|
|
: 8'h0)
|
|
| (_s3_predicted_fh_dup_WIRE_56_3_2
|
|
? {s3_folded_gh_dup_3_hist_0_folded_hist[5:0],
|
|
1'h0,
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1}
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :229:73, :288:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:300:37, :484:19, :488:97
|
|
.redirect_FGHT_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.redirect_FGHT_src_hist_17_folded_hist (_GEN_81[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_16_folded_hist (_GEN_82[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_15_folded_hist (_GEN_83[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_14_folded_hist (_GEN_84[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_13_folded_hist (_GEN_85[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_12_folded_hist (_GEN_86[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_11_folded_hist (_GEN_87[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_10_folded_hist (_GEN_88[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_9_folded_hist (_GEN_89[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_8_folded_hist (_GEN_90[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_7_folded_hist (_GEN_91[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_6_folded_hist (_GEN_92[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_5_folded_hist (_GEN_93[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_4_folded_hist (_GEN_94[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_3_folded_hist (_GEN_95[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_2_folded_hist (_GEN_96[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_1_folded_hist (_GEN_97[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.redirect_FGHT_src_hist_0_folded_hist (_GEN_98[thisBrNumOH_dup_shiftAmount]), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, utility/src/main/scala/utility/PriorityMuxGen.scala:138:24
|
|
.stallFGH_src_hist_17_folded_hist (s0_folded_gh_reg_dup_3_hist_17_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_16_folded_hist (s0_folded_gh_reg_dup_3_hist_16_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_15_folded_hist (s0_folded_gh_reg_dup_3_hist_15_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_14_folded_hist (s0_folded_gh_reg_dup_3_hist_14_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_13_folded_hist (s0_folded_gh_reg_dup_3_hist_13_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_12_folded_hist (s0_folded_gh_reg_dup_3_hist_12_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_11_folded_hist (s0_folded_gh_reg_dup_3_hist_11_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_10_folded_hist (s0_folded_gh_reg_dup_3_hist_10_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_9_folded_hist (s0_folded_gh_reg_dup_3_hist_9_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_8_folded_hist (s0_folded_gh_reg_dup_3_hist_8_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_7_folded_hist (s0_folded_gh_reg_dup_3_hist_7_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_6_folded_hist (s0_folded_gh_reg_dup_3_hist_6_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_5_folded_hist (s0_folded_gh_reg_dup_3_hist_5_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_4_folded_hist (s0_folded_gh_reg_dup_3_hist_4_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_3_folded_hist (s0_folded_gh_reg_dup_3_hist_3_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_2_folded_hist (s0_folded_gh_reg_dup_3_hist_2_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_1_folded_hist (s0_folded_gh_reg_dup_3_hist_1_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.stallFGH_src_hist_0_folded_hist (s0_folded_gh_reg_dup_3_hist_0_folded_hist), // src/main/scala/xiangshan/frontend/BPU.scala:285:63
|
|
.out_res_hist_17_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_17_folded_hist),
|
|
.out_res_hist_16_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_16_folded_hist),
|
|
.out_res_hist_15_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_15_folded_hist),
|
|
.out_res_hist_14_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_14_folded_hist),
|
|
.out_res_hist_13_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_13_folded_hist),
|
|
.out_res_hist_12_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_12_folded_hist),
|
|
.out_res_hist_11_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_11_folded_hist),
|
|
.out_res_hist_10_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_10_folded_hist),
|
|
.out_res_hist_9_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_9_folded_hist),
|
|
.out_res_hist_8_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_8_folded_hist),
|
|
.out_res_hist_7_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_7_folded_hist),
|
|
.out_res_hist_6_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_6_folded_hist),
|
|
.out_res_hist_5_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_5_folded_hist),
|
|
.out_res_hist_4_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_4_folded_hist),
|
|
.out_res_hist_3_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_3_folded_hist),
|
|
.out_res_hist_2_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_2_folded_hist),
|
|
.out_res_hist_1_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_1_folded_hist),
|
|
.out_res_hist_0_folded_hist
|
|
(_s0_folded_gh_dup_3_ppm_out_res_hist_0_folded_hist)
|
|
);
|
|
PriorityMuxModule_8 s0_ghist_ptr_dup_0_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_GHPtr_sel
|
|
(s2_redirect_dup_0 & ~s3_redirect_dup_0 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_GHPtr_src_flag
|
|
(_s2_predicted_ghist_ptr_dup_WIRE_56_0_0
|
|
& ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[8])
|
|
| _s2_predicted_ghist_ptr_dup_WIRE_56_0_1
|
|
& ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[8])
|
|
| _s2_predicted_ghist_ptr_dup_WIRE_56_0_2
|
|
& ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21
|
|
.s2_GHPtr_src_value
|
|
((_s2_predicted_ghist_ptr_dup_WIRE_56_0_0
|
|
? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[7:0]
|
|
: 8'h0)
|
|
| (_s2_predicted_ghist_ptr_dup_WIRE_56_0_1
|
|
? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[7:0]
|
|
: 8'h0)
|
|
| (_s2_predicted_ghist_ptr_dup_WIRE_56_0_2
|
|
? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[7:0]
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}
|
|
.s1_GHPtr_sel
|
|
(s1_valid_dup_3 & ~s2_redirect_dup_0 & ~s3_redirect_dup_0
|
|
& ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_GHPtr_src_flag
|
|
(_s1_predicted_ghist_ptr_dup_WIRE_56_0_0
|
|
& ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[8])
|
|
| _s1_predicted_ghist_ptr_dup_WIRE_56_0_1
|
|
& ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[8])
|
|
| _s1_predicted_ghist_ptr_dup_WIRE_56_0_2
|
|
& ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21
|
|
.s1_GHPtr_src_value
|
|
((_s1_predicted_ghist_ptr_dup_WIRE_56_0_0
|
|
? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[7:0]
|
|
: 8'h0)
|
|
| (_s1_predicted_ghist_ptr_dup_WIRE_56_0_1
|
|
? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[7:0]
|
|
: 8'h0)
|
|
| (_s1_predicted_ghist_ptr_dup_WIRE_56_0_2
|
|
? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[7:0]
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}
|
|
.s3_GHPtr_sel (s3_redirect_dup_0 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_GHPtr_src_flag
|
|
(_s3_predicted_ghist_ptr_dup_WIRE_56_0_0
|
|
& ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[8])
|
|
| _s3_predicted_ghist_ptr_dup_WIRE_56_0_1
|
|
& ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[8])
|
|
| _s3_predicted_ghist_ptr_dup_WIRE_56_0_2
|
|
& ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21
|
|
.s3_GHPtr_src_value
|
|
((_s3_predicted_ghist_ptr_dup_WIRE_56_0_0
|
|
? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_1[7:0]
|
|
: 8'h0)
|
|
| (_s3_predicted_ghist_ptr_dup_WIRE_56_0_1
|
|
? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_3[7:0]
|
|
: 8'h0)
|
|
| (_s3_predicted_ghist_ptr_dup_WIRE_56_0_2
|
|
? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_5[7:0]
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}
|
|
.redirect_GHPtr_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_1[8])), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21
|
|
.redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_1[7:0]), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}
|
|
.stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_0_flag), // src/main/scala/xiangshan/frontend/BPU.scala:322:63
|
|
.stallGHPtr_src_value (s0_ghist_ptr_reg_dup_0_value), // src/main/scala/xiangshan/frontend/BPU.scala:322:63
|
|
.out_res_flag (_s0_ghist_ptr_dup_0_ppm_out_res_flag),
|
|
.out_res_value (_s0_ghist_ptr_dup_0_ppm_out_res_value)
|
|
);
|
|
PriorityMuxModule_8 s0_ghist_ptr_dup_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_GHPtr_sel
|
|
(s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_GHPtr_src_flag
|
|
(_s2_predicted_ghist_ptr_dup_WIRE_56_1_0
|
|
& ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[8])
|
|
| _s2_predicted_ghist_ptr_dup_WIRE_56_1_1
|
|
& ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[8])
|
|
| _s2_predicted_ghist_ptr_dup_WIRE_56_1_2
|
|
& ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21
|
|
.s2_GHPtr_src_value
|
|
((_s2_predicted_ghist_ptr_dup_WIRE_56_1_0
|
|
? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[7:0]
|
|
: 8'h0)
|
|
| (_s2_predicted_ghist_ptr_dup_WIRE_56_1_1
|
|
? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[7:0]
|
|
: 8'h0)
|
|
| (_s2_predicted_ghist_ptr_dup_WIRE_56_1_2
|
|
? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[7:0]
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}
|
|
.s1_GHPtr_sel
|
|
(s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1
|
|
& ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_GHPtr_src_flag
|
|
(_s1_predicted_ghist_ptr_dup_WIRE_56_1_0
|
|
& ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[8])
|
|
| _s1_predicted_ghist_ptr_dup_WIRE_56_1_1
|
|
& ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[8])
|
|
| _s1_predicted_ghist_ptr_dup_WIRE_56_1_2
|
|
& ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21
|
|
.s1_GHPtr_src_value
|
|
((_s1_predicted_ghist_ptr_dup_WIRE_56_1_0
|
|
? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[7:0]
|
|
: 8'h0)
|
|
| (_s1_predicted_ghist_ptr_dup_WIRE_56_1_1
|
|
? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[7:0]
|
|
: 8'h0)
|
|
| (_s1_predicted_ghist_ptr_dup_WIRE_56_1_2
|
|
? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[7:0]
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}
|
|
.s3_GHPtr_sel (s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_GHPtr_src_flag
|
|
(_s3_predicted_ghist_ptr_dup_WIRE_56_1_0
|
|
& ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[8])
|
|
| _s3_predicted_ghist_ptr_dup_WIRE_56_1_1
|
|
& ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[8])
|
|
| _s3_predicted_ghist_ptr_dup_WIRE_56_1_2
|
|
& ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21
|
|
.s3_GHPtr_src_value
|
|
((_s3_predicted_ghist_ptr_dup_WIRE_56_1_0
|
|
? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_7[7:0]
|
|
: 8'h0)
|
|
| (_s3_predicted_ghist_ptr_dup_WIRE_56_1_1
|
|
? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_9[7:0]
|
|
: 8'h0)
|
|
| (_s3_predicted_ghist_ptr_dup_WIRE_56_1_2
|
|
? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_11[7:0]
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}
|
|
.redirect_GHPtr_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_3[8])), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21
|
|
.redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_3[7:0]), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}
|
|
.stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_1_flag), // src/main/scala/xiangshan/frontend/BPU.scala:322:63
|
|
.stallGHPtr_src_value (s0_ghist_ptr_reg_dup_1_value), // src/main/scala/xiangshan/frontend/BPU.scala:322:63
|
|
.out_res_flag (_s0_ghist_ptr_dup_1_ppm_out_res_flag),
|
|
.out_res_value (_s0_ghist_ptr_dup_1_ppm_out_res_value)
|
|
);
|
|
PriorityMuxModule_8 s0_ghist_ptr_dup_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_GHPtr_sel
|
|
(s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_GHPtr_src_flag
|
|
(_s2_predicted_ghist_ptr_dup_WIRE_56_2_0
|
|
& ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[8])
|
|
| _s2_predicted_ghist_ptr_dup_WIRE_56_2_1
|
|
& ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[8])
|
|
| _s2_predicted_ghist_ptr_dup_WIRE_56_2_2
|
|
& ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21
|
|
.s2_GHPtr_src_value
|
|
((_s2_predicted_ghist_ptr_dup_WIRE_56_2_0
|
|
? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[7:0]
|
|
: 8'h0)
|
|
| (_s2_predicted_ghist_ptr_dup_WIRE_56_2_1
|
|
? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[7:0]
|
|
: 8'h0)
|
|
| (_s2_predicted_ghist_ptr_dup_WIRE_56_2_2
|
|
? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[7:0]
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}
|
|
.s1_GHPtr_sel
|
|
(s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2
|
|
& ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_GHPtr_src_flag
|
|
(_s1_predicted_ghist_ptr_dup_WIRE_56_2_0
|
|
& ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[8])
|
|
| _s1_predicted_ghist_ptr_dup_WIRE_56_2_1
|
|
& ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[8])
|
|
| _s1_predicted_ghist_ptr_dup_WIRE_56_2_2
|
|
& ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21
|
|
.s1_GHPtr_src_value
|
|
((_s1_predicted_ghist_ptr_dup_WIRE_56_2_0
|
|
? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[7:0]
|
|
: 8'h0)
|
|
| (_s1_predicted_ghist_ptr_dup_WIRE_56_2_1
|
|
? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[7:0]
|
|
: 8'h0)
|
|
| (_s1_predicted_ghist_ptr_dup_WIRE_56_2_2
|
|
? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[7:0]
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}
|
|
.s3_GHPtr_sel (s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_GHPtr_src_flag
|
|
(_s3_predicted_ghist_ptr_dup_WIRE_56_2_0
|
|
& ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[8])
|
|
| _s3_predicted_ghist_ptr_dup_WIRE_56_2_1
|
|
& ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[8])
|
|
| _s3_predicted_ghist_ptr_dup_WIRE_56_2_2
|
|
& ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21
|
|
.s3_GHPtr_src_value
|
|
((_s3_predicted_ghist_ptr_dup_WIRE_56_2_0
|
|
? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_13[7:0]
|
|
: 8'h0)
|
|
| (_s3_predicted_ghist_ptr_dup_WIRE_56_2_1
|
|
? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_15[7:0]
|
|
: 8'h0)
|
|
| (_s3_predicted_ghist_ptr_dup_WIRE_56_2_2
|
|
? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_17[7:0]
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}
|
|
.redirect_GHPtr_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_5[8])), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21
|
|
.redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_5[7:0]), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}
|
|
.stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_2_flag), // src/main/scala/xiangshan/frontend/BPU.scala:322:63
|
|
.stallGHPtr_src_value (s0_ghist_ptr_reg_dup_2_value), // src/main/scala/xiangshan/frontend/BPU.scala:322:63
|
|
.out_res_flag (_s0_ghist_ptr_dup_2_ppm_out_res_flag),
|
|
.out_res_value (_s0_ghist_ptr_dup_2_ppm_out_res_value)
|
|
);
|
|
PriorityMuxModule_8 s0_ghist_ptr_dup_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_GHPtr_sel
|
|
(s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_GHPtr_src_flag
|
|
(_s2_predicted_ghist_ptr_dup_WIRE_56_3_0
|
|
& ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[8])
|
|
| _s2_predicted_ghist_ptr_dup_WIRE_56_3_1
|
|
& ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[8])
|
|
| _s2_predicted_ghist_ptr_dup_WIRE_56_3_2
|
|
& ~(_s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21
|
|
.s2_GHPtr_src_value
|
|
((_s2_predicted_ghist_ptr_dup_WIRE_56_3_0
|
|
? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[7:0]
|
|
: 8'h0)
|
|
| (_s2_predicted_ghist_ptr_dup_WIRE_56_3_1
|
|
? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[7:0]
|
|
: 8'h0)
|
|
| (_s2_predicted_ghist_ptr_dup_WIRE_56_3_2
|
|
? _s2_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[7:0]
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}
|
|
.s1_GHPtr_sel
|
|
(s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3
|
|
& ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_GHPtr_src_flag
|
|
(_s1_predicted_ghist_ptr_dup_WIRE_56_3_0
|
|
& ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[8])
|
|
| _s1_predicted_ghist_ptr_dup_WIRE_56_3_1
|
|
& ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[8])
|
|
| _s1_predicted_ghist_ptr_dup_WIRE_56_3_2
|
|
& ~(_s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21
|
|
.s1_GHPtr_src_value
|
|
((_s1_predicted_ghist_ptr_dup_WIRE_56_3_0
|
|
? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[7:0]
|
|
: 8'h0)
|
|
| (_s1_predicted_ghist_ptr_dup_WIRE_56_3_1
|
|
? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[7:0]
|
|
: 8'h0)
|
|
| (_s1_predicted_ghist_ptr_dup_WIRE_56_3_2
|
|
? _s1_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[7:0]
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}
|
|
.s3_GHPtr_sel (s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_GHPtr_src_flag
|
|
(_s3_predicted_ghist_ptr_dup_WIRE_56_3_0
|
|
& ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[8])
|
|
| _s3_predicted_ghist_ptr_dup_WIRE_56_3_1
|
|
& ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[8])
|
|
| _s3_predicted_ghist_ptr_dup_WIRE_56_3_2
|
|
& ~(_s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[8])), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21
|
|
.s3_GHPtr_src_value
|
|
((_s3_predicted_ghist_ptr_dup_WIRE_56_3_0
|
|
? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_19[7:0]
|
|
: 8'h0)
|
|
| (_s3_predicted_ghist_ptr_dup_WIRE_56_3_1
|
|
? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_21[7:0]
|
|
: 8'h0)
|
|
| (_s3_predicted_ghist_ptr_dup_WIRE_56_3_2
|
|
? _s3_possible_predicted_ghist_ptrs_dup_flipped_new_ptr_new_ptr_WIRE_23[7:0]
|
|
: 8'h0)), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, src/main/scala/xiangshan/frontend/FrontendBundle.scala:484:19, :488:97, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}
|
|
.redirect_GHPtr_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.redirect_GHPtr_src_flag (~(_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_7[8])), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :56:21
|
|
.redirect_GHPtr_src_value (_updated_ptr_dup_flipped_new_ptr_new_ptr_WIRE_7[7:0]), // utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}
|
|
.stallGHPtr_src_flag (s0_ghist_ptr_reg_dup_3_flag), // src/main/scala/xiangshan/frontend/BPU.scala:322:63
|
|
.stallGHPtr_src_value (s0_ghist_ptr_reg_dup_3_value), // src/main/scala/xiangshan/frontend/BPU.scala:322:63
|
|
.out_res_flag (_s0_ghist_ptr_dup_3_ppm_out_res_flag),
|
|
.out_res_value (_s0_ghist_ptr_dup_3_ppm_out_res_value)
|
|
);
|
|
PriorityMuxModule_12 s0_ahead_fh_oldest_bits_dup_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_AFHOB_sel
|
|
(s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_4_bits_0 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_4_bits_1 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_3_bits_3 (s2_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_1_bits_0 (s2_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_1_bits_3 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_0_bits_0 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_1_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_0_bits_2 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_0_bits_3 (s2_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_sel
|
|
(s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1
|
|
& ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_4_bits_0 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_src_afhob_4_bits_1 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_3_bits_3 (s1_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.s1_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.s1_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.s1_AFHOB_src_afhob_1_bits_0 (s1_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
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.s1_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.s1_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.s1_AFHOB_src_afhob_1_bits_3 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
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.s1_AFHOB_src_afhob_0_bits_0 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
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.s1_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_1_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.s1_AFHOB_src_afhob_0_bits_2 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
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.s1_AFHOB_src_afhob_0_bits_3 (s1_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
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.s3_AFHOB_sel (s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
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.s3_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.s3_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.s3_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.s3_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.s3_AFHOB_src_afhob_4_bits_0 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
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.s3_AFHOB_src_afhob_4_bits_1 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
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.s3_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.s3_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.s3_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.s3_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.s3_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
.s3_AFHOB_src_afhob_3_bits_3 (s3_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
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|
.s3_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.s3_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.s3_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.s3_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
.s3_AFHOB_src_afhob_1_bits_0 (s3_ahead_fh_ob_src_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
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|
.s3_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
.s3_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
.s3_AFHOB_src_afhob_1_bits_3 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
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|
.s3_AFHOB_src_afhob_0_bits_0 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
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|
.s3_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_1_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
.s3_AFHOB_src_afhob_0_bits_2 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
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|
.s3_AFHOB_src_afhob_0_bits_3 (s3_ahead_fh_ob_src_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
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.redirect_AFHOB_src_afhob_5_bits_0
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|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
.redirect_AFHOB_src_afhob_5_bits_1
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(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
.redirect_AFHOB_src_afhob_5_bits_2
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|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
.redirect_AFHOB_src_afhob_5_bits_3
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(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_4_bits_0 (thisAheadFhOb_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_4_bits_1 (thisAheadFhOb_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
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|
.redirect_AFHOB_src_afhob_4_bits_2
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|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
.redirect_AFHOB_src_afhob_4_bits_3
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|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
.redirect_AFHOB_src_afhob_3_bits_0
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|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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.redirect_AFHOB_src_afhob_3_bits_1
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|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
.redirect_AFHOB_src_afhob_3_bits_2
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|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_3_bits_3 (thisAheadFhOb_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_2_bits_0
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_2_bits_1
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|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
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|
.redirect_AFHOB_src_afhob_2_bits_2
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|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_2_bits_3
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_1_bits_0 (thisAheadFhOb_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_1_bits_1
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_1_bits_2
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_1_bits_3 (thisAheadFhOb_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_0_bits_0 (thisAheadFhOb_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_0_bits_1
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_0_bits_2 (thisAheadFhOb_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_0_bits_3 (thisAheadFhOb_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.stallAFHOB_src_afhob_5_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_5_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_5_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_5_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_5_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_4_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_4_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_4_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_4_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_4_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_3_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_3_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_3_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_3_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_3_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_2_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_2_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_2_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_2_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_2_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_1_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_1_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_1_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_1_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_1_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_0_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_0_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_0_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_0_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_1_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.out_res_afhob_5_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_0),
|
|
.out_res_afhob_5_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_1),
|
|
.out_res_afhob_5_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_2),
|
|
.out_res_afhob_5_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_5_bits_3),
|
|
.out_res_afhob_4_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_0),
|
|
.out_res_afhob_4_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_1),
|
|
.out_res_afhob_4_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_2),
|
|
.out_res_afhob_4_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_4_bits_3),
|
|
.out_res_afhob_3_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_0),
|
|
.out_res_afhob_3_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_1),
|
|
.out_res_afhob_3_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_2),
|
|
.out_res_afhob_3_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_3_bits_3),
|
|
.out_res_afhob_2_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_0),
|
|
.out_res_afhob_2_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_1),
|
|
.out_res_afhob_2_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_2),
|
|
.out_res_afhob_2_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_2_bits_3),
|
|
.out_res_afhob_1_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_0),
|
|
.out_res_afhob_1_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_1),
|
|
.out_res_afhob_1_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_2),
|
|
.out_res_afhob_1_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_1_bits_3),
|
|
.out_res_afhob_0_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_0),
|
|
.out_res_afhob_0_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_1),
|
|
.out_res_afhob_0_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_2),
|
|
.out_res_afhob_0_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_1_ppm_out_res_afhob_0_bits_3)
|
|
);
|
|
PriorityMuxModule_12 s0_ahead_fh_oldest_bits_dup_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_AFHOB_sel
|
|
(s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_4_bits_0 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_4_bits_1 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_3_bits_3 (s2_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_1_bits_0 (s2_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_1_bits_3 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_0_bits_0 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_2_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_0_bits_2 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_0_bits_3 (s2_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_sel
|
|
(s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2
|
|
& ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_4_bits_0 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_src_afhob_4_bits_1 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_3_bits_3 (s1_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_1_bits_0 (s1_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_1_bits_3 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_src_afhob_0_bits_0 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_2_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_0_bits_2 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_src_afhob_0_bits_3 (s1_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s3_AFHOB_sel (s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_4_bits_0 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s3_AFHOB_src_afhob_4_bits_1 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s3_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_3_bits_3 (s3_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s3_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_1_bits_0 (s3_ahead_fh_ob_src_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s3_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_1_bits_3 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s3_AFHOB_src_afhob_0_bits_0 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s3_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_2_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_0_bits_2 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s3_AFHOB_src_afhob_0_bits_3 (s3_ahead_fh_ob_src_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.redirect_AFHOB_src_afhob_5_bits_0
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_5_bits_1
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_5_bits_2
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_5_bits_3
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_4_bits_0 (thisAheadFhOb_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_4_bits_1 (thisAheadFhOb_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_4_bits_2
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_4_bits_3
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_3_bits_0
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_3_bits_1
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_3_bits_2
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_3_bits_3 (thisAheadFhOb_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_2_bits_0
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_2_bits_1
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_2_bits_2
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_2_bits_3
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_1_bits_0 (thisAheadFhOb_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_1_bits_1
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_1_bits_2
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_1_bits_3 (thisAheadFhOb_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_0_bits_0 (thisAheadFhOb_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_0_bits_1
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_0_bits_2 (thisAheadFhOb_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_0_bits_3 (thisAheadFhOb_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.stallAFHOB_src_afhob_5_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_5_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_5_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_5_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_5_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_4_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_4_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_4_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_4_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_4_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_3_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_3_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_3_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_3_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_3_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_2_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_2_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_2_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_2_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_2_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_1_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_1_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_1_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_1_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_1_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_0_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_0_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_0_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_0_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_2_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.out_res_afhob_5_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_0),
|
|
.out_res_afhob_5_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_1),
|
|
.out_res_afhob_5_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_2),
|
|
.out_res_afhob_5_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_5_bits_3),
|
|
.out_res_afhob_4_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_0),
|
|
.out_res_afhob_4_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_1),
|
|
.out_res_afhob_4_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_2),
|
|
.out_res_afhob_4_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_4_bits_3),
|
|
.out_res_afhob_3_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_0),
|
|
.out_res_afhob_3_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_1),
|
|
.out_res_afhob_3_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_2),
|
|
.out_res_afhob_3_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_3_bits_3),
|
|
.out_res_afhob_2_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_0),
|
|
.out_res_afhob_2_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_1),
|
|
.out_res_afhob_2_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_2),
|
|
.out_res_afhob_2_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_2_bits_3),
|
|
.out_res_afhob_1_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_0),
|
|
.out_res_afhob_1_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_1),
|
|
.out_res_afhob_1_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_2),
|
|
.out_res_afhob_1_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_1_bits_3),
|
|
.out_res_afhob_0_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_0),
|
|
.out_res_afhob_0_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_1),
|
|
.out_res_afhob_0_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_2),
|
|
.out_res_afhob_0_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_2_ppm_out_res_afhob_0_bits_3)
|
|
);
|
|
PriorityMuxModule_12 s0_ahead_fh_oldest_bits_dup_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_AFHOB_sel
|
|
(s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_4_bits_0 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_4_bits_1 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_3_bits_3 (s2_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_1_bits_0 (s2_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_1_bits_3 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_0_bits_0 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s2_ghist_ptr_dup_3_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :324:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s2_AFHOB_src_afhob_0_bits_2 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s2_AFHOB_src_afhob_0_bits_3 (s2_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_sel
|
|
(s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3
|
|
& ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_4_bits_0 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_src_afhob_4_bits_1 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_3_bits_3 (s1_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_1_bits_0 (s1_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_1_bits_3 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_src_afhob_0_bits_0 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s1_ghist_ptr_dup_3_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :323:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s1_AFHOB_src_afhob_0_bits_2 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s1_AFHOB_src_afhob_0_bits_3 (s1_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s3_AFHOB_sel (s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_AFHOB_src_afhob_5_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_5_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_5_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_5_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_4_bits_0 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s3_AFHOB_src_afhob_4_bits_1 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s3_AFHOB_src_afhob_4_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_4_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_3_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_3_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_3_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_3_bits_3 (s3_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s3_AFHOB_src_afhob_2_bits_0 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_2_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_2_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_2_bits_3 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_1_bits_0 (s3_ahead_fh_ob_src_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s3_AFHOB_src_afhob_1_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_1_bits_2 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_1_bits_3 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s3_AFHOB_src_afhob_0_bits_0 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s3_AFHOB_src_afhob_0_bits_1 (_GEN_3[8'(s3_ghist_ptr_dup_3_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.s3_AFHOB_src_afhob_0_bits_2 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.s3_AFHOB_src_afhob_0_bits_3 (s3_ahead_fh_ob_src_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.redirect_AFHOB_src_afhob_5_bits_0
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h77)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_5_bits_1
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h76)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_5_bits_2
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h75)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_5_bits_3
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h74)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_4_bits_0 (thisAheadFhOb_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_4_bits_1 (thisAheadFhOb_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_4_bits_2
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h6)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_4_bits_3
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h5)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_3_bits_0
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h10)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_3_bits_1
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hF)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_3_bits_2
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hE)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_3_bits_3 (thisAheadFhOb_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_2_bits_0
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h20)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_2_bits_1
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1F)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_2_bits_2
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1E)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_2_bits_3
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h1D)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_1_bits_0 (thisAheadFhOb_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_1_bits_1
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hC)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_1_bits_2
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'hB)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_1_bits_3 (thisAheadFhOb_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_0_bits_0 (thisAheadFhOb_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_0_bits_1
|
|
(_GEN_3[8'(do_redirect_dup_3_bits_cfiUpdate_histPtr_value + 8'h9)]), // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46
|
|
.redirect_AFHOB_src_afhob_0_bits_2 (thisAheadFhOb_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.redirect_AFHOB_src_afhob_0_bits_3 (thisAheadFhOb_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:339:20
|
|
.stallAFHOB_src_afhob_5_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_5_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_5_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_5_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_5_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_4_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_4_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_4_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_4_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_4_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_3_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_3_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_3_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_3_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_3_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_2_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_2_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_2_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_2_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_2_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_1_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_1_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_1_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_1_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_1_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_0_bits_0 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_0), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_0_bits_1 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_1), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_0_bits_2 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_2), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.stallAFHOB_src_afhob_0_bits_3 (s0_ahead_fh_oldest_bits_reg_dup_3_afhob_0_bits_3), // src/main/scala/xiangshan/frontend/BPU.scala:297:85
|
|
.out_res_afhob_5_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_0),
|
|
.out_res_afhob_5_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_1),
|
|
.out_res_afhob_5_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_2),
|
|
.out_res_afhob_5_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_5_bits_3),
|
|
.out_res_afhob_4_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_0),
|
|
.out_res_afhob_4_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_1),
|
|
.out_res_afhob_4_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_2),
|
|
.out_res_afhob_4_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_4_bits_3),
|
|
.out_res_afhob_3_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_0),
|
|
.out_res_afhob_3_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_1),
|
|
.out_res_afhob_3_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_2),
|
|
.out_res_afhob_3_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_3_bits_3),
|
|
.out_res_afhob_2_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_0),
|
|
.out_res_afhob_2_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_1),
|
|
.out_res_afhob_2_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_2),
|
|
.out_res_afhob_2_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_2_bits_3),
|
|
.out_res_afhob_1_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_0),
|
|
.out_res_afhob_1_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_1),
|
|
.out_res_afhob_1_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_2),
|
|
.out_res_afhob_1_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_1_bits_3),
|
|
.out_res_afhob_0_bits_0
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_0),
|
|
.out_res_afhob_0_bits_1
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_1),
|
|
.out_res_afhob_0_bits_2
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_2),
|
|
.out_res_afhob_0_bits_3
|
|
(_s0_ahead_fh_oldest_bits_dup_3_ppm_out_res_afhob_0_bits_3)
|
|
);
|
|
PriorityMuxModule_16 s0_last_br_num_oh_dup_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_BrNumOH_sel
|
|
(s2_redirect_dup_1 & ~s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_BrNumOH_src
|
|
({_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1 & ~_GEN_25
|
|
& _predictors_io_out_s2_full_pred_1_hit,
|
|
_predictors_io_out_s2_full_pred_1_slot_valids_0
|
|
& (_GEN_25 | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1)
|
|
& _predictors_io_out_s2_full_pred_1_hit,
|
|
~_predictors_io_out_s2_full_pred_1_hit
|
|
| ~(_predictors_io_out_s2_full_pred_1_slot_valids_0
|
|
| _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_21_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :614:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}
|
|
.s1_BrNumOH_sel
|
|
(s1_valid_dup_3 & ~s2_redirect_dup_1 & ~s3_redirect_dup_1
|
|
& ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_BrNumOH_src
|
|
({_s1_predicted_fh_dup_WIRE_21_1 & ~_GEN_9 & _predictors_io_out_s1_full_pred_1_hit,
|
|
_predictors_io_out_s1_full_pred_1_slot_valids_0 & _GEN_10
|
|
& _predictors_io_out_s1_full_pred_1_hit,
|
|
~_predictors_io_out_s1_full_pred_1_hit | ~_GEN_8}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :511:118, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,97}
|
|
.s3_BrNumOH_sel (s3_redirect_dup_1 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_BrNumOH_src
|
|
({_s3_predicted_fh_dup_WIRE_21_1 & ~_GEN_36 & _predictors_io_out_s3_full_pred_1_hit,
|
|
_predictors_io_out_s3_full_pred_1_slot_valids_0
|
|
& (_GEN_36 | ~_s3_predicted_fh_dup_WIRE_21_1)
|
|
& _predictors_io_out_s3_full_pred_1_hit,
|
|
~_predictors_io_out_s3_full_pred_1_hit
|
|
| ~(_predictors_io_out_s3_full_pred_1_slot_valids_0
|
|
| _s3_predicted_fh_dup_WIRE_21_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :699:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}
|
|
.redirect_BrNumOH_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.redirect_BrNumOH_src (_thisBrNumOH_dup_T_1[2:0]), // src/main/scala/chisel3/util/OneHot.scala:65:{12,27}
|
|
.stallBrNumOH_src (s0_last_br_num_oh_reg_dup_1), // src/main/scala/xiangshan/frontend/BPU.scala:291:73
|
|
.out_res (_s0_last_br_num_oh_dup_1_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_16 s0_last_br_num_oh_dup_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_BrNumOH_sel
|
|
(s2_redirect_dup_2 & ~s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_BrNumOH_src
|
|
({_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1 & ~_GEN_26
|
|
& _predictors_io_out_s2_full_pred_2_hit,
|
|
_predictors_io_out_s2_full_pred_2_slot_valids_0
|
|
& (_GEN_26 | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1)
|
|
& _predictors_io_out_s2_full_pred_2_hit,
|
|
~_predictors_io_out_s2_full_pred_2_hit
|
|
| ~(_predictors_io_out_s2_full_pred_2_slot_valids_0
|
|
| _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_35_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :614:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}
|
|
.s1_BrNumOH_sel
|
|
(s1_valid_dup_3 & ~s2_redirect_dup_2 & ~s3_redirect_dup_2
|
|
& ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_BrNumOH_src
|
|
({_s1_predicted_fh_dup_WIRE_35_1 & ~_GEN_12 & _predictors_io_out_s1_full_pred_2_hit,
|
|
_predictors_io_out_s1_full_pred_2_slot_valids_0 & _GEN_13
|
|
& _predictors_io_out_s1_full_pred_2_hit,
|
|
~_predictors_io_out_s1_full_pred_2_hit | ~_GEN_11}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :511:118, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,97}
|
|
.s3_BrNumOH_sel (s3_redirect_dup_2 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_BrNumOH_src
|
|
({_s3_predicted_fh_dup_WIRE_35_1 & ~_GEN_37 & _predictors_io_out_s3_full_pred_2_hit,
|
|
_predictors_io_out_s3_full_pred_2_slot_valids_0
|
|
& (_GEN_37 | ~_s3_predicted_fh_dup_WIRE_35_1)
|
|
& _predictors_io_out_s3_full_pred_2_hit,
|
|
~_predictors_io_out_s3_full_pred_2_hit
|
|
| ~(_predictors_io_out_s3_full_pred_2_slot_valids_0
|
|
| _s3_predicted_fh_dup_WIRE_35_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :699:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}
|
|
.redirect_BrNumOH_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.redirect_BrNumOH_src (_thisBrNumOH_dup_T_2[2:0]), // src/main/scala/chisel3/util/OneHot.scala:65:{12,27}
|
|
.stallBrNumOH_src (s0_last_br_num_oh_reg_dup_2), // src/main/scala/xiangshan/frontend/BPU.scala:291:73
|
|
.out_res (_s0_last_br_num_oh_dup_2_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_16 s0_last_br_num_oh_dup_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_BrNumOH_sel
|
|
(s2_redirect_dup_3 & ~s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_BrNumOH_src
|
|
({_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1 & ~_GEN_27
|
|
& _predictors_io_out_s2_full_pred_3_hit,
|
|
_predictors_io_out_s2_full_pred_3_slot_valids_0
|
|
& (_GEN_27 | ~_s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1)
|
|
& _predictors_io_out_s2_full_pred_3_hit,
|
|
~_predictors_io_out_s2_full_pred_3_hit
|
|
| ~(_predictors_io_out_s2_full_pred_3_slot_valids_0
|
|
| _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_49_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :614:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}
|
|
.s1_BrNumOH_sel
|
|
(s1_valid_dup_3 & ~s2_redirect_dup_3 & ~s3_redirect_dup_3
|
|
& ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:271:65, :350:40, :605:28, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_BrNumOH_src
|
|
({_s1_predicted_fh_dup_WIRE_49_1 & ~_GEN_15 & _predictors_io_out_s1_full_pred_3_hit,
|
|
_predictors_io_out_s1_full_pred_3_slot_valids_0 & _GEN_16
|
|
& _predictors_io_out_s1_full_pred_3_hit,
|
|
~_predictors_io_out_s1_full_pred_3_hit | ~_GEN_14}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :511:118, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,97}
|
|
.s3_BrNumOH_sel (s3_redirect_dup_3 & ~do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40, :684:28, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_BrNumOH_src
|
|
({_s3_predicted_fh_dup_WIRE_49_1 & ~_GEN_38 & _predictors_io_out_s3_full_pred_3_hit,
|
|
_predictors_io_out_s3_full_pred_3_slot_valids_0
|
|
& (_GEN_38 | ~_s3_predicted_fh_dup_WIRE_49_1)
|
|
& _predictors_io_out_s3_full_pred_3_hit,
|
|
~_predictors_io_out_s3_full_pred_3_hit
|
|
| ~(_predictors_io_out_s3_full_pred_3_slot_valids_0
|
|
| _s3_predicted_fh_dup_WIRE_49_1)}), // src/main/scala/xiangshan/frontend/BPU.scala:225:26, :699:124, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :473:32, :484:{14,19,22,41}, :487:9, :488:{34,37,97}
|
|
.redirect_BrNumOH_sel (do_redirect_dup_3_valid), // src/main/scala/xiangshan/frontend/BPU.scala:350:40
|
|
.redirect_BrNumOH_src (_thisBrNumOH_dup_T_3[2:0]), // src/main/scala/chisel3/util/OneHot.scala:65:{12,27}
|
|
.stallBrNumOH_src (s0_last_br_num_oh_reg_dup_3), // src/main/scala/xiangshan/frontend/BPU.scala:291:73
|
|
.out_res (_s0_last_br_num_oh_dup_3_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_0_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_0_T_1 & ~_ghv_wens_0_T_2 & ~_ghv_wens_0_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(~(|s2_ghist_ptr_dup_0_value) & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h1
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :582:58, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_0_T & ~_ghv_wens_0_T_1 & ~_ghv_wens_0_T_2 & ~_ghv_wens_0_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(~(|s1_ghist_ptr_dup_0_value) & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h1 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :494:58, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_0_T_2 & ~_ghv_wens_0_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(~(|s3_ghist_ptr_dup_0_value) & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h1 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :663:58, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(~(|do_redirect_dup_3_bits_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :760:50, :763:52
|
|
.out_res (_ghv_write_datas_0_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_1_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_1_T_1 & ~_ghv_wens_1_T_2 & ~_ghv_wens_1_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h2
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_1_T & ~_ghv_wens_1_T_1 & ~_ghv_wens_1_T_2 & ~_ghv_wens_1_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h2 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_1_T_2 & ~_ghv_wens_1_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h1 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h2 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_1_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_2_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_2_T_1 & ~_ghv_wens_2_T_2 & ~_ghv_wens_2_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h3
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_2_T & ~_ghv_wens_2_T_1 & ~_ghv_wens_2_T_2 & ~_ghv_wens_2_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h3 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_2_T_2 & ~_ghv_wens_2_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h2 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h3 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_2_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_3_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_3_T_1 & ~_ghv_wens_3_T_2 & ~_ghv_wens_3_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h4
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_3_T & ~_ghv_wens_3_T_1 & ~_ghv_wens_3_T_2 & ~_ghv_wens_3_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h4 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_3_T_2 & ~_ghv_wens_3_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h3 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h4 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_3_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_4_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_4_T_1 & ~_ghv_wens_4_T_2 & ~_ghv_wens_4_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h5
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_4_T & ~_ghv_wens_4_T_1 & ~_ghv_wens_4_T_2 & ~_ghv_wens_4_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h5 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_4_T_2 & ~_ghv_wens_4_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h4 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h5 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_4_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_5_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_5_T_1 & ~_ghv_wens_5_T_2 & ~_ghv_wens_5_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h6
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_5_T & ~_ghv_wens_5_T_1 & ~_ghv_wens_5_T_2 & ~_ghv_wens_5_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h6 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_5_T_2 & ~_ghv_wens_5_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h5 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h6 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_5_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_6_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_6_T_1 & ~_ghv_wens_6_T_2 & ~_ghv_wens_6_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h7
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_6_T & ~_ghv_wens_6_T_1 & ~_ghv_wens_6_T_2 & ~_ghv_wens_6_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h7 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_6_T_2 & ~_ghv_wens_6_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h6 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h7 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_6_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_7_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_7_T_1 & ~_ghv_wens_7_T_2 & ~_ghv_wens_7_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h8
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_7_T & ~_ghv_wens_7_T_1 & ~_ghv_wens_7_T_2 & ~_ghv_wens_7_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h8 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_7_T_2 & ~_ghv_wens_7_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h7 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h8 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_7_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_8_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_8_T_1 & ~_ghv_wens_8_T_2 & ~_ghv_wens_8_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h9
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_8_T & ~_ghv_wens_8_T_1 & ~_ghv_wens_8_T_2 & ~_ghv_wens_8_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h9 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_8_T_2 & ~_ghv_wens_8_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h8 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h9 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_8_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_9_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_9_T_1 & ~_ghv_wens_9_T_2 & ~_ghv_wens_9_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hA
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_9_T & ~_ghv_wens_9_T_1 & ~_ghv_wens_9_T_2 & ~_ghv_wens_9_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hA & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_9_T_2 & ~_ghv_wens_9_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h9 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hA & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_9_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_10_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_10_T_1 & ~_ghv_wens_10_T_2 & ~_ghv_wens_10_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hB
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_10_T & ~_ghv_wens_10_T_1 & ~_ghv_wens_10_T_2 & ~_ghv_wens_10_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hB & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_10_T_2 & ~_ghv_wens_10_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hA & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hB & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_10_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_11_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_11_T_1 & ~_ghv_wens_11_T_2 & ~_ghv_wens_11_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hC
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_11_T & ~_ghv_wens_11_T_1 & ~_ghv_wens_11_T_2 & ~_ghv_wens_11_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hC & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_11_T_2 & ~_ghv_wens_11_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hB & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hC & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_11_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_12_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_12_T_1 & ~_ghv_wens_12_T_2 & ~_ghv_wens_12_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hD
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_12_T & ~_ghv_wens_12_T_1 & ~_ghv_wens_12_T_2 & ~_ghv_wens_12_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hD & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_12_T_2 & ~_ghv_wens_12_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hC & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hD & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_12_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_13_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_13_T_1 & ~_ghv_wens_13_T_2 & ~_ghv_wens_13_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hE
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_13_T & ~_ghv_wens_13_T_1 & ~_ghv_wens_13_T_2 & ~_ghv_wens_13_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hE & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_13_T_2 & ~_ghv_wens_13_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hD & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hE & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_13_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_14_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_14_T_1 & ~_ghv_wens_14_T_2 & ~_ghv_wens_14_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hF
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_14_T & ~_ghv_wens_14_T_1 & ~_ghv_wens_14_T_2 & ~_ghv_wens_14_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hF & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_14_T_2 & ~_ghv_wens_14_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hE & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hF & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_14_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_15_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_15_T_1 & ~_ghv_wens_15_T_2 & ~_ghv_wens_15_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h10
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_15_T & ~_ghv_wens_15_T_1 & ~_ghv_wens_15_T_2 & ~_ghv_wens_15_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h10 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_15_T_2 & ~_ghv_wens_15_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hF & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h10 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h10 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_15_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_16_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_16_T_1 & ~_ghv_wens_16_T_2 & ~_ghv_wens_16_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h11
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_16_T & ~_ghv_wens_16_T_1 & ~_ghv_wens_16_T_2 & ~_ghv_wens_16_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h11 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_16_T_2 & ~_ghv_wens_16_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h10 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h11 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h10 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h11 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_16_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_17_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_17_T_1 & ~_ghv_wens_17_T_2 & ~_ghv_wens_17_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h12
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_17_T & ~_ghv_wens_17_T_1 & ~_ghv_wens_17_T_2 & ~_ghv_wens_17_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h12 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_17_T_2 & ~_ghv_wens_17_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h11 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h12 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h11 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h12 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_17_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_18_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_18_T_1 & ~_ghv_wens_18_T_2 & ~_ghv_wens_18_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h13
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_18_T & ~_ghv_wens_18_T_1 & ~_ghv_wens_18_T_2 & ~_ghv_wens_18_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h13 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_18_T_2 & ~_ghv_wens_18_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h12 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h13 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h12 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h13 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_18_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_19_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_19_T_1 & ~_ghv_wens_19_T_2 & ~_ghv_wens_19_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h14
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_19_T & ~_ghv_wens_19_T_1 & ~_ghv_wens_19_T_2 & ~_ghv_wens_19_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h14 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_19_T_2 & ~_ghv_wens_19_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h13 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h14 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h13 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h14 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_19_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_20_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_20_T_1 & ~_ghv_wens_20_T_2 & ~_ghv_wens_20_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h15
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_20_T & ~_ghv_wens_20_T_1 & ~_ghv_wens_20_T_2 & ~_ghv_wens_20_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h15 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_20_T_2 & ~_ghv_wens_20_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h14 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h15 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h14 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h15 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_20_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_21_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_21_T_1 & ~_ghv_wens_21_T_2 & ~_ghv_wens_21_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h16
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_21_T & ~_ghv_wens_21_T_1 & ~_ghv_wens_21_T_2 & ~_ghv_wens_21_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h16 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_21_T_2 & ~_ghv_wens_21_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h15 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h16 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h15 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h16 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_21_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_22_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_22_T_1 & ~_ghv_wens_22_T_2 & ~_ghv_wens_22_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h17
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_22_T & ~_ghv_wens_22_T_1 & ~_ghv_wens_22_T_2 & ~_ghv_wens_22_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h17 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_22_T_2 & ~_ghv_wens_22_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h16 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h17 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h16 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h17 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_22_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_23_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_23_T_1 & ~_ghv_wens_23_T_2 & ~_ghv_wens_23_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h18
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_23_T & ~_ghv_wens_23_T_1 & ~_ghv_wens_23_T_2 & ~_ghv_wens_23_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h18 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_23_T_2 & ~_ghv_wens_23_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h17 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h18 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h17 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h18 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_23_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_24_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_24_T_1 & ~_ghv_wens_24_T_2 & ~_ghv_wens_24_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h19
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_24_T & ~_ghv_wens_24_T_1 & ~_ghv_wens_24_T_2 & ~_ghv_wens_24_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h19 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_24_T_2 & ~_ghv_wens_24_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h18 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h19 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h18 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h19 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_24_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_25_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_25_T_1 & ~_ghv_wens_25_T_2 & ~_ghv_wens_25_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h1A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_25_T & ~_ghv_wens_25_T_1 & ~_ghv_wens_25_T_2 & ~_ghv_wens_25_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h1A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_25_T_2 & ~_ghv_wens_25_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h19 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h1A & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h19 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1A & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_25_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_26_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_26_T_1 & ~_ghv_wens_26_T_2 & ~_ghv_wens_26_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h1B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_26_T & ~_ghv_wens_26_T_1 & ~_ghv_wens_26_T_2 & ~_ghv_wens_26_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h1B & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_26_T_2 & ~_ghv_wens_26_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h1A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h1B & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1A & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1B & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_26_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_27_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_27_T_1 & ~_ghv_wens_27_T_2 & ~_ghv_wens_27_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h1C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_27_T & ~_ghv_wens_27_T_1 & ~_ghv_wens_27_T_2 & ~_ghv_wens_27_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h1C & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_27_T_2 & ~_ghv_wens_27_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h1B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h1C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1B & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1C & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_27_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_28_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_28_T_1 & ~_ghv_wens_28_T_2 & ~_ghv_wens_28_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h1D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_28_T & ~_ghv_wens_28_T_1 & ~_ghv_wens_28_T_2 & ~_ghv_wens_28_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h1D & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_28_T_2 & ~_ghv_wens_28_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h1C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h1D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1C & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1D & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_28_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_29_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_29_T_1 & ~_ghv_wens_29_T_2 & ~_ghv_wens_29_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h1E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_29_T & ~_ghv_wens_29_T_1 & ~_ghv_wens_29_T_2 & ~_ghv_wens_29_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h1E & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_29_T_2 & ~_ghv_wens_29_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h1D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h1E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1D & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1E & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_29_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_30_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_30_T_1 & ~_ghv_wens_30_T_2 & ~_ghv_wens_30_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h1F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_30_T & ~_ghv_wens_30_T_1 & ~_ghv_wens_30_T_2 & ~_ghv_wens_30_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h1F & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_30_T_2 & ~_ghv_wens_30_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h1E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h1F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1E & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1F & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_30_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_31_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_31_T_1 & ~_ghv_wens_31_T_2 & ~_ghv_wens_31_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h20
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_31_T & ~_ghv_wens_31_T_1 & ~_ghv_wens_31_T_2 & ~_ghv_wens_31_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h20 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_31_T_2 & ~_ghv_wens_31_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h1F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h20 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h1F & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h20 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_31_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_32_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_32_T_1 & ~_ghv_wens_32_T_2 & ~_ghv_wens_32_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h21
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_32_T & ~_ghv_wens_32_T_1 & ~_ghv_wens_32_T_2 & ~_ghv_wens_32_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h21 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_32_T_2 & ~_ghv_wens_32_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h20 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h21 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h20 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h21 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_32_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_33_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_33_T_1 & ~_ghv_wens_33_T_2 & ~_ghv_wens_33_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h22
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_33_T & ~_ghv_wens_33_T_1 & ~_ghv_wens_33_T_2 & ~_ghv_wens_33_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h22 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_33_T_2 & ~_ghv_wens_33_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h21 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h22 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h21 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h22 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_33_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_34_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_34_T_1 & ~_ghv_wens_34_T_2 & ~_ghv_wens_34_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h23
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_34_T & ~_ghv_wens_34_T_1 & ~_ghv_wens_34_T_2 & ~_ghv_wens_34_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h23 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_34_T_2 & ~_ghv_wens_34_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h22 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h23 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h22 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h23 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_34_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_35_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_35_T_1 & ~_ghv_wens_35_T_2 & ~_ghv_wens_35_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h24
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_35_T & ~_ghv_wens_35_T_1 & ~_ghv_wens_35_T_2 & ~_ghv_wens_35_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h24 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_35_T_2 & ~_ghv_wens_35_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h23 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h24 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h23 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h24 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_35_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_36_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_36_T_1 & ~_ghv_wens_36_T_2 & ~_ghv_wens_36_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h25
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_36_T & ~_ghv_wens_36_T_1 & ~_ghv_wens_36_T_2 & ~_ghv_wens_36_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h25 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_36_T_2 & ~_ghv_wens_36_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h24 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h25 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h24 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h25 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_36_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_37_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_37_T_1 & ~_ghv_wens_37_T_2 & ~_ghv_wens_37_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h26
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_37_T & ~_ghv_wens_37_T_1 & ~_ghv_wens_37_T_2 & ~_ghv_wens_37_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h26 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_37_T_2 & ~_ghv_wens_37_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h25 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h26 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h25 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h26 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_37_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_38_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_38_T_1 & ~_ghv_wens_38_T_2 & ~_ghv_wens_38_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h27
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_38_T & ~_ghv_wens_38_T_1 & ~_ghv_wens_38_T_2 & ~_ghv_wens_38_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h27 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_38_T_2 & ~_ghv_wens_38_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h26 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h27 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h26 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h27 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_38_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_39_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_39_T_1 & ~_ghv_wens_39_T_2 & ~_ghv_wens_39_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h28
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_39_T & ~_ghv_wens_39_T_1 & ~_ghv_wens_39_T_2 & ~_ghv_wens_39_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h28 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_39_T_2 & ~_ghv_wens_39_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h27 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h28 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h27 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h28 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_39_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_40_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_40_T_1 & ~_ghv_wens_40_T_2 & ~_ghv_wens_40_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h29
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_40_T & ~_ghv_wens_40_T_1 & ~_ghv_wens_40_T_2 & ~_ghv_wens_40_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h29 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_40_T_2 & ~_ghv_wens_40_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h28 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h29 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h28 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h29 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_40_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_41_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_41_T_1 & ~_ghv_wens_41_T_2 & ~_ghv_wens_41_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h2A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_41_T & ~_ghv_wens_41_T_1 & ~_ghv_wens_41_T_2 & ~_ghv_wens_41_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h2A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_41_T_2 & ~_ghv_wens_41_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h29 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h2A & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h29 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2A & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_41_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_42_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_42_T_1 & ~_ghv_wens_42_T_2 & ~_ghv_wens_42_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h2B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_42_T & ~_ghv_wens_42_T_1 & ~_ghv_wens_42_T_2 & ~_ghv_wens_42_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h2B & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_42_T_2 & ~_ghv_wens_42_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h2A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h2B & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2A & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2B & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_42_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_43_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_43_T_1 & ~_ghv_wens_43_T_2 & ~_ghv_wens_43_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h2C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_43_T & ~_ghv_wens_43_T_1 & ~_ghv_wens_43_T_2 & ~_ghv_wens_43_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h2C & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_43_T_2 & ~_ghv_wens_43_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h2B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h2C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2B & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2C & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_43_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_44_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_44_T_1 & ~_ghv_wens_44_T_2 & ~_ghv_wens_44_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h2D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_44_T & ~_ghv_wens_44_T_1 & ~_ghv_wens_44_T_2 & ~_ghv_wens_44_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h2D & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_44_T_2 & ~_ghv_wens_44_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h2C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h2D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2C & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2D & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_44_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_45_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_45_T_1 & ~_ghv_wens_45_T_2 & ~_ghv_wens_45_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h2E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_45_T & ~_ghv_wens_45_T_1 & ~_ghv_wens_45_T_2 & ~_ghv_wens_45_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h2E & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_45_T_2 & ~_ghv_wens_45_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h2D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h2E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2D & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2E & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_45_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_46_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_46_T_1 & ~_ghv_wens_46_T_2 & ~_ghv_wens_46_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h2F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_46_T & ~_ghv_wens_46_T_1 & ~_ghv_wens_46_T_2 & ~_ghv_wens_46_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h2F & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_46_T_2 & ~_ghv_wens_46_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h2E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h2F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2E & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2F & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_46_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_47_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_47_T_1 & ~_ghv_wens_47_T_2 & ~_ghv_wens_47_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h30
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_47_T & ~_ghv_wens_47_T_1 & ~_ghv_wens_47_T_2 & ~_ghv_wens_47_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h30 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_47_T_2 & ~_ghv_wens_47_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h2F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h30 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h2F & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h30 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_47_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_48_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_48_T_1 & ~_ghv_wens_48_T_2 & ~_ghv_wens_48_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h31
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_48_T & ~_ghv_wens_48_T_1 & ~_ghv_wens_48_T_2 & ~_ghv_wens_48_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h31 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_48_T_2 & ~_ghv_wens_48_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h30 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h31 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h30 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h31 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_48_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_49_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_49_T_1 & ~_ghv_wens_49_T_2 & ~_ghv_wens_49_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h32
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_49_T & ~_ghv_wens_49_T_1 & ~_ghv_wens_49_T_2 & ~_ghv_wens_49_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h32 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_49_T_2 & ~_ghv_wens_49_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h31 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h32 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h31 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h32 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_49_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_50_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_50_T_1 & ~_ghv_wens_50_T_2 & ~_ghv_wens_50_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h33
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_50_T & ~_ghv_wens_50_T_1 & ~_ghv_wens_50_T_2 & ~_ghv_wens_50_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h33 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_50_T_2 & ~_ghv_wens_50_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h32 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h33 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h32 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h33 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_50_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_51_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_51_T_1 & ~_ghv_wens_51_T_2 & ~_ghv_wens_51_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h34
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_51_T & ~_ghv_wens_51_T_1 & ~_ghv_wens_51_T_2 & ~_ghv_wens_51_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h34 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_51_T_2 & ~_ghv_wens_51_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h33 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h34 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h33 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h34 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_51_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_52_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_52_T_1 & ~_ghv_wens_52_T_2 & ~_ghv_wens_52_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h35
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_52_T & ~_ghv_wens_52_T_1 & ~_ghv_wens_52_T_2 & ~_ghv_wens_52_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h35 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_52_T_2 & ~_ghv_wens_52_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h34 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h35 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h34 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h35 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_52_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_53_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_53_T_1 & ~_ghv_wens_53_T_2 & ~_ghv_wens_53_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h36
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_53_T & ~_ghv_wens_53_T_1 & ~_ghv_wens_53_T_2 & ~_ghv_wens_53_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h36 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_53_T_2 & ~_ghv_wens_53_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h35 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h36 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h35 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h36 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_53_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_54_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_54_T_1 & ~_ghv_wens_54_T_2 & ~_ghv_wens_54_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h37
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_54_T & ~_ghv_wens_54_T_1 & ~_ghv_wens_54_T_2 & ~_ghv_wens_54_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h37 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_54_T_2 & ~_ghv_wens_54_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h36 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h37 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h36 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h37 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_54_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_55_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_55_T_1 & ~_ghv_wens_55_T_2 & ~_ghv_wens_55_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h38
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_55_T & ~_ghv_wens_55_T_1 & ~_ghv_wens_55_T_2 & ~_ghv_wens_55_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h38 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_55_T_2 & ~_ghv_wens_55_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h37 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h38 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h37 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h38 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_55_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_56_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_56_T_1 & ~_ghv_wens_56_T_2 & ~_ghv_wens_56_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h39
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_56_T & ~_ghv_wens_56_T_1 & ~_ghv_wens_56_T_2 & ~_ghv_wens_56_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h39 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_56_T_2 & ~_ghv_wens_56_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h38 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h39 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h38 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h39 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_56_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_57_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_57_T_1 & ~_ghv_wens_57_T_2 & ~_ghv_wens_57_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h3A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_57_T & ~_ghv_wens_57_T_1 & ~_ghv_wens_57_T_2 & ~_ghv_wens_57_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h3A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_57_T_2 & ~_ghv_wens_57_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h39 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h3A & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h39 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3A & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_57_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_58_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_58_T_1 & ~_ghv_wens_58_T_2 & ~_ghv_wens_58_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h3B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_58_T & ~_ghv_wens_58_T_1 & ~_ghv_wens_58_T_2 & ~_ghv_wens_58_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h3B & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_58_T_2 & ~_ghv_wens_58_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h3A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h3B & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3A & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3B & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_58_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_59_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_59_T_1 & ~_ghv_wens_59_T_2 & ~_ghv_wens_59_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h3C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_59_T & ~_ghv_wens_59_T_1 & ~_ghv_wens_59_T_2 & ~_ghv_wens_59_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h3C & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_59_T_2 & ~_ghv_wens_59_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h3B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h3C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3B & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3C & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_59_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_60_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_60_T_1 & ~_ghv_wens_60_T_2 & ~_ghv_wens_60_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h3D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_60_T & ~_ghv_wens_60_T_1 & ~_ghv_wens_60_T_2 & ~_ghv_wens_60_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h3D & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_60_T_2 & ~_ghv_wens_60_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h3C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h3D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3C & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3D & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_60_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_61_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_61_T_1 & ~_ghv_wens_61_T_2 & ~_ghv_wens_61_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h3E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_61_T & ~_ghv_wens_61_T_1 & ~_ghv_wens_61_T_2 & ~_ghv_wens_61_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h3E & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_61_T_2 & ~_ghv_wens_61_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h3D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h3E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3D & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3E & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_61_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_62_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_62_T_1 & ~_ghv_wens_62_T_2 & ~_ghv_wens_62_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h3F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_62_T & ~_ghv_wens_62_T_1 & ~_ghv_wens_62_T_2 & ~_ghv_wens_62_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h3F & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_62_T_2 & ~_ghv_wens_62_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h3E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h3F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3E & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3F & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_62_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_63_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_63_T_1 & ~_ghv_wens_63_T_2 & ~_ghv_wens_63_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h40
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_63_T & ~_ghv_wens_63_T_1 & ~_ghv_wens_63_T_2 & ~_ghv_wens_63_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h40 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_63_T_2 & ~_ghv_wens_63_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h3F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h40 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h3F & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h40 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_63_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_64_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_64_T_1 & ~_ghv_wens_64_T_2 & ~_ghv_wens_64_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h41
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_64_T & ~_ghv_wens_64_T_1 & ~_ghv_wens_64_T_2 & ~_ghv_wens_64_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h41 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_64_T_2 & ~_ghv_wens_64_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h40 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h41 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h40 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h41 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_64_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_65_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_65_T_1 & ~_ghv_wens_65_T_2 & ~_ghv_wens_65_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h42
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_65_T & ~_ghv_wens_65_T_1 & ~_ghv_wens_65_T_2 & ~_ghv_wens_65_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h42 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_65_T_2 & ~_ghv_wens_65_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h41 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h42 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h41 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h42 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_65_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_66_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_66_T_1 & ~_ghv_wens_66_T_2 & ~_ghv_wens_66_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h43
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_66_T & ~_ghv_wens_66_T_1 & ~_ghv_wens_66_T_2 & ~_ghv_wens_66_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h43 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_66_T_2 & ~_ghv_wens_66_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h42 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h43 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h42 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h43 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_66_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_67_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_67_T_1 & ~_ghv_wens_67_T_2 & ~_ghv_wens_67_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h44
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_67_T & ~_ghv_wens_67_T_1 & ~_ghv_wens_67_T_2 & ~_ghv_wens_67_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h44 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_67_T_2 & ~_ghv_wens_67_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h43 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h44 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h43 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h44 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_67_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_68_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_68_T_1 & ~_ghv_wens_68_T_2 & ~_ghv_wens_68_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h45
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_68_T & ~_ghv_wens_68_T_1 & ~_ghv_wens_68_T_2 & ~_ghv_wens_68_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h45 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_68_T_2 & ~_ghv_wens_68_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h44 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h45 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h44 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h45 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_68_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_69_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_69_T_1 & ~_ghv_wens_69_T_2 & ~_ghv_wens_69_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h46
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_69_T & ~_ghv_wens_69_T_1 & ~_ghv_wens_69_T_2 & ~_ghv_wens_69_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h46 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_69_T_2 & ~_ghv_wens_69_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h45 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h46 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h45 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h46 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_69_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_70_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_70_T_1 & ~_ghv_wens_70_T_2 & ~_ghv_wens_70_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h47
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_70_T & ~_ghv_wens_70_T_1 & ~_ghv_wens_70_T_2 & ~_ghv_wens_70_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h47 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_70_T_2 & ~_ghv_wens_70_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h46 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h47 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h46 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h47 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_70_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_71_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_71_T_1 & ~_ghv_wens_71_T_2 & ~_ghv_wens_71_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h48
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_71_T & ~_ghv_wens_71_T_1 & ~_ghv_wens_71_T_2 & ~_ghv_wens_71_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h48 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_71_T_2 & ~_ghv_wens_71_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h47 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h48 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h47 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h48 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_71_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_72_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_72_T_1 & ~_ghv_wens_72_T_2 & ~_ghv_wens_72_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h49
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_72_T & ~_ghv_wens_72_T_1 & ~_ghv_wens_72_T_2 & ~_ghv_wens_72_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h49 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_72_T_2 & ~_ghv_wens_72_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h48 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h49 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h48 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h49 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_72_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_73_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_73_T_1 & ~_ghv_wens_73_T_2 & ~_ghv_wens_73_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h4A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_73_T & ~_ghv_wens_73_T_1 & ~_ghv_wens_73_T_2 & ~_ghv_wens_73_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h4A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_73_T_2 & ~_ghv_wens_73_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h49 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h4A & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h49 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4A & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_73_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_74_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_74_T_1 & ~_ghv_wens_74_T_2 & ~_ghv_wens_74_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h4B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_74_T & ~_ghv_wens_74_T_1 & ~_ghv_wens_74_T_2 & ~_ghv_wens_74_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h4B & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_74_T_2 & ~_ghv_wens_74_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h4A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h4B & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4A & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4B & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_74_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_75_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_75_T_1 & ~_ghv_wens_75_T_2 & ~_ghv_wens_75_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h4C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_75_T & ~_ghv_wens_75_T_1 & ~_ghv_wens_75_T_2 & ~_ghv_wens_75_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h4C & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_75_T_2 & ~_ghv_wens_75_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h4B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h4C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4B & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4C & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_75_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_76_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_76_T_1 & ~_ghv_wens_76_T_2 & ~_ghv_wens_76_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h4D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_76_T & ~_ghv_wens_76_T_1 & ~_ghv_wens_76_T_2 & ~_ghv_wens_76_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h4D & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_76_T_2 & ~_ghv_wens_76_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h4C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h4D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4C & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4D & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_76_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_77_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_77_T_1 & ~_ghv_wens_77_T_2 & ~_ghv_wens_77_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h4E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_77_T & ~_ghv_wens_77_T_1 & ~_ghv_wens_77_T_2 & ~_ghv_wens_77_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h4E & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_77_T_2 & ~_ghv_wens_77_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h4D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h4E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4D & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4E & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_77_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_78_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_78_T_1 & ~_ghv_wens_78_T_2 & ~_ghv_wens_78_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h4F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_78_T & ~_ghv_wens_78_T_1 & ~_ghv_wens_78_T_2 & ~_ghv_wens_78_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h4F & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_78_T_2 & ~_ghv_wens_78_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h4E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h4F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4E & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4F & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_78_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_79_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_79_T_1 & ~_ghv_wens_79_T_2 & ~_ghv_wens_79_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h50
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_79_T & ~_ghv_wens_79_T_1 & ~_ghv_wens_79_T_2 & ~_ghv_wens_79_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h50 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_79_T_2 & ~_ghv_wens_79_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h4F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h50 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h4F & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h50 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_79_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_80_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_80_T_1 & ~_ghv_wens_80_T_2 & ~_ghv_wens_80_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h51
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_80_T & ~_ghv_wens_80_T_1 & ~_ghv_wens_80_T_2 & ~_ghv_wens_80_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h51 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_80_T_2 & ~_ghv_wens_80_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h50 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h51 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h50 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h51 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_80_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_81_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_81_T_1 & ~_ghv_wens_81_T_2 & ~_ghv_wens_81_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h52
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_81_T & ~_ghv_wens_81_T_1 & ~_ghv_wens_81_T_2 & ~_ghv_wens_81_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h52 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_81_T_2 & ~_ghv_wens_81_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h51 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h52 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h51 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h52 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_81_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_82_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_82_T_1 & ~_ghv_wens_82_T_2 & ~_ghv_wens_82_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h53
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_82_T & ~_ghv_wens_82_T_1 & ~_ghv_wens_82_T_2 & ~_ghv_wens_82_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h53 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_82_T_2 & ~_ghv_wens_82_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h52 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h53 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h52 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h53 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_82_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_83_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_83_T_1 & ~_ghv_wens_83_T_2 & ~_ghv_wens_83_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h54
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_83_T & ~_ghv_wens_83_T_1 & ~_ghv_wens_83_T_2 & ~_ghv_wens_83_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h54 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_83_T_2 & ~_ghv_wens_83_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h53 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h54 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h53 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h54 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_83_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_84_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_84_T_1 & ~_ghv_wens_84_T_2 & ~_ghv_wens_84_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h55
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_84_T & ~_ghv_wens_84_T_1 & ~_ghv_wens_84_T_2 & ~_ghv_wens_84_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h55 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_84_T_2 & ~_ghv_wens_84_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h54 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h55 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h54 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h55 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_84_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_85_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_85_T_1 & ~_ghv_wens_85_T_2 & ~_ghv_wens_85_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h56
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_85_T & ~_ghv_wens_85_T_1 & ~_ghv_wens_85_T_2 & ~_ghv_wens_85_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h56 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_85_T_2 & ~_ghv_wens_85_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h55 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h56 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h55 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h56 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_85_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_86_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_86_T_1 & ~_ghv_wens_86_T_2 & ~_ghv_wens_86_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h57
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_86_T & ~_ghv_wens_86_T_1 & ~_ghv_wens_86_T_2 & ~_ghv_wens_86_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h57 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_86_T_2 & ~_ghv_wens_86_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h56 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h57 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h56 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h57 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_86_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_87_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_87_T_1 & ~_ghv_wens_87_T_2 & ~_ghv_wens_87_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h58
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_87_T & ~_ghv_wens_87_T_1 & ~_ghv_wens_87_T_2 & ~_ghv_wens_87_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h58 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_87_T_2 & ~_ghv_wens_87_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h57 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h58 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h57 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h58 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_87_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_88_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_88_T_1 & ~_ghv_wens_88_T_2 & ~_ghv_wens_88_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h59
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_88_T & ~_ghv_wens_88_T_1 & ~_ghv_wens_88_T_2 & ~_ghv_wens_88_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h59 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_88_T_2 & ~_ghv_wens_88_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h58 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h59 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h58 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h59 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_88_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_89_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_89_T_1 & ~_ghv_wens_89_T_2 & ~_ghv_wens_89_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h5A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_89_T & ~_ghv_wens_89_T_1 & ~_ghv_wens_89_T_2 & ~_ghv_wens_89_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h5A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_89_T_2 & ~_ghv_wens_89_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h59 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h5A & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h59 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5A & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_89_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_90_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_90_T_1 & ~_ghv_wens_90_T_2 & ~_ghv_wens_90_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h5B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_90_T & ~_ghv_wens_90_T_1 & ~_ghv_wens_90_T_2 & ~_ghv_wens_90_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h5B & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_90_T_2 & ~_ghv_wens_90_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h5A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h5B & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5A & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5B & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_90_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_91_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_91_T_1 & ~_ghv_wens_91_T_2 & ~_ghv_wens_91_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h5C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_91_T & ~_ghv_wens_91_T_1 & ~_ghv_wens_91_T_2 & ~_ghv_wens_91_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h5C & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_91_T_2 & ~_ghv_wens_91_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h5B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h5C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5B & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5C & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_91_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_92_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_92_T_1 & ~_ghv_wens_92_T_2 & ~_ghv_wens_92_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h5D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_92_T & ~_ghv_wens_92_T_1 & ~_ghv_wens_92_T_2 & ~_ghv_wens_92_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h5D & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_92_T_2 & ~_ghv_wens_92_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h5C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h5D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5C & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5D & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_92_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_93_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_93_T_1 & ~_ghv_wens_93_T_2 & ~_ghv_wens_93_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h5E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_93_T & ~_ghv_wens_93_T_1 & ~_ghv_wens_93_T_2 & ~_ghv_wens_93_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h5E & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_93_T_2 & ~_ghv_wens_93_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h5D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h5E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5D & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5E & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_93_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_94_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_94_T_1 & ~_ghv_wens_94_T_2 & ~_ghv_wens_94_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h5F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_94_T & ~_ghv_wens_94_T_1 & ~_ghv_wens_94_T_2 & ~_ghv_wens_94_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h5F & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_94_T_2 & ~_ghv_wens_94_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h5E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h5F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5E & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5F & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_94_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_95_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_95_T_1 & ~_ghv_wens_95_T_2 & ~_ghv_wens_95_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h60
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_95_T & ~_ghv_wens_95_T_1 & ~_ghv_wens_95_T_2 & ~_ghv_wens_95_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h60 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_95_T_2 & ~_ghv_wens_95_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h5F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h60 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h5F & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h60 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_95_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_96_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_96_T_1 & ~_ghv_wens_96_T_2 & ~_ghv_wens_96_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h61
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_96_T & ~_ghv_wens_96_T_1 & ~_ghv_wens_96_T_2 & ~_ghv_wens_96_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h61 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_96_T_2 & ~_ghv_wens_96_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h60 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h61 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h60 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h61 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_96_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_97_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_97_T_1 & ~_ghv_wens_97_T_2 & ~_ghv_wens_97_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h62
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_97_T & ~_ghv_wens_97_T_1 & ~_ghv_wens_97_T_2 & ~_ghv_wens_97_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h62 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_97_T_2 & ~_ghv_wens_97_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h61 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h62 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h61 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h62 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_97_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_98_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_98_T_1 & ~_ghv_wens_98_T_2 & ~_ghv_wens_98_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h63
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_98_T & ~_ghv_wens_98_T_1 & ~_ghv_wens_98_T_2 & ~_ghv_wens_98_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h63 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_98_T_2 & ~_ghv_wens_98_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h62 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h63 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h62 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h63 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_98_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_99_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_99_T_1 & ~_ghv_wens_99_T_2 & ~_ghv_wens_99_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h64
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_99_T & ~_ghv_wens_99_T_1 & ~_ghv_wens_99_T_2 & ~_ghv_wens_99_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h64 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_99_T_2 & ~_ghv_wens_99_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h63 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h64 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h63 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h64 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_99_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_100_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_100_T_1 & ~_ghv_wens_100_T_2 & ~_ghv_wens_100_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h65
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_100_T & ~_ghv_wens_100_T_1 & ~_ghv_wens_100_T_2 & ~_ghv_wens_100_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h65 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_100_T_2 & ~_ghv_wens_100_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h64 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h65 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h64 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h65 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_100_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_101_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_101_T_1 & ~_ghv_wens_101_T_2 & ~_ghv_wens_101_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h66
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_101_T & ~_ghv_wens_101_T_1 & ~_ghv_wens_101_T_2 & ~_ghv_wens_101_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h66 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_101_T_2 & ~_ghv_wens_101_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h65 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h66 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h65 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h66 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_101_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_102_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_102_T_1 & ~_ghv_wens_102_T_2 & ~_ghv_wens_102_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h67
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_102_T & ~_ghv_wens_102_T_1 & ~_ghv_wens_102_T_2 & ~_ghv_wens_102_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h67 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_102_T_2 & ~_ghv_wens_102_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h66 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h67 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h66 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h67 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_102_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_103_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_103_T_1 & ~_ghv_wens_103_T_2 & ~_ghv_wens_103_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h68
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_103_T & ~_ghv_wens_103_T_1 & ~_ghv_wens_103_T_2 & ~_ghv_wens_103_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h68 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_103_T_2 & ~_ghv_wens_103_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h67 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h68 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h67 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h68 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_103_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_104_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_104_T_1 & ~_ghv_wens_104_T_2 & ~_ghv_wens_104_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h69
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_104_T & ~_ghv_wens_104_T_1 & ~_ghv_wens_104_T_2 & ~_ghv_wens_104_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h69 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_104_T_2 & ~_ghv_wens_104_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h68 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h69 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h68 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h69 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_104_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_105_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_105_T_1 & ~_ghv_wens_105_T_2 & ~_ghv_wens_105_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h6A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_105_T & ~_ghv_wens_105_T_1 & ~_ghv_wens_105_T_2 & ~_ghv_wens_105_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h6A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_105_T_2 & ~_ghv_wens_105_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h69 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h6A & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h69 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6A & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_105_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_106_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_106_T_1 & ~_ghv_wens_106_T_2 & ~_ghv_wens_106_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h6B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_106_T & ~_ghv_wens_106_T_1 & ~_ghv_wens_106_T_2 & ~_ghv_wens_106_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h6B & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_106_T_2 & ~_ghv_wens_106_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h6A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h6B & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6A & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6B & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_106_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_107_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_107_T_1 & ~_ghv_wens_107_T_2 & ~_ghv_wens_107_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h6C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_107_T & ~_ghv_wens_107_T_1 & ~_ghv_wens_107_T_2 & ~_ghv_wens_107_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h6C & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_107_T_2 & ~_ghv_wens_107_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h6B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h6C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6B & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6C & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_107_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_108_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_108_T_1 & ~_ghv_wens_108_T_2 & ~_ghv_wens_108_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h6D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_108_T & ~_ghv_wens_108_T_1 & ~_ghv_wens_108_T_2 & ~_ghv_wens_108_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h6D & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_108_T_2 & ~_ghv_wens_108_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h6C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h6D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6C & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6D & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_108_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_109_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_109_T_1 & ~_ghv_wens_109_T_2 & ~_ghv_wens_109_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h6E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_109_T & ~_ghv_wens_109_T_1 & ~_ghv_wens_109_T_2 & ~_ghv_wens_109_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h6E & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_109_T_2 & ~_ghv_wens_109_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h6D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h6E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6D & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6E & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_109_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_110_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_110_T_1 & ~_ghv_wens_110_T_2 & ~_ghv_wens_110_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h6F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_110_T & ~_ghv_wens_110_T_1 & ~_ghv_wens_110_T_2 & ~_ghv_wens_110_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h6F & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_110_T_2 & ~_ghv_wens_110_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h6E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h6F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6E & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6F & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_110_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_111_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_111_T_1 & ~_ghv_wens_111_T_2 & ~_ghv_wens_111_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h70
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_111_T & ~_ghv_wens_111_T_1 & ~_ghv_wens_111_T_2 & ~_ghv_wens_111_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h70 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_111_T_2 & ~_ghv_wens_111_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h6F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h70 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h6F & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h70 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_111_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_112_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_112_T_1 & ~_ghv_wens_112_T_2 & ~_ghv_wens_112_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h71
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_112_T & ~_ghv_wens_112_T_1 & ~_ghv_wens_112_T_2 & ~_ghv_wens_112_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h71 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_112_T_2 & ~_ghv_wens_112_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h70 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h71 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h70 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h71 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_112_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_113_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_113_T_1 & ~_ghv_wens_113_T_2 & ~_ghv_wens_113_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h72
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_113_T & ~_ghv_wens_113_T_1 & ~_ghv_wens_113_T_2 & ~_ghv_wens_113_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h72 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_113_T_2 & ~_ghv_wens_113_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h71 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h72 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h71 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h72 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_113_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_114_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_114_T_1 & ~_ghv_wens_114_T_2 & ~_ghv_wens_114_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h73
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_114_T & ~_ghv_wens_114_T_1 & ~_ghv_wens_114_T_2 & ~_ghv_wens_114_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h73 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_114_T_2 & ~_ghv_wens_114_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h72 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h73 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h72 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h73 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_114_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_115_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_115_T_1 & ~_ghv_wens_115_T_2 & ~_ghv_wens_115_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h74
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_115_T & ~_ghv_wens_115_T_1 & ~_ghv_wens_115_T_2 & ~_ghv_wens_115_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h74 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_115_T_2 & ~_ghv_wens_115_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h73 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h74 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h73 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h74 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_115_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_116_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_116_T_1 & ~_ghv_wens_116_T_2 & ~_ghv_wens_116_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h75
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_116_T & ~_ghv_wens_116_T_1 & ~_ghv_wens_116_T_2 & ~_ghv_wens_116_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h75 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_116_T_2 & ~_ghv_wens_116_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h74 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h75 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h74 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h75 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_116_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_117_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_117_T_1 & ~_ghv_wens_117_T_2 & ~_ghv_wens_117_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h76
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_117_T & ~_ghv_wens_117_T_1 & ~_ghv_wens_117_T_2 & ~_ghv_wens_117_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h76 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_117_T_2 & ~_ghv_wens_117_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h75 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h76 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h75 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h76 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_117_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_118_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_118_T_1 & ~_ghv_wens_118_T_2 & ~_ghv_wens_118_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h77
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_118_T & ~_ghv_wens_118_T_1 & ~_ghv_wens_118_T_2 & ~_ghv_wens_118_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h77 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_118_T_2 & ~_ghv_wens_118_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h76 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h77 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h76 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h77 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_118_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_119_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_119_T_1 & ~_ghv_wens_119_T_2 & ~_ghv_wens_119_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h78
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_119_T & ~_ghv_wens_119_T_1 & ~_ghv_wens_119_T_2 & ~_ghv_wens_119_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h78 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_119_T_2 & ~_ghv_wens_119_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h77 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h78 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h77 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h78 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_119_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_120_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_120_T_1 & ~_ghv_wens_120_T_2 & ~_ghv_wens_120_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h79
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_120_T & ~_ghv_wens_120_T_1 & ~_ghv_wens_120_T_2 & ~_ghv_wens_120_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h79 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_120_T_2 & ~_ghv_wens_120_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h78 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h79 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h78 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h79 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_120_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_121_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_121_T_1 & ~_ghv_wens_121_T_2 & ~_ghv_wens_121_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h7A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_121_T & ~_ghv_wens_121_T_1 & ~_ghv_wens_121_T_2 & ~_ghv_wens_121_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h7A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_121_T_2 & ~_ghv_wens_121_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h79 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h7A & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h79 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7A & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_121_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_122_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_122_T_1 & ~_ghv_wens_122_T_2 & ~_ghv_wens_122_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h7B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_122_T & ~_ghv_wens_122_T_1 & ~_ghv_wens_122_T_2 & ~_ghv_wens_122_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h7B & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_122_T_2 & ~_ghv_wens_122_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h7A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h7B & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7A & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7B & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_122_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_123_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_123_T_1 & ~_ghv_wens_123_T_2 & ~_ghv_wens_123_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h7C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_123_T & ~_ghv_wens_123_T_1 & ~_ghv_wens_123_T_2 & ~_ghv_wens_123_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h7C & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_123_T_2 & ~_ghv_wens_123_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h7B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h7C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7B & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7C & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_123_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_124_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_124_T_1 & ~_ghv_wens_124_T_2 & ~_ghv_wens_124_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h7D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_124_T & ~_ghv_wens_124_T_1 & ~_ghv_wens_124_T_2 & ~_ghv_wens_124_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h7D & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_124_T_2 & ~_ghv_wens_124_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h7C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h7D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7C & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7D & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_124_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_125_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_125_T_1 & ~_ghv_wens_125_T_2 & ~_ghv_wens_125_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h7E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_125_T & ~_ghv_wens_125_T_1 & ~_ghv_wens_125_T_2 & ~_ghv_wens_125_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h7E & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_125_T_2 & ~_ghv_wens_125_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h7D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h7E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7D & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7E & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_125_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_126_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_126_T_1 & ~_ghv_wens_126_T_2 & ~_ghv_wens_126_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h7F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_126_T & ~_ghv_wens_126_T_1 & ~_ghv_wens_126_T_2 & ~_ghv_wens_126_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h7F & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_126_T_2 & ~_ghv_wens_126_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h7E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h7F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7E & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7F & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_126_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_127_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_127_T_1 & ~_ghv_wens_127_T_2 & ~_ghv_wens_127_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h80
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_127_T & ~_ghv_wens_127_T_1 & ~_ghv_wens_127_T_2 & ~_ghv_wens_127_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h80 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_127_T_2 & ~_ghv_wens_127_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h7F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h80 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h7F & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h80 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_127_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_128_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_128_T_1 & ~_ghv_wens_128_T_2 & ~_ghv_wens_128_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h81
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_128_T & ~_ghv_wens_128_T_1 & ~_ghv_wens_128_T_2 & ~_ghv_wens_128_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h81 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_128_T_2 & ~_ghv_wens_128_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h80 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h81 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h80 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h81 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_128_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_129_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_129_T_1 & ~_ghv_wens_129_T_2 & ~_ghv_wens_129_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h82
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_129_T & ~_ghv_wens_129_T_1 & ~_ghv_wens_129_T_2 & ~_ghv_wens_129_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h82 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_129_T_2 & ~_ghv_wens_129_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h81 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h82 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h81 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h82 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_129_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_130_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_130_T_1 & ~_ghv_wens_130_T_2 & ~_ghv_wens_130_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h83
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_130_T & ~_ghv_wens_130_T_1 & ~_ghv_wens_130_T_2 & ~_ghv_wens_130_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h83 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_130_T_2 & ~_ghv_wens_130_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h82 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h83 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h82 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h83 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_130_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_131_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_131_T_1 & ~_ghv_wens_131_T_2 & ~_ghv_wens_131_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h84
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_131_T & ~_ghv_wens_131_T_1 & ~_ghv_wens_131_T_2 & ~_ghv_wens_131_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h84 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_131_T_2 & ~_ghv_wens_131_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h83 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h84 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h83 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h84 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_131_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_132_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_132_T_1 & ~_ghv_wens_132_T_2 & ~_ghv_wens_132_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h85
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_132_T & ~_ghv_wens_132_T_1 & ~_ghv_wens_132_T_2 & ~_ghv_wens_132_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h85 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_132_T_2 & ~_ghv_wens_132_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h84 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h85 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h84 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h85 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_132_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_133_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_133_T_1 & ~_ghv_wens_133_T_2 & ~_ghv_wens_133_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h86
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_133_T & ~_ghv_wens_133_T_1 & ~_ghv_wens_133_T_2 & ~_ghv_wens_133_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h86 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_133_T_2 & ~_ghv_wens_133_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h85 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h86 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h85 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h86 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_133_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_134_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_134_T_1 & ~_ghv_wens_134_T_2 & ~_ghv_wens_134_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h87
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_134_T & ~_ghv_wens_134_T_1 & ~_ghv_wens_134_T_2 & ~_ghv_wens_134_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h87 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_134_T_2 & ~_ghv_wens_134_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h86 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h87 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h86 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h87 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_134_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_135_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_135_T_1 & ~_ghv_wens_135_T_2 & ~_ghv_wens_135_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h88
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_135_T & ~_ghv_wens_135_T_1 & ~_ghv_wens_135_T_2 & ~_ghv_wens_135_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h88 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_135_T_2 & ~_ghv_wens_135_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h87 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h88 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h87 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h88 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_135_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_136_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_136_T_1 & ~_ghv_wens_136_T_2 & ~_ghv_wens_136_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h89
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_136_T & ~_ghv_wens_136_T_1 & ~_ghv_wens_136_T_2 & ~_ghv_wens_136_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h89 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_136_T_2 & ~_ghv_wens_136_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h88 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h89 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h88 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h89 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_136_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_137_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_137_T_1 & ~_ghv_wens_137_T_2 & ~_ghv_wens_137_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h8A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_137_T & ~_ghv_wens_137_T_1 & ~_ghv_wens_137_T_2 & ~_ghv_wens_137_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h8A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_137_T_2 & ~_ghv_wens_137_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h89 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h8A & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h89 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8A & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_137_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_138_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_138_T_1 & ~_ghv_wens_138_T_2 & ~_ghv_wens_138_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h8B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_138_T & ~_ghv_wens_138_T_1 & ~_ghv_wens_138_T_2 & ~_ghv_wens_138_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h8B & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_138_T_2 & ~_ghv_wens_138_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h8A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h8B & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8A & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8B & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_138_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_139_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_139_T_1 & ~_ghv_wens_139_T_2 & ~_ghv_wens_139_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h8C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_139_T & ~_ghv_wens_139_T_1 & ~_ghv_wens_139_T_2 & ~_ghv_wens_139_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h8C & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_139_T_2 & ~_ghv_wens_139_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h8B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h8C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8B & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8C & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_139_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_140_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_140_T_1 & ~_ghv_wens_140_T_2 & ~_ghv_wens_140_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h8D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_140_T & ~_ghv_wens_140_T_1 & ~_ghv_wens_140_T_2 & ~_ghv_wens_140_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h8D & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_140_T_2 & ~_ghv_wens_140_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h8C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h8D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8C & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8D & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_140_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_141_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_141_T_1 & ~_ghv_wens_141_T_2 & ~_ghv_wens_141_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h8E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_141_T & ~_ghv_wens_141_T_1 & ~_ghv_wens_141_T_2 & ~_ghv_wens_141_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h8E & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_141_T_2 & ~_ghv_wens_141_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h8D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h8E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8D & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8E & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_141_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_142_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_142_T_1 & ~_ghv_wens_142_T_2 & ~_ghv_wens_142_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h8F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_142_T & ~_ghv_wens_142_T_1 & ~_ghv_wens_142_T_2 & ~_ghv_wens_142_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h8F & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_142_T_2 & ~_ghv_wens_142_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h8E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h8F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8E & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8F & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_142_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_143_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_143_T_1 & ~_ghv_wens_143_T_2 & ~_ghv_wens_143_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h90
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_143_T & ~_ghv_wens_143_T_1 & ~_ghv_wens_143_T_2 & ~_ghv_wens_143_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h90 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_143_T_2 & ~_ghv_wens_143_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h8F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h90 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h8F & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h90 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_143_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_144_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_144_T_1 & ~_ghv_wens_144_T_2 & ~_ghv_wens_144_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h91
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_144_T & ~_ghv_wens_144_T_1 & ~_ghv_wens_144_T_2 & ~_ghv_wens_144_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h91 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_144_T_2 & ~_ghv_wens_144_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h90 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h91 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h90 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h91 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_144_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_145_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_145_T_1 & ~_ghv_wens_145_T_2 & ~_ghv_wens_145_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h92
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_145_T & ~_ghv_wens_145_T_1 & ~_ghv_wens_145_T_2 & ~_ghv_wens_145_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h92 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_145_T_2 & ~_ghv_wens_145_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h91 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h92 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h91 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h92 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_145_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_146_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_146_T_1 & ~_ghv_wens_146_T_2 & ~_ghv_wens_146_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h93
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_146_T & ~_ghv_wens_146_T_1 & ~_ghv_wens_146_T_2 & ~_ghv_wens_146_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h93 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_146_T_2 & ~_ghv_wens_146_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h92 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h93 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h92 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h93 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_146_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_147_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_147_T_1 & ~_ghv_wens_147_T_2 & ~_ghv_wens_147_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h94
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_147_T & ~_ghv_wens_147_T_1 & ~_ghv_wens_147_T_2 & ~_ghv_wens_147_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h94 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_147_T_2 & ~_ghv_wens_147_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h93 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h94 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h93 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h94 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_147_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_148_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_148_T_1 & ~_ghv_wens_148_T_2 & ~_ghv_wens_148_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h95
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_148_T & ~_ghv_wens_148_T_1 & ~_ghv_wens_148_T_2 & ~_ghv_wens_148_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h95 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_148_T_2 & ~_ghv_wens_148_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h94 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h95 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h94 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h95 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_148_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_149_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_149_T_1 & ~_ghv_wens_149_T_2 & ~_ghv_wens_149_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h96
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_149_T & ~_ghv_wens_149_T_1 & ~_ghv_wens_149_T_2 & ~_ghv_wens_149_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h96 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_149_T_2 & ~_ghv_wens_149_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h95 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h96 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h95 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h96 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_149_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_150_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_150_T_1 & ~_ghv_wens_150_T_2 & ~_ghv_wens_150_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h97
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_150_T & ~_ghv_wens_150_T_1 & ~_ghv_wens_150_T_2 & ~_ghv_wens_150_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h97 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_150_T_2 & ~_ghv_wens_150_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h96 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h97 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h96 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h97 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_150_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_151_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_151_T_1 & ~_ghv_wens_151_T_2 & ~_ghv_wens_151_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h98
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_151_T & ~_ghv_wens_151_T_1 & ~_ghv_wens_151_T_2 & ~_ghv_wens_151_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h98 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_151_T_2 & ~_ghv_wens_151_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h97 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h98 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h97 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h98 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_151_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_152_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_152_T_1 & ~_ghv_wens_152_T_2 & ~_ghv_wens_152_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h99
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_152_T & ~_ghv_wens_152_T_1 & ~_ghv_wens_152_T_2 & ~_ghv_wens_152_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h99 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_152_T_2 & ~_ghv_wens_152_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h98 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h99 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h98 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h99 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_152_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_153_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_153_T_1 & ~_ghv_wens_153_T_2 & ~_ghv_wens_153_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h9A
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_153_T & ~_ghv_wens_153_T_1 & ~_ghv_wens_153_T_2 & ~_ghv_wens_153_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h9A & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_153_T_2 & ~_ghv_wens_153_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h99 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h9A & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h99 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9A & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_153_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_154_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_154_T_1 & ~_ghv_wens_154_T_2 & ~_ghv_wens_154_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h9B
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_154_T & ~_ghv_wens_154_T_1 & ~_ghv_wens_154_T_2 & ~_ghv_wens_154_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h9B & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_154_T_2 & ~_ghv_wens_154_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h9A & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h9B & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9A & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9B & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_154_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_155_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_155_T_1 & ~_ghv_wens_155_T_2 & ~_ghv_wens_155_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h9C
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_155_T & ~_ghv_wens_155_T_1 & ~_ghv_wens_155_T_2 & ~_ghv_wens_155_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h9C & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_155_T_2 & ~_ghv_wens_155_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h9B & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h9C & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9B & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9C & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_155_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_156_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_156_T_1 & ~_ghv_wens_156_T_2 & ~_ghv_wens_156_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h9D
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_156_T & ~_ghv_wens_156_T_1 & ~_ghv_wens_156_T_2 & ~_ghv_wens_156_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h9D & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_156_T_2 & ~_ghv_wens_156_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h9C & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h9D & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9C & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9D & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_156_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_157_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_157_T_1 & ~_ghv_wens_157_T_2 & ~_ghv_wens_157_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h9E
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_157_T & ~_ghv_wens_157_T_1 & ~_ghv_wens_157_T_2 & ~_ghv_wens_157_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h9E & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_157_T_2 & ~_ghv_wens_157_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h9D & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h9E & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9D & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9E & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_157_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_158_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_158_T_1 & ~_ghv_wens_158_T_2 & ~_ghv_wens_158_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'h9F
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_158_T & ~_ghv_wens_158_T_1 & ~_ghv_wens_158_T_2 & ~_ghv_wens_158_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'h9F & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_158_T_2 & ~_ghv_wens_158_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h9E & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'h9F & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9E & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9F & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_158_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_159_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_159_T_1 & ~_ghv_wens_159_T_2 & ~_ghv_wens_159_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hA0
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_159_T & ~_ghv_wens_159_T_1 & ~_ghv_wens_159_T_2 & ~_ghv_wens_159_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hA0 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_159_T_2 & ~_ghv_wens_159_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'h9F & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hA0 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'h9F & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA0 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_159_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_160_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_160_T_1 & ~_ghv_wens_160_T_2 & ~_ghv_wens_160_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hA1
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_160_T & ~_ghv_wens_160_T_1 & ~_ghv_wens_160_T_2 & ~_ghv_wens_160_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hA1 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_160_T_2 & ~_ghv_wens_160_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hA0 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hA1 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA0 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA1 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_160_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_161_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_161_T_1 & ~_ghv_wens_161_T_2 & ~_ghv_wens_161_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hA2
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_161_T & ~_ghv_wens_161_T_1 & ~_ghv_wens_161_T_2 & ~_ghv_wens_161_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hA2 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_161_T_2 & ~_ghv_wens_161_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hA1 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hA2 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA1 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA2 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_161_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_162_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_162_T_1 & ~_ghv_wens_162_T_2 & ~_ghv_wens_162_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hA3
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_162_T & ~_ghv_wens_162_T_1 & ~_ghv_wens_162_T_2 & ~_ghv_wens_162_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hA3 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_162_T_2 & ~_ghv_wens_162_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hA2 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hA3 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA2 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA3 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_162_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_163_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_163_T_1 & ~_ghv_wens_163_T_2 & ~_ghv_wens_163_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hA4
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_163_T & ~_ghv_wens_163_T_1 & ~_ghv_wens_163_T_2 & ~_ghv_wens_163_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hA4 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_163_T_2 & ~_ghv_wens_163_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hA3 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hA4 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA3 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA4 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_163_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_164_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_164_T_1 & ~_ghv_wens_164_T_2 & ~_ghv_wens_164_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hA5
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_164_T & ~_ghv_wens_164_T_1 & ~_ghv_wens_164_T_2 & ~_ghv_wens_164_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hA5 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_164_T_2 & ~_ghv_wens_164_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hA4 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hA5 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA4 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA5 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_164_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_165_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_165_T_1 & ~_ghv_wens_165_T_2 & ~_ghv_wens_165_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hA6
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_165_T & ~_ghv_wens_165_T_1 & ~_ghv_wens_165_T_2 & ~_ghv_wens_165_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hA6 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_165_T_2 & ~_ghv_wens_165_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hA5 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hA6 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA5 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA6 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_165_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_166_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_166_T_1 & ~_ghv_wens_166_T_2 & ~_ghv_wens_166_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hA7
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_166_T & ~_ghv_wens_166_T_1 & ~_ghv_wens_166_T_2 & ~_ghv_wens_166_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hA7 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_166_T_2 & ~_ghv_wens_166_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hA6 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hA7 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA6 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA7 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_166_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_167_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_167_T_1 & ~_ghv_wens_167_T_2 & ~_ghv_wens_167_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hA8
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_167_T & ~_ghv_wens_167_T_1 & ~_ghv_wens_167_T_2 & ~_ghv_wens_167_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hA8 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_167_T_2 & ~_ghv_wens_167_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hA7 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hA8 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA7 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA8 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_167_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_168_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_168_T_1 & ~_ghv_wens_168_T_2 & ~_ghv_wens_168_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hA9
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_168_T & ~_ghv_wens_168_T_1 & ~_ghv_wens_168_T_2 & ~_ghv_wens_168_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hA9 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_168_T_2 & ~_ghv_wens_168_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hA8 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hA9 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA8 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA9 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_168_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_169_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_169_T_1 & ~_ghv_wens_169_T_2 & ~_ghv_wens_169_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hAA
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_169_T & ~_ghv_wens_169_T_1 & ~_ghv_wens_169_T_2 & ~_ghv_wens_169_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hAA & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_169_T_2 & ~_ghv_wens_169_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hA9 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hAA & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hA9 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAA & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_169_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_170_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_170_T_1 & ~_ghv_wens_170_T_2 & ~_ghv_wens_170_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hAB
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_170_T & ~_ghv_wens_170_T_1 & ~_ghv_wens_170_T_2 & ~_ghv_wens_170_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hAB & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_170_T_2 & ~_ghv_wens_170_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hAA & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hAB & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAA & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAB & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_170_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_171_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_171_T_1 & ~_ghv_wens_171_T_2 & ~_ghv_wens_171_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hAC
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_171_T & ~_ghv_wens_171_T_1 & ~_ghv_wens_171_T_2 & ~_ghv_wens_171_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hAC & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_171_T_2 & ~_ghv_wens_171_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hAB & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hAC & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAB & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAC & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_171_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_172_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_172_T_1 & ~_ghv_wens_172_T_2 & ~_ghv_wens_172_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hAD
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_172_T & ~_ghv_wens_172_T_1 & ~_ghv_wens_172_T_2 & ~_ghv_wens_172_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hAD & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_172_T_2 & ~_ghv_wens_172_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hAC & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hAD & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAC & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAD & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_172_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_173_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_173_T_1 & ~_ghv_wens_173_T_2 & ~_ghv_wens_173_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hAE
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_173_T & ~_ghv_wens_173_T_1 & ~_ghv_wens_173_T_2 & ~_ghv_wens_173_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hAE & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_173_T_2 & ~_ghv_wens_173_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hAD & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hAE & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAD & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAE & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_173_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_174_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_174_T_1 & ~_ghv_wens_174_T_2 & ~_ghv_wens_174_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hAF
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_174_T & ~_ghv_wens_174_T_1 & ~_ghv_wens_174_T_2 & ~_ghv_wens_174_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hAF & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_174_T_2 & ~_ghv_wens_174_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hAE & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hAF & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAE & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAF & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_174_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_175_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_175_T_1 & ~_ghv_wens_175_T_2 & ~_ghv_wens_175_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hB0
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_175_T & ~_ghv_wens_175_T_1 & ~_ghv_wens_175_T_2 & ~_ghv_wens_175_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hB0 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_175_T_2 & ~_ghv_wens_175_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hAF & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hB0 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hAF & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB0 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_175_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_176_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_176_T_1 & ~_ghv_wens_176_T_2 & ~_ghv_wens_176_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hB1
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_176_T & ~_ghv_wens_176_T_1 & ~_ghv_wens_176_T_2 & ~_ghv_wens_176_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hB1 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_176_T_2 & ~_ghv_wens_176_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hB0 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hB1 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB0 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB1 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_176_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_177_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_177_T_1 & ~_ghv_wens_177_T_2 & ~_ghv_wens_177_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hB2
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_177_T & ~_ghv_wens_177_T_1 & ~_ghv_wens_177_T_2 & ~_ghv_wens_177_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hB2 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_177_T_2 & ~_ghv_wens_177_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hB1 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hB2 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB1 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB2 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_177_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_178_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_178_T_1 & ~_ghv_wens_178_T_2 & ~_ghv_wens_178_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hB3
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_178_T & ~_ghv_wens_178_T_1 & ~_ghv_wens_178_T_2 & ~_ghv_wens_178_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hB3 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_178_T_2 & ~_ghv_wens_178_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hB2 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hB3 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB2 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB3 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_178_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_179_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_179_T_1 & ~_ghv_wens_179_T_2 & ~_ghv_wens_179_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hB4
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_179_T & ~_ghv_wens_179_T_1 & ~_ghv_wens_179_T_2 & ~_ghv_wens_179_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hB4 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_179_T_2 & ~_ghv_wens_179_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hB3 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hB4 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB3 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB4 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_179_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_180_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_180_T_1 & ~_ghv_wens_180_T_2 & ~_ghv_wens_180_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hB5
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_180_T & ~_ghv_wens_180_T_1 & ~_ghv_wens_180_T_2 & ~_ghv_wens_180_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hB5 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_180_T_2 & ~_ghv_wens_180_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hB4 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hB5 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB4 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB5 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52
|
|
.out_res (_ghv_write_datas_180_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_181_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_181_T_1 & ~_ghv_wens_181_T_2 & ~_ghv_wens_181_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hB6
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_181_T & ~_ghv_wens_181_T_1 & ~_ghv_wens_181_T_2 & ~_ghv_wens_181_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hB6 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_181_T_2 & ~_ghv_wens_181_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hB5 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hB6 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB5 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB6 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:221:7, :350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_181_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_182_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_182_T_1 & ~_ghv_wens_182_T_2 & ~_ghv_wens_182_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hB7
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_182_T & ~_ghv_wens_182_T_1 & ~_ghv_wens_182_T_2 & ~_ghv_wens_182_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hB7 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_182_T_2 & ~_ghv_wens_182_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hB6 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hB7 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB6 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB7 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_182_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_183_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_183_T_1 & ~_ghv_wens_183_T_2 & ~_ghv_wens_183_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hB8
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_183_T & ~_ghv_wens_183_T_1 & ~_ghv_wens_183_T_2 & ~_ghv_wens_183_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hB8 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_183_T_2 & ~_ghv_wens_183_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hB7 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hB8 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB7 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB8 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_183_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_184_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_184_T_1 & ~_ghv_wens_184_T_2 & ~_ghv_wens_184_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hB9
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_184_T & ~_ghv_wens_184_T_1 & ~_ghv_wens_184_T_2 & ~_ghv_wens_184_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hB9 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_184_T_2 & ~_ghv_wens_184_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hB8 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hB9 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB8 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB9 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_184_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_185_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_185_T_1 & ~_ghv_wens_185_T_2 & ~_ghv_wens_185_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hBA
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_185_T & ~_ghv_wens_185_T_1 & ~_ghv_wens_185_T_2 & ~_ghv_wens_185_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hBA & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_185_T_2 & ~_ghv_wens_185_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hB9 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hBA & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hB9 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBA & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_185_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_186_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_186_T_1 & ~_ghv_wens_186_T_2 & ~_ghv_wens_186_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hBB
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_186_T & ~_ghv_wens_186_T_1 & ~_ghv_wens_186_T_2 & ~_ghv_wens_186_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hBB & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_186_T_2 & ~_ghv_wens_186_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hBA & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hBB & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBA & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBB & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_186_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_187_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_187_T_1 & ~_ghv_wens_187_T_2 & ~_ghv_wens_187_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hBC
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_187_T & ~_ghv_wens_187_T_1 & ~_ghv_wens_187_T_2 & ~_ghv_wens_187_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hBC & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_187_T_2 & ~_ghv_wens_187_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hBB & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hBC & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBB & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBC & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_187_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_188_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_188_T_1 & ~_ghv_wens_188_T_2 & ~_ghv_wens_188_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hBD
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_188_T & ~_ghv_wens_188_T_1 & ~_ghv_wens_188_T_2 & ~_ghv_wens_188_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hBD & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_188_T_2 & ~_ghv_wens_188_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hBC & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hBD & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBC & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBD & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_188_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_189_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_189_T_1 & ~_ghv_wens_189_T_2 & ~_ghv_wens_189_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hBE
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_189_T & ~_ghv_wens_189_T_1 & ~_ghv_wens_189_T_2 & ~_ghv_wens_189_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hBE & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_189_T_2 & ~_ghv_wens_189_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hBD & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hBE & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBD & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBE & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_189_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_190_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_190_T_1 & ~_ghv_wens_190_T_2 & ~_ghv_wens_190_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hBF
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_190_T & ~_ghv_wens_190_T_1 & ~_ghv_wens_190_T_2 & ~_ghv_wens_190_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hBF & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_190_T_2 & ~_ghv_wens_190_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hBE & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hBF & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBE & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBF & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_190_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_191_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_191_T_1 & ~_ghv_wens_191_T_2 & ~_ghv_wens_191_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hC0
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_191_T & ~_ghv_wens_191_T_1 & ~_ghv_wens_191_T_2 & ~_ghv_wens_191_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hC0 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_191_T_2 & ~_ghv_wens_191_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hBF & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hC0 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hBF & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC0 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_191_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_192_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_192_T_1 & ~_ghv_wens_192_T_2 & ~_ghv_wens_192_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hC1
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_192_T & ~_ghv_wens_192_T_1 & ~_ghv_wens_192_T_2 & ~_ghv_wens_192_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hC1 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_192_T_2 & ~_ghv_wens_192_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hC0 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hC1 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC0 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC1 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_192_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_193_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_193_T_1 & ~_ghv_wens_193_T_2 & ~_ghv_wens_193_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hC2
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_193_T & ~_ghv_wens_193_T_1 & ~_ghv_wens_193_T_2 & ~_ghv_wens_193_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hC2 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_193_T_2 & ~_ghv_wens_193_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hC1 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hC2 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC1 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC2 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_193_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_194_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_194_T_1 & ~_ghv_wens_194_T_2 & ~_ghv_wens_194_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hC3
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_194_T & ~_ghv_wens_194_T_1 & ~_ghv_wens_194_T_2 & ~_ghv_wens_194_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hC3 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_194_T_2 & ~_ghv_wens_194_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hC2 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hC3 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC2 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC3 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_194_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_195_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_195_T_1 & ~_ghv_wens_195_T_2 & ~_ghv_wens_195_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hC4
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_195_T & ~_ghv_wens_195_T_1 & ~_ghv_wens_195_T_2 & ~_ghv_wens_195_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hC4 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_195_T_2 & ~_ghv_wens_195_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hC3 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hC4 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC3 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC4 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_195_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_196_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_196_T_1 & ~_ghv_wens_196_T_2 & ~_ghv_wens_196_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hC5
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_196_T & ~_ghv_wens_196_T_1 & ~_ghv_wens_196_T_2 & ~_ghv_wens_196_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hC5 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_196_T_2 & ~_ghv_wens_196_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hC4 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hC5 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC4 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC5 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_196_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_197_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_197_T_1 & ~_ghv_wens_197_T_2 & ~_ghv_wens_197_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hC6
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_197_T & ~_ghv_wens_197_T_1 & ~_ghv_wens_197_T_2 & ~_ghv_wens_197_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hC6 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_197_T_2 & ~_ghv_wens_197_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hC5 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hC6 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC5 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC6 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_197_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_198_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_198_T_1 & ~_ghv_wens_198_T_2 & ~_ghv_wens_198_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hC7
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_198_T & ~_ghv_wens_198_T_1 & ~_ghv_wens_198_T_2 & ~_ghv_wens_198_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hC7 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_198_T_2 & ~_ghv_wens_198_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hC6 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hC7 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC6 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC7 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_198_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_199_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_199_T_1 & ~_ghv_wens_199_T_2 & ~_ghv_wens_199_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hC8
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_199_T & ~_ghv_wens_199_T_1 & ~_ghv_wens_199_T_2 & ~_ghv_wens_199_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hC8 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_199_T_2 & ~_ghv_wens_199_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hC7 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hC8 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC7 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC8 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_199_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_200_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_200_T_1 & ~_ghv_wens_200_T_2 & ~_ghv_wens_200_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hC9
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_200_T & ~_ghv_wens_200_T_1 & ~_ghv_wens_200_T_2 & ~_ghv_wens_200_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hC9 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_200_T_2 & ~_ghv_wens_200_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hC8 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hC9 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC8 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC9 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_200_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_201_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_201_T_1 & ~_ghv_wens_201_T_2 & ~_ghv_wens_201_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hCA
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_201_T & ~_ghv_wens_201_T_1 & ~_ghv_wens_201_T_2 & ~_ghv_wens_201_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hCA & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_201_T_2 & ~_ghv_wens_201_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hC9 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hCA & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hC9 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCA & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_201_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_202_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_202_T_1 & ~_ghv_wens_202_T_2 & ~_ghv_wens_202_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hCB
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_202_T & ~_ghv_wens_202_T_1 & ~_ghv_wens_202_T_2 & ~_ghv_wens_202_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hCB & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_202_T_2 & ~_ghv_wens_202_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hCA & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hCB & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCA & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCB & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_202_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_203_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_203_T_1 & ~_ghv_wens_203_T_2 & ~_ghv_wens_203_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hCC
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_203_T & ~_ghv_wens_203_T_1 & ~_ghv_wens_203_T_2 & ~_ghv_wens_203_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hCC & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_203_T_2 & ~_ghv_wens_203_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hCB & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hCC & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCB & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCC & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_203_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_204_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_204_T_1 & ~_ghv_wens_204_T_2 & ~_ghv_wens_204_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hCD
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_204_T & ~_ghv_wens_204_T_1 & ~_ghv_wens_204_T_2 & ~_ghv_wens_204_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hCD & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_204_T_2 & ~_ghv_wens_204_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hCC & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hCD & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCC & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCD & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_204_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_205_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_205_T_1 & ~_ghv_wens_205_T_2 & ~_ghv_wens_205_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hCE
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_205_T & ~_ghv_wens_205_T_1 & ~_ghv_wens_205_T_2 & ~_ghv_wens_205_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hCE & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_205_T_2 & ~_ghv_wens_205_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hCD & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hCE & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCD & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCE & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_205_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_206_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_206_T_1 & ~_ghv_wens_206_T_2 & ~_ghv_wens_206_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hCF
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_206_T & ~_ghv_wens_206_T_1 & ~_ghv_wens_206_T_2 & ~_ghv_wens_206_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hCF & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_206_T_2 & ~_ghv_wens_206_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hCE & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hCF & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCE & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCF & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_206_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_207_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_207_T_1 & ~_ghv_wens_207_T_2 & ~_ghv_wens_207_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hD0
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_207_T & ~_ghv_wens_207_T_1 & ~_ghv_wens_207_T_2 & ~_ghv_wens_207_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hD0 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_207_T_2 & ~_ghv_wens_207_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hCF & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hD0 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hCF & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD0 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_207_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_208_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_208_T_1 & ~_ghv_wens_208_T_2 & ~_ghv_wens_208_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hD1
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_208_T & ~_ghv_wens_208_T_1 & ~_ghv_wens_208_T_2 & ~_ghv_wens_208_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hD1 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_208_T_2 & ~_ghv_wens_208_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hD0 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hD1 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD0 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD1 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_208_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_209_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_209_T_1 & ~_ghv_wens_209_T_2 & ~_ghv_wens_209_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hD2
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_209_T & ~_ghv_wens_209_T_1 & ~_ghv_wens_209_T_2 & ~_ghv_wens_209_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hD2 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_209_T_2 & ~_ghv_wens_209_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hD1 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hD2 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD1 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD2 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_209_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_210_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_210_T_1 & ~_ghv_wens_210_T_2 & ~_ghv_wens_210_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hD3
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_210_T & ~_ghv_wens_210_T_1 & ~_ghv_wens_210_T_2 & ~_ghv_wens_210_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hD3 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_210_T_2 & ~_ghv_wens_210_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hD2 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hD3 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD2 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD3 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_210_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_211_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_211_T_1 & ~_ghv_wens_211_T_2 & ~_ghv_wens_211_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hD4
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_211_T & ~_ghv_wens_211_T_1 & ~_ghv_wens_211_T_2 & ~_ghv_wens_211_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hD4 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_211_T_2 & ~_ghv_wens_211_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hD3 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hD4 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD3 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD4 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_211_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_212_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_212_T_1 & ~_ghv_wens_212_T_2 & ~_ghv_wens_212_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hD5
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_212_T & ~_ghv_wens_212_T_1 & ~_ghv_wens_212_T_2 & ~_ghv_wens_212_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hD5 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_212_T_2 & ~_ghv_wens_212_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hD4 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hD5 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD4 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD5 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_212_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_213_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_213_T_1 & ~_ghv_wens_213_T_2 & ~_ghv_wens_213_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hD6
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_213_T & ~_ghv_wens_213_T_1 & ~_ghv_wens_213_T_2 & ~_ghv_wens_213_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hD6 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_213_T_2 & ~_ghv_wens_213_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hD5 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hD6 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD5 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD6 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_213_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_214_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_214_T_1 & ~_ghv_wens_214_T_2 & ~_ghv_wens_214_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hD7
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_214_T & ~_ghv_wens_214_T_1 & ~_ghv_wens_214_T_2 & ~_ghv_wens_214_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hD7 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_214_T_2 & ~_ghv_wens_214_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hD6 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hD7 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD6 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD7 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_214_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_215_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_215_T_1 & ~_ghv_wens_215_T_2 & ~_ghv_wens_215_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hD8
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_215_T & ~_ghv_wens_215_T_1 & ~_ghv_wens_215_T_2 & ~_ghv_wens_215_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hD8 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_215_T_2 & ~_ghv_wens_215_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hD7 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hD8 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD7 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD8 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_215_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_216_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_216_T_1 & ~_ghv_wens_216_T_2 & ~_ghv_wens_216_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hD9
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_216_T & ~_ghv_wens_216_T_1 & ~_ghv_wens_216_T_2 & ~_ghv_wens_216_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hD9 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_216_T_2 & ~_ghv_wens_216_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hD8 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hD9 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD8 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD9 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_216_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_217_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_217_T_1 & ~_ghv_wens_217_T_2 & ~_ghv_wens_217_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hDA
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_217_T & ~_ghv_wens_217_T_1 & ~_ghv_wens_217_T_2 & ~_ghv_wens_217_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hDA & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_217_T_2 & ~_ghv_wens_217_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hD9 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hDA & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hD9 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDA & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_217_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_218_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_218_T_1 & ~_ghv_wens_218_T_2 & ~_ghv_wens_218_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hDB
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_218_T & ~_ghv_wens_218_T_1 & ~_ghv_wens_218_T_2 & ~_ghv_wens_218_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hDB & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_218_T_2 & ~_ghv_wens_218_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hDA & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hDB & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDA & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDB & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_218_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_219_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_219_T_1 & ~_ghv_wens_219_T_2 & ~_ghv_wens_219_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hDC
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_219_T & ~_ghv_wens_219_T_1 & ~_ghv_wens_219_T_2 & ~_ghv_wens_219_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hDC & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_219_T_2 & ~_ghv_wens_219_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hDB & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hDC & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDB & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDC & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_219_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_220_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_220_T_1 & ~_ghv_wens_220_T_2 & ~_ghv_wens_220_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hDD
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_220_T & ~_ghv_wens_220_T_1 & ~_ghv_wens_220_T_2 & ~_ghv_wens_220_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hDD & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_220_T_2 & ~_ghv_wens_220_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hDC & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hDD & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDC & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDD & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_220_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_221_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_221_T_1 & ~_ghv_wens_221_T_2 & ~_ghv_wens_221_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hDE
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_221_T & ~_ghv_wens_221_T_1 & ~_ghv_wens_221_T_2 & ~_ghv_wens_221_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hDE & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_221_T_2 & ~_ghv_wens_221_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hDD & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hDE & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDD & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDE & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_221_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_222_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_222_T_1 & ~_ghv_wens_222_T_2 & ~_ghv_wens_222_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hDF
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_222_T & ~_ghv_wens_222_T_1 & ~_ghv_wens_222_T_2 & ~_ghv_wens_222_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hDF & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_222_T_2 & ~_ghv_wens_222_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hDE & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hDF & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDE & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDF & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_222_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_223_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_223_T_1 & ~_ghv_wens_223_T_2 & ~_ghv_wens_223_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hE0
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_223_T & ~_ghv_wens_223_T_1 & ~_ghv_wens_223_T_2 & ~_ghv_wens_223_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hE0 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_223_T_2 & ~_ghv_wens_223_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hDF & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hE0 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hDF & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE0 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_223_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_224_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_224_T_1 & ~_ghv_wens_224_T_2 & ~_ghv_wens_224_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hE1
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_224_T & ~_ghv_wens_224_T_1 & ~_ghv_wens_224_T_2 & ~_ghv_wens_224_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hE1 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_224_T_2 & ~_ghv_wens_224_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hE0 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hE1 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE0 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE1 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_224_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_225_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_225_T_1 & ~_ghv_wens_225_T_2 & ~_ghv_wens_225_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hE2
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_225_T & ~_ghv_wens_225_T_1 & ~_ghv_wens_225_T_2 & ~_ghv_wens_225_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hE2 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_225_T_2 & ~_ghv_wens_225_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hE1 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hE2 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE1 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE2 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_225_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_226_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_226_T_1 & ~_ghv_wens_226_T_2 & ~_ghv_wens_226_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hE3
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_226_T & ~_ghv_wens_226_T_1 & ~_ghv_wens_226_T_2 & ~_ghv_wens_226_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hE3 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_226_T_2 & ~_ghv_wens_226_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hE2 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hE3 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE2 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE3 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_226_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_227_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_227_T_1 & ~_ghv_wens_227_T_2 & ~_ghv_wens_227_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hE4
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_227_T & ~_ghv_wens_227_T_1 & ~_ghv_wens_227_T_2 & ~_ghv_wens_227_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hE4 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_227_T_2 & ~_ghv_wens_227_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hE3 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hE4 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE3 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE4 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_227_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_228_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_228_T_1 & ~_ghv_wens_228_T_2 & ~_ghv_wens_228_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hE5
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_228_T & ~_ghv_wens_228_T_1 & ~_ghv_wens_228_T_2 & ~_ghv_wens_228_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hE5 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_228_T_2 & ~_ghv_wens_228_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hE4 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hE5 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE4 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE5 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_228_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_229_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_229_T_1 & ~_ghv_wens_229_T_2 & ~_ghv_wens_229_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hE6
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_229_T & ~_ghv_wens_229_T_1 & ~_ghv_wens_229_T_2 & ~_ghv_wens_229_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hE6 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_229_T_2 & ~_ghv_wens_229_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hE5 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hE6 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE5 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE6 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_229_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_230_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_230_T_1 & ~_ghv_wens_230_T_2 & ~_ghv_wens_230_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hE7
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_230_T & ~_ghv_wens_230_T_1 & ~_ghv_wens_230_T_2 & ~_ghv_wens_230_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hE7 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_230_T_2 & ~_ghv_wens_230_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hE6 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hE7 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE6 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE7 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_230_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_231_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_231_T_1 & ~_ghv_wens_231_T_2 & ~_ghv_wens_231_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hE8
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_231_T & ~_ghv_wens_231_T_1 & ~_ghv_wens_231_T_2 & ~_ghv_wens_231_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hE8 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_231_T_2 & ~_ghv_wens_231_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hE7 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hE8 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE7 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE8 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_231_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_232_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_232_T_1 & ~_ghv_wens_232_T_2 & ~_ghv_wens_232_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hE9
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_232_T & ~_ghv_wens_232_T_1 & ~_ghv_wens_232_T_2 & ~_ghv_wens_232_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hE9 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_232_T_2 & ~_ghv_wens_232_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hE8 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hE9 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE8 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE9 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_232_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_233_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_233_T_1 & ~_ghv_wens_233_T_2 & ~_ghv_wens_233_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hEA
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_233_T & ~_ghv_wens_233_T_1 & ~_ghv_wens_233_T_2 & ~_ghv_wens_233_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hEA & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_233_T_2 & ~_ghv_wens_233_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hE9 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hEA & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hE9 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEA & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_233_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_234_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_234_T_1 & ~_ghv_wens_234_T_2 & ~_ghv_wens_234_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hEB
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_234_T & ~_ghv_wens_234_T_1 & ~_ghv_wens_234_T_2 & ~_ghv_wens_234_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hEB & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_234_T_2 & ~_ghv_wens_234_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hEA & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hEB & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEA & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEB & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_234_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_235_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_235_T_1 & ~_ghv_wens_235_T_2 & ~_ghv_wens_235_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hEC
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_235_T & ~_ghv_wens_235_T_1 & ~_ghv_wens_235_T_2 & ~_ghv_wens_235_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hEC & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_235_T_2 & ~_ghv_wens_235_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hEB & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hEC & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEB & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEC & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_235_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_236_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_236_T_1 & ~_ghv_wens_236_T_2 & ~_ghv_wens_236_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hED
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_236_T & ~_ghv_wens_236_T_1 & ~_ghv_wens_236_T_2 & ~_ghv_wens_236_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hED & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_236_T_2 & ~_ghv_wens_236_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hEC & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hED & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEC & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hED & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_236_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_237_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_237_T_1 & ~_ghv_wens_237_T_2 & ~_ghv_wens_237_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hEE
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_237_T & ~_ghv_wens_237_T_1 & ~_ghv_wens_237_T_2 & ~_ghv_wens_237_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hEE & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_237_T_2 & ~_ghv_wens_237_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hED & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hEE & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hED & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEE & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_237_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_238_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_238_T_1 & ~_ghv_wens_238_T_2 & ~_ghv_wens_238_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hEF
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_238_T & ~_ghv_wens_238_T_1 & ~_ghv_wens_238_T_2 & ~_ghv_wens_238_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hEF & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_238_T_2 & ~_ghv_wens_238_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hEE & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hEF & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEE & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEF & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_238_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_239_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_239_T_1 & ~_ghv_wens_239_T_2 & ~_ghv_wens_239_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hF0
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_239_T & ~_ghv_wens_239_T_1 & ~_ghv_wens_239_T_2 & ~_ghv_wens_239_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hF0 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_239_T_2 & ~_ghv_wens_239_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hEF & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hF0 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hEF & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF0 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_239_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_240_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_240_T_1 & ~_ghv_wens_240_T_2 & ~_ghv_wens_240_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hF1
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_240_T & ~_ghv_wens_240_T_1 & ~_ghv_wens_240_T_2 & ~_ghv_wens_240_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hF1 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_240_T_2 & ~_ghv_wens_240_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hF0 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hF1 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF0 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF1 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_240_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_241_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_241_T_1 & ~_ghv_wens_241_T_2 & ~_ghv_wens_241_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hF2
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_241_T & ~_ghv_wens_241_T_1 & ~_ghv_wens_241_T_2 & ~_ghv_wens_241_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hF2 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_241_T_2 & ~_ghv_wens_241_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hF1 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hF2 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF1 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF2 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_241_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_242_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_242_T_1 & ~_ghv_wens_242_T_2 & ~_ghv_wens_242_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hF3
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_242_T & ~_ghv_wens_242_T_1 & ~_ghv_wens_242_T_2 & ~_ghv_wens_242_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hF3 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_242_T_2 & ~_ghv_wens_242_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hF2 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hF3 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF2 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF3 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_242_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_243_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_243_T_1 & ~_ghv_wens_243_T_2 & ~_ghv_wens_243_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hF4
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_243_T & ~_ghv_wens_243_T_1 & ~_ghv_wens_243_T_2 & ~_ghv_wens_243_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hF4 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_243_T_2 & ~_ghv_wens_243_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hF3 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hF4 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF3 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF4 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_243_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_244_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_244_T_1 & ~_ghv_wens_244_T_2 & ~_ghv_wens_244_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hF5
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_244_T & ~_ghv_wens_244_T_1 & ~_ghv_wens_244_T_2 & ~_ghv_wens_244_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hF5 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_244_T_2 & ~_ghv_wens_244_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hF4 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hF5 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF4 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF5 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_244_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_245_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_245_T_1 & ~_ghv_wens_245_T_2 & ~_ghv_wens_245_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hF6
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_245_T & ~_ghv_wens_245_T_1 & ~_ghv_wens_245_T_2 & ~_ghv_wens_245_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hF6 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_245_T_2 & ~_ghv_wens_245_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hF5 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hF6 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF5 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF6 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_245_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_246_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_246_T_1 & ~_ghv_wens_246_T_2 & ~_ghv_wens_246_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hF7
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_246_T & ~_ghv_wens_246_T_1 & ~_ghv_wens_246_T_2 & ~_ghv_wens_246_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hF7 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_246_T_2 & ~_ghv_wens_246_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hF6 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hF7 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF6 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF7 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_246_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_247_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_247_T_1 & ~_ghv_wens_247_T_2 & ~_ghv_wens_247_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hF8
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_247_T & ~_ghv_wens_247_T_1 & ~_ghv_wens_247_T_2 & ~_ghv_wens_247_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hF8 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_247_T_2 & ~_ghv_wens_247_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hF7 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hF8 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF7 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF8 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_247_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_248_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_248_T_1 & ~_ghv_wens_248_T_2 & ~_ghv_wens_248_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hF9
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_248_T & ~_ghv_wens_248_T_1 & ~_ghv_wens_248_T_2 & ~_ghv_wens_248_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hF9 & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_248_T_2 & ~_ghv_wens_248_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hF8 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hF9 & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF8 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF9 & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_248_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_249_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_249_T_1 & ~_ghv_wens_249_T_2 & ~_ghv_wens_249_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hFA
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_249_T & ~_ghv_wens_249_T_1 & ~_ghv_wens_249_T_2 & ~_ghv_wens_249_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hFA & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_249_T_2 & ~_ghv_wens_249_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hF9 & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hFA & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hF9 & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFA & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_249_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_250_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_250_T_1 & ~_ghv_wens_250_T_2 & ~_ghv_wens_250_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hFB
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_250_T & ~_ghv_wens_250_T_1 & ~_ghv_wens_250_T_2 & ~_ghv_wens_250_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hFB & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_250_T_2 & ~_ghv_wens_250_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hFA & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hFB & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFA & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFB & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_250_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_251_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_251_T_1 & ~_ghv_wens_251_T_2 & ~_ghv_wens_251_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hFC
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_251_T & ~_ghv_wens_251_T_1 & ~_ghv_wens_251_T_2 & ~_ghv_wens_251_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hFC & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_251_T_2 & ~_ghv_wens_251_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hFB & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hFC & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFB & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFC & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_251_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_252_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_252_T_1 & ~_ghv_wens_252_T_2 & ~_ghv_wens_252_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hFD
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_252_T & ~_ghv_wens_252_T_1 & ~_ghv_wens_252_T_2 & ~_ghv_wens_252_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hFD & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_252_T_2 & ~_ghv_wens_252_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hFC & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hFD & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFC & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFD & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_252_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_253_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_253_T_1 & ~_ghv_wens_253_T_2 & ~_ghv_wens_253_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| s2_ghist_ptr_dup_0_value == 8'hFE
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_253_T & ~_ghv_wens_253_T_1 & ~_ghv_wens_253_T_2 & ~_ghv_wens_253_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| s1_ghist_ptr_dup_0_value == 8'hFE & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_253_T_2 & ~_ghv_wens_253_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hFD & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| s3_ghist_ptr_dup_0_value == 8'hFE & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFD & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0
|
|
| do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFE & shouldShiftVec_dup_0_1
|
|
& real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_253_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_254_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_254_T_1 & ~_ghv_wens_254_T_2 & ~_ghv_wens_254_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
(s2_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| (&s2_ghist_ptr_dup_0_value)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_254_T & ~_ghv_wens_254_T_1 & ~_ghv_wens_254_T_2 & ~_ghv_wens_254_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
(s1_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| (&s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_254_T_2 & ~_ghv_wens_254_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
(s3_ghist_ptr_dup_0_value == 8'hFE & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| (&s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15, :453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
(do_redirect_dup_3_bits_cfiUpdate_histPtr_value == 8'hFE & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0 | (&do_redirect_dup_3_bits_cfiUpdate_histPtr_value)
|
|
& shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :763:52, src/main/scala/xiangshan/frontend/FrontendBundle.scala:192:15
|
|
.out_res (_ghv_write_datas_254_ppm_out_res)
|
|
);
|
|
PriorityMuxModule_20 ghv_write_datas_255_ppm ( // utility/src/main/scala/utility/PriorityMuxGen.scala:134:25
|
|
.s2_new_bit_0_sel (_ghv_wens_255_T_1 & ~_ghv_wens_255_T_2 & ~_ghv_wens_255_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s2_new_bit_0_src
|
|
((&s2_ghist_ptr_dup_0_value) & _predictors_io_out_s2_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit
|
|
| ~(|s2_ghist_ptr_dup_0_value)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_WIRE_7_1
|
|
& ~(_selVecOH_T_66 & _predictors_io_out_s2_full_pred_0_hit)
|
|
& _s2_redirect_s1_last_pred_vec_dup_lastBrPosOHDiff_T_53
|
|
& _predictors_io_out_s2_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s2_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :324:35, :582:58, :586:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.s1_new_bit_0_sel
|
|
(_ghv_wens_255_T & ~_ghv_wens_255_T_1 & ~_ghv_wens_255_T_2 & ~_ghv_wens_255_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:516:26, :619:26, :704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s1_new_bit_0_src
|
|
((&s1_ghist_ptr_dup_0_value) & _predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~_s1_ghv_wdatas_WIRE_44494_1) & _predictors_io_out_s1_full_pred_0_hit
|
|
| ~(|s1_ghist_ptr_dup_0_value) & _s1_ghv_wdatas_WIRE_44494_1
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& (_predictors_io_out_s1_full_pred_0_slot_valids_0
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_0
|
|
& _predictors_io_out_s1_full_pred_0_hit | _s1_ghv_wdatas_WIRE_44494_1
|
|
& _predictors_io_out_s1_full_pred_0_br_taken_mask_1
|
|
& _predictors_io_out_s1_full_pred_0_hit)
|
|
& ~(_cfiIndex_bits_WIRE_18_0 & _predictors_io_out_s1_full_pred_0_hit)
|
|
& _predictors_io_out_s1_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :323:35, :494:58, :498:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :481:12, :487:9, :488:{34,37}, :493:{74,90}
|
|
.s3_new_bit_0_sel (_ghv_wens_255_T_2 & ~_ghv_wens_255_T_3), // src/main/scala/xiangshan/frontend/BPU.scala:704:26, :855:26, utility/src/main/scala/utility/PriorityMuxGen.scala:119:{41,120}
|
|
.s3_new_bit_0_src
|
|
((&s3_ghist_ptr_dup_0_value) & _predictors_io_out_s3_full_pred_0_slot_valids_0
|
|
& _selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit
|
|
| ~(|s3_ghist_ptr_dup_0_value) & _s3_ghv_wdatas_WIRE_13797_1
|
|
& ~(_selVecOH_T_98 & _predictors_io_out_s3_full_pred_0_hit)
|
|
& _s3_both_first_taken_dup_T_7 & _predictors_io_out_s3_full_pred_0_is_br_sharing
|
|
& _predictors_io_out_s3_full_pred_0_hit), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:225:26, :325:35, :663:58, :667:37, src/main/scala/xiangshan/frontend/FrontendBundle.scala:453:48, :458:69, :473:32, :474:27, :481:12
|
|
.redirect_new_bit_0_src
|
|
((&do_redirect_dup_3_bits_cfiUpdate_histPtr_value) & shouldShiftVec_dup_0_0
|
|
& real_br_taken_mask_dup_0_0 | ~(|do_redirect_dup_3_bits_cfiUpdate_histPtr_value)
|
|
& shouldShiftVec_dup_0_1 & real_br_taken_mask_dup_0_1), // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/BPU.scala:350:40, :737:54, :747:65, :760:50, :763:52
|
|
.out_res (_ghv_write_datas_255_ppm_out_res)
|
|
);
|
|
assign io_bpu_to_ftq_resp_valid =
|
|
s1_valid_dup_3 | s2_valid_dup_3 & s2_redirect_dup_2 | s3_valid_dup_3
|
|
& s3_redirect_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65, :419:{20,42}, :420:20, :605:28, :684:28
|
|
assign io_bpu_to_ftq_resp_bits_s1_pc_3 = _predictors_io_out_s1_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_0 =
|
|
_predictors_io_out_s1_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_br_taken_mask_1 =
|
|
_predictors_io_out_s1_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_0 =
|
|
_predictors_io_out_s1_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_slot_valids_1 =
|
|
_predictors_io_out_s1_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_0 =
|
|
_predictors_io_out_s1_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_targets_1 =
|
|
_predictors_io_out_s1_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_0 =
|
|
_predictors_io_out_s1_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_offsets_1 =
|
|
_predictors_io_out_s1_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_fallThroughAddr =
|
|
_predictors_io_out_s1_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_is_br_sharing =
|
|
_predictors_io_out_s1_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s1_full_pred_3_hit =
|
|
_predictors_io_out_s1_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s2_pc_3 = _predictors_io_out_s2_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s2_valid_3 = s2_valid_dup_3 & ~s2_flush_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65, :358:26, :717:{32,35}
|
|
assign io_bpu_to_ftq_resp_bits_s2_hasRedirect_3 = s2_redirect_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :605:28
|
|
assign io_bpu_to_ftq_resp_bits_s2_ftq_idx_flag = s2_ftq_idx_flag; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :708:29
|
|
assign io_bpu_to_ftq_resp_bits_s2_ftq_idx_value = s2_ftq_idx_value; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :708:29
|
|
assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_0 =
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_br_taken_mask_1 =
|
|
_predictors_io_out_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_0 =
|
|
_predictors_io_out_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_slot_valids_1 =
|
|
_predictors_io_out_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_0 =
|
|
_predictors_io_out_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_targets_1 =
|
|
_predictors_io_out_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_0 =
|
|
_predictors_io_out_s2_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_offsets_1 =
|
|
_predictors_io_out_s2_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_fallThroughAddr =
|
|
_predictors_io_out_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_is_br_sharing =
|
|
_predictors_io_out_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s2_full_pred_3_hit =
|
|
_predictors_io_out_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s3_pc_3 = _predictors_io_out_s3_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s3_valid_3 =
|
|
s3_valid_dup_3 & ~io_ftq_to_bpu_redirect_valid; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :271:65, :722:{32,35}
|
|
assign io_bpu_to_ftq_resp_bits_s3_hasRedirect_3 = s3_redirect_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :684:28
|
|
assign io_bpu_to_ftq_resp_bits_s3_ftq_idx_flag = s3_ftq_idx_flag; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :709:29
|
|
assign io_bpu_to_ftq_resp_bits_s3_ftq_idx_value = s3_ftq_idx_value; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :709:29
|
|
assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_0 =
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_br_taken_mask_1 =
|
|
_predictors_io_out_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_0 =
|
|
_predictors_io_out_s3_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_slot_valids_1 =
|
|
_predictors_io_out_s3_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_0 =
|
|
_predictors_io_out_s3_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_targets_1 =
|
|
_predictors_io_out_s3_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughAddr =
|
|
_predictors_io_out_s3_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_fallThroughErr =
|
|
_predictors_io_out_s3_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_is_br_sharing =
|
|
_predictors_io_out_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_s3_full_pred_3_hit =
|
|
_predictors_io_out_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :225:26
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_17_folded_hist =
|
|
s3_folded_gh_dup_2_hist_17_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_16_folded_hist =
|
|
s3_folded_gh_dup_2_hist_16_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_15_folded_hist =
|
|
s3_folded_gh_dup_2_hist_15_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_14_folded_hist =
|
|
s3_folded_gh_dup_2_hist_14_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_13_folded_hist =
|
|
s3_folded_gh_dup_2_hist_13_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_12_folded_hist =
|
|
s3_folded_gh_dup_2_hist_12_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_11_folded_hist =
|
|
s3_folded_gh_dup_2_hist_11_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_10_folded_hist =
|
|
s3_folded_gh_dup_2_hist_10_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_9_folded_hist =
|
|
s3_folded_gh_dup_2_hist_9_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_8_folded_hist =
|
|
s3_folded_gh_dup_2_hist_8_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_7_folded_hist =
|
|
s3_folded_gh_dup_2_hist_7_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_6_folded_hist =
|
|
s3_folded_gh_dup_2_hist_6_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_5_folded_hist =
|
|
s3_folded_gh_dup_2_hist_5_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_4_folded_hist =
|
|
s3_folded_gh_dup_2_hist_4_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_3_folded_hist =
|
|
s3_folded_gh_dup_2_hist_3_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_2_folded_hist =
|
|
s3_folded_gh_dup_2_hist_2_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_1_folded_hist =
|
|
s3_folded_gh_dup_2_hist_1_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_folded_hist_hist_0_folded_hist =
|
|
s3_folded_gh_dup_2_hist_0_folded_hist; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :288:35
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_0 =
|
|
s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
|
|
assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_1 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_2 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_5_bits_3 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_5_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_0 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_1 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_2 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_4_bits_3 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_4_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_0 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_1 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_2 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_3_bits_3 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_3_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_0 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_1 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_2 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_2_bits_3 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_2_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_0 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_1 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_2 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_1_bits_3 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_1_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_0 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_0; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_1 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_1; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_2 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_afhob_afhob_0_bits_3 =
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s3_ahead_fh_oldest_bits_dup_2_afhob_0_bits_3; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :300:46
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_lastBrNumOH =
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s3_last_br_num_oh_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :294:40
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_flag =
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s3_ghist_ptr_dup_2_flag; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35
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assign io_bpu_to_ftq_resp_bits_last_stage_spec_info_histPtr_value =
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s3_ghist_ptr_dup_2_value; // src/main/scala/xiangshan/frontend/BPU.scala:221:7, :325:35
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endmodule
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