283 lines
22 KiB
Systemverilog
283 lines
22 KiB
Systemverilog
// Generated by CIRCT firtool-1.61.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module WrBypass( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
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input clock,
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input reset,
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input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
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input [8:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
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input [2:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
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output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
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output io_hit_data_0_valid, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
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output [2:0] io_hit_data_0_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
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);
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wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
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wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
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wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
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wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
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wire _idx_tag_cam_io_r_resp_0_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
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wire _idx_tag_cam_io_r_resp_0_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
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wire _idx_tag_cam_io_r_resp_0_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
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wire _idx_tag_cam_io_r_resp_0_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
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reg valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
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reg valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
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reg valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
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reg valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
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reg valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
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reg valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
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reg valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
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reg valids_7_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23
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reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
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reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
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reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
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reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
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reg ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
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reg ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
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reg ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
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reg ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
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wire hits_oh_0 = _idx_tag_cam_io_r_resp_0_0 & ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
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wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
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wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
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wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
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wire hits_oh_4 = _idx_tag_cam_io_r_resp_0_4 & ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
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wire hits_oh_5 = _idx_tag_cam_io_r_resp_0_5 & ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
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wire hits_oh_6 = _idx_tag_cam_io_r_resp_0_6 & ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
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wire hits_oh_7 = _idx_tag_cam_io_r_resp_0_7 & ever_written_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
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wire [2:0] _hit_idx_T_2 =
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{hits_oh_7, hits_oh_6, hits_oh_5} | {hits_oh_3, hits_oh_2, hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:28, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83
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wire [2:0] data_mem_io_hit_data_0_bits_MPORT_addr =
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{|{hits_oh_7, hits_oh_6, hits_oh_5, hits_oh_4},
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|(_hit_idx_T_2[2:1]),
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_hit_idx_T_2[2] | _hit_idx_T_2[0]}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :31:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83
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wire hit =
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hits_oh_0 | hits_oh_1 | hits_oh_2 | hits_oh_3 | hits_oh_4 | hits_oh_5 | hits_oh_6
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| hits_oh_7; // src/main/scala/xiangshan/frontend/WrBypass.scala:61:83, :63:29
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reg [6:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
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wire [2:0] enq_idx =
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{state_reg[6],
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state_reg[6]
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? {state_reg[5], state_reg[5] ? state_reg[4] : state_reg[3]}
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: {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13
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wire [2:0] state_reg_touch_way_sized =
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hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37
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wire _GEN = enq_idx == 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
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wire _GEN_0 = enq_idx == 3'h1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
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wire _GEN_1 = enq_idx == 3'h2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
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wire _GEN_2 = enq_idx == 3'h3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
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wire _GEN_3 = enq_idx == 3'h4; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
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wire _GEN_4 = enq_idx == 3'h5; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
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wire _GEN_5 = enq_idx == 3'h6; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:95:30, :98:31
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always @(posedge clock or posedge reset) begin
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if (reset) begin
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valids_0_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_1_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_2_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_3_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_4_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_5_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_6_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_7_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
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ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
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ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
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ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
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ever_written_4 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
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ever_written_5 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
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ever_written_6 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
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ever_written_7 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
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state_reg <= 7'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
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end
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else begin
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if (io_wen) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
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if (hit) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29
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valids_0_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h0 | valids_0_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30
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valids_1_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h1 | valids_1_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30
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valids_2_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h2 | valids_2_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30
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valids_3_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h3 | valids_3_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30
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valids_4_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h4 | valids_4_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30
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valids_5_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h5 | valids_5_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30
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valids_6_0 <= data_mem_io_hit_data_0_bits_MPORT_addr == 3'h6 | valids_6_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30
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valids_7_0 <= (&data_mem_io_hit_data_0_bits_MPORT_addr) | valids_7_0; // src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :95:30
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end
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else begin // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29
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valids_0_0 <= _GEN | ~_GEN & valids_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30
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valids_1_0 <= _GEN_0 | ~_GEN_0 & valids_1_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30
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valids_2_0 <= _GEN_1 | ~_GEN_1 & valids_2_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30
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valids_3_0 <= _GEN_2 | ~_GEN_2 & valids_3_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30
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valids_4_0 <= _GEN_3 | ~_GEN_3 & valids_4_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30
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valids_5_0 <= _GEN_4 | ~_GEN_4 & valids_5_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30
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valids_6_0 <= _GEN_5 | ~_GEN_5 & valids_6_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30
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valids_7_0 <= (&enq_idx) | ~(&enq_idx) & valids_7_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:56:23, :98:31, :99:28, :101:30
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end
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state_reg <=
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{~(state_reg_touch_way_sized[2]),
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state_reg_touch_way_sized[2]
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? {~(state_reg_touch_way_sized[1]),
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state_reg_touch_way_sized[1]
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? ~(state_reg_touch_way_sized[0])
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: state_reg[4],
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state_reg_touch_way_sized[1]
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? state_reg[3]
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: ~(state_reg_touch_way_sized[0])}
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: state_reg[5:3],
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state_reg_touch_way_sized[2]
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? state_reg[2:0]
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: {~(state_reg_touch_way_sized[1]),
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state_reg_touch_way_sized[1]
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? ~(state_reg_touch_way_sized[0])
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: state_reg[1],
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state_reg_touch_way_sized[1]
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? state_reg[0]
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: ~(state_reg_touch_way_sized[0])}}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :198:38, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37
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end
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ever_written_0 <= io_wen & ~hit & _GEN | ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
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ever_written_1 <= io_wen & ~hit & _GEN_0 | ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
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ever_written_2 <= io_wen & ~hit & _GEN_1 | ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
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ever_written_3 <= io_wen & ~hit & _GEN_2 | ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
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ever_written_4 <= io_wen & ~hit & _GEN_3 | ever_written_4; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
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ever_written_5 <= io_wen & ~hit & _GEN_4 | ever_written_5; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
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ever_written_6 <= io_wen & ~hit & _GEN_5 | ever_written_6; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
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ever_written_7 <= io_wen & ~hit & (&enq_idx) | ever_written_7; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
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end
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end // always @(posedge, posedge)
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`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
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`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
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`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
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`endif // FIRRTL_BEFORE_INITIAL
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logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
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initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
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`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
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`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
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`endif // INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
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_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
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valids_0_0 = _RANDOM[/*Zero width*/ 1'b0][0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_1_0 = _RANDOM[/*Zero width*/ 1'b0][1]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_2_0 = _RANDOM[/*Zero width*/ 1'b0][2]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_3_0 = _RANDOM[/*Zero width*/ 1'b0][3]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_4_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_5_0 = _RANDOM[/*Zero width*/ 1'b0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_6_0 = _RANDOM[/*Zero width*/ 1'b0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_7_0 = _RANDOM[/*Zero width*/ 1'b0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][8]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
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ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][9]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
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ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][10]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
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ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][11]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
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ever_written_4 = _RANDOM[/*Zero width*/ 1'b0][12]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
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ever_written_5 = _RANDOM[/*Zero width*/ 1'b0][13]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
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ever_written_6 = _RANDOM[/*Zero width*/ 1'b0][14]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
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ever_written_7 = _RANDOM[/*Zero width*/ 1'b0][15]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :57:29
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state_reg = _RANDOM[/*Zero width*/ 1'b0][22:16]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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`endif // RANDOMIZE_REG_INIT
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if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
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valids_0_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_1_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_2_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_3_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_4_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_5_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_6_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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valids_7_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23
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ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
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ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
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ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
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ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
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ever_written_4 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
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ever_written_5 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
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ever_written_6 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
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ever_written_7 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
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state_reg = 7'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
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end
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
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`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
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`endif // FIRRTL_AFTER_INITIAL
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`endif // ENABLE_INITIAL_REG_
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CAMTemplate idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
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.clock (clock),
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.io_r_req_0_idx (io_write_idx),
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.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
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.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
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.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
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.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
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.io_r_resp_0_4 (_idx_tag_cam_io_r_resp_0_4),
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.io_r_resp_0_5 (_idx_tag_cam_io_r_resp_0_5),
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.io_r_resp_0_6 (_idx_tag_cam_io_r_resp_0_6),
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.io_r_resp_0_7 (_idx_tag_cam_io_r_resp_0_7),
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.io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26}
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.io_w_bits_data_idx (io_write_idx),
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.io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12
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);
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data_mem_0_8x3 data_mem_0_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
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.R0_addr (data_mem_io_hit_data_0_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10
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.R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
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.R0_clk (clock),
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.R0_data (io_hit_data_0_bits),
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.W0_addr (hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29
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.W0_en (io_wen),
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.W0_clk (clock),
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.W0_data (io_write_data_0)
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);
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assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29
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assign io_hit_data_0_valid =
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hits_oh_0 & valids_0_0 | hits_oh_1 & valids_1_0 | hits_oh_2 & valids_2_0 | hits_oh_3
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& valids_3_0 | hits_oh_4 & valids_4_0 | hits_oh_5 & valids_5_0 | hits_oh_6
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& valids_6_0 | hits_oh_7 & valids_7_0; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :56:23, :61:83
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endmodule
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