414 lines
29 KiB
Systemverilog
414 lines
29 KiB
Systemverilog
// Generated by CIRCT firtool-1.61.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module FTBEntryGen( // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7
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input [38:0] io_start_addr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_old_entry_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input [3:0] io_old_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input [11:0] io_old_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input [1:0] io_old_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_old_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_old_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input [3:0] io_old_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input [19:0] io_old_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input [1:0] io_old_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_old_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_old_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input [3:0] io_old_entry_pftAddr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_old_entry_carry, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_old_entry_isCall, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_old_entry_isRet, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_old_entry_isJalr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_old_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_old_entry_always_taken_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_old_entry_always_taken_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_brMask_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_brMask_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_brMask_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_brMask_3, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_brMask_4, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_brMask_5, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_brMask_6, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_brMask_7, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_brMask_8, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_brMask_9, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_brMask_10, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_brMask_11, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_brMask_12, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_brMask_13, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_brMask_14, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_brMask_15, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_jmpInfo_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_jmpInfo_bits_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_jmpInfo_bits_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_jmpInfo_bits_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input [3:0] io_pd_jmpOffset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input [38:0] io_pd_jalTarget, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_rvcMask_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_rvcMask_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_rvcMask_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_rvcMask_3, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_rvcMask_4, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_rvcMask_5, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_rvcMask_6, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_rvcMask_7, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_rvcMask_8, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_rvcMask_9, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_rvcMask_10, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_rvcMask_11, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_rvcMask_12, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_rvcMask_13, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_rvcMask_14, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_pd_rvcMask_15, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_cfiIndex_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input [3:0] io_cfiIndex_bits, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input [38:0] io_target, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_hit, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_mispredict_vec_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_mispredict_vec_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_mispredict_vec_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_mispredict_vec_3, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_mispredict_vec_4, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_mispredict_vec_5, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_mispredict_vec_6, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_mispredict_vec_7, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_mispredict_vec_8, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_mispredict_vec_9, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_mispredict_vec_10, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_mispredict_vec_11, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_mispredict_vec_12, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_mispredict_vec_13, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_mispredict_vec_14, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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input io_mispredict_vec_15, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_new_entry_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output [3:0] io_new_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output [11:0] io_new_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output [1:0] io_new_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_new_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_new_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output [3:0] io_new_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output [19:0] io_new_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output [1:0] io_new_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_new_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_new_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output [3:0] io_new_entry_pftAddr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_new_entry_carry, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_new_entry_isCall, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_new_entry_isRet, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_new_entry_isJalr, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_new_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_new_entry_always_taken_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_new_entry_always_taken_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_taken_mask_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_taken_mask_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_jmp_taken, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_mispred_mask_0, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_mispred_mask_1, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_mispred_mask_2, // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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output io_is_old_entry // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14
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);
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wire [15:0] _GEN =
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{{io_pd_brMask_15},
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{io_pd_brMask_14},
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{io_pd_brMask_13},
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{io_pd_brMask_12},
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{io_pd_brMask_11},
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{io_pd_brMask_10},
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{io_pd_brMask_9},
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{io_pd_brMask_8},
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{io_pd_brMask_7},
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{io_pd_brMask_6},
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{io_pd_brMask_5},
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{io_pd_brMask_4},
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{io_pd_brMask_3},
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{io_pd_brMask_2},
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{io_pd_brMask_1},
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{io_pd_brMask_0}}; // src/main/scala/xiangshan/frontend/NewFtq.scala:253:47
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wire init_entry_always_taken_0 = _GEN[io_cfiIndex_bits] & io_cfiIndex_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:253:47
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wire init_entry_isJalr =
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io_pd_jmpInfo_valid & io_pd_jmpInfo_bits_0 & io_cfiIndex_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:256:62
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wire last_jmp_rvi = io_pd_jmpInfo_valid & (&io_pd_jmpOffset) & ~io_pd_rvcMask_15; // src/main/scala/xiangshan/frontend/NewFtq.scala:259:{52,75,78}
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wire cfi_is_jalr = io_cfiIndex_bits == io_pd_jmpOffset & init_entry_isJalr; // src/main/scala/xiangshan/frontend/NewFtq.scala:256:62, :262:37, :263:55
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wire [37:0] _GEN_0 = cfi_is_jalr ? io_target[38:1] : io_pd_jalTarget[38:1]; // src/main/scala/xiangshan/frontend/NewFtq.scala:222:14, :263:55, :284:64
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wire [4:0] _GEN_1 = {1'h0, io_start_addr[4:1]}; // src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :266:30, :287:40
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wire [15:0] _GEN_2 =
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{{io_pd_rvcMask_15},
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{io_pd_rvcMask_14},
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{io_pd_rvcMask_13},
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{io_pd_rvcMask_12},
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{io_pd_rvcMask_11},
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{io_pd_rvcMask_10},
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{io_pd_rvcMask_9},
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{io_pd_rvcMask_8},
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{io_pd_rvcMask_7},
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{io_pd_rvcMask_6},
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{io_pd_rvcMask_5},
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{io_pd_rvcMask_4},
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{io_pd_rvcMask_3},
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{io_pd_rvcMask_2},
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{io_pd_rvcMask_1},
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{io_pd_rvcMask_0}}; // src/main/scala/xiangshan/frontend/NewFtq.scala:287:62
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wire [4:0] jmpPft =
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5'(_GEN_1
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+ 5'({1'h0, io_pd_jmpOffset} + {3'h0, _GEN_2[io_pd_jmpOffset] ? 2'h1 : 2'h2})); // src/main/scala/xiangshan/frontend/FTB.scala:60:10, :61:12, src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :287:{40,56,62}
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wire is_new_br =
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init_entry_always_taken_0
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& {io_old_entry_tailSlot_valid & io_old_entry_tailSlot_offset == io_cfiIndex_bits
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& io_old_entry_tailSlot_sharing,
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io_old_entry_brSlots_0_valid
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& io_old_entry_brSlots_0_offset == io_cfiIndex_bits} == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:194:{32,44}, :195:{42,53}, src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :253:47, :299:{37,44}, :300:29
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wire new_br_insert_onehot_0 =
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~io_old_entry_brSlots_0_valid | io_cfiIndex_bits < io_old_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:307:{9,33,50}
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wire _new_br_insert_onehot_T_3 =
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io_cfiIndex_bits > io_old_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:309:53
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wire new_br_insert_onehot_1 =
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io_old_entry_brSlots_0_valid & _new_br_insert_onehot_T_3
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& (~io_old_entry_tailSlot_valid | io_cfiIndex_bits < io_old_entry_tailSlot_offset); // src/main/scala/xiangshan/frontend/NewFtq.scala:309:{53,83}, :310:{10,36,53}
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wire _GEN_3 = io_cfiIndex_bits > io_old_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:322:31
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wire _GEN_4 = _GEN_3 | ~io_old_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:314:36, :322:{31,61}, :329:44
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wire pft_need_to_change =
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is_new_br & io_old_entry_brSlots_0_valid & io_old_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :342:38
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wire [3:0] new_pft_offset =
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{new_br_insert_onehot_1, new_br_insert_onehot_0} == 2'h0
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? io_cfiIndex_bits
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: io_old_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :307:33, :309:83, :346:{10,33,40}
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wire [4:0] _old_entry_modified_carry_T_1 = 5'(_GEN_1 + {1'h0, new_pft_offset}); // src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :287:40, :346:10, :350:59, :351:58
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wire _old_target_target_T_9 = io_old_entry_tailSlot_tarStat == 2'h1; // src/main/scala/xiangshan/frontend/FTB.scala:60:10, :98:19
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wire _old_target_target_T_10 = io_old_entry_tailSlot_tarStat == 2'h2; // src/main/scala/xiangshan/frontend/FTB.scala:61:12, :99:19
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wire _old_target_target_T_11 = io_old_entry_tailSlot_tarStat == 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:100:19, src/main/scala/xiangshan/frontend/NewFtq.scala:250:41
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|
wire jalr_target_modified =
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cfi_is_jalr
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|
& {io_old_entry_tailSlot_sharing
|
|
? {(_old_target_target_T_9 ? 26'(io_start_addr[38:13] + 26'h1) : 26'h0)
|
|
| (_old_target_target_T_10 ? 26'(io_start_addr[38:13] - 26'h1) : 26'h0)
|
|
| (_old_target_target_T_11 ? io_start_addr[38:13] : 26'h0),
|
|
io_old_entry_tailSlot_lower[11:0]}
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|
: {(_old_target_target_T_9 ? 18'(io_start_addr[38:21] + 18'h1) : 18'h0)
|
|
| (_old_target_target_T_10 ? 18'(io_start_addr[38:21] - 18'h1) : 18'h0)
|
|
| (_old_target_target_T_11 ? io_start_addr[38:21] : 18'h0),
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io_old_entry_tailSlot_lower},
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|
1'h0} != io_target & ~io_old_entry_tailSlot_sharing; // src/main/scala/chisel3/util/Mux.scala:30:73, src/main/scala/xiangshan/frontend/FTB.scala:76:32, :92:30, :93:31, :96:12, :98:19, :99:19, :100:19, :102:16, :109:10, src/main/scala/xiangshan/frontend/NewFtq.scala:250:41, :263:55, :360:25, :361:{57,72}
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wire old_entry_always_taken_always_taken_0 =
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io_old_entry_always_taken_0 & io_cfiIndex_valid & io_old_entry_brSlots_0_valid
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& io_cfiIndex_bits == io_old_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:371:{65,85}
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wire old_entry_always_taken_always_taken_1 =
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io_old_entry_always_taken_1 & io_cfiIndex_valid & io_old_entry_tailSlot_valid
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& io_old_entry_tailSlot_sharing & io_cfiIndex_bits == io_old_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/NewFtq.scala:371:{65,85}
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wire _GEN_5 = is_new_br & new_br_insert_onehot_0; // src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :307:33, :379:8
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wire _GEN_6 = is_new_br & pft_need_to_change; // src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :342:38, :379:8
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wire _GEN_7 = ~is_new_br | ~pft_need_to_change; // src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :314:36, :342:38, :344:29, :352:45, :379:8
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wire [3:0] _io_new_entry_brSlots_0_offset_output =
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io_hit
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? (_GEN_5 ? io_cfiIndex_bits : io_old_entry_brSlots_0_offset)
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: init_entry_always_taken_0 ? io_cfiIndex_bits : 4'h0; // src/main/scala/xiangshan/frontend/NewFtq.scala:250:{28,41}, :253:47, :273:20, :275:25, :379:8, :383:22
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wire _io_new_entry_brSlots_0_valid_output =
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io_hit ? _GEN_5 | io_old_entry_brSlots_0_valid : init_entry_always_taken_0; // src/main/scala/xiangshan/frontend/NewFtq.scala:253:47, :379:8, :383:22
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wire [3:0] _io_new_entry_tailSlot_offset_output =
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|
io_hit
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|
? (is_new_br
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? (new_br_insert_onehot_1
|
|
? io_cfiIndex_bits
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|
: _GEN_4 ? io_old_entry_tailSlot_offset : io_old_entry_brSlots_0_offset)
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|
: io_old_entry_tailSlot_offset)
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|
: io_pd_jmpInfo_valid ? io_pd_jmpOffset : 4'h0; // src/main/scala/xiangshan/frontend/NewFtq.scala:250:{28,41}, :281:24, :282:32, :300:29, :309:83, :314:36, :317:36, :319:19, :322:61, :329:44, :379:8, :383:22
|
|
wire _io_new_entry_tailSlot_sharing_output =
|
|
io_hit
|
|
& (is_new_br
|
|
? new_br_insert_onehot_1 | ~_GEN_3 & io_old_entry_brSlots_0_valid
|
|
| io_old_entry_tailSlot_sharing
|
|
: ~jalr_target_modified & io_old_entry_tailSlot_sharing); // src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:300:29, :309:83, :314:36, :317:36, :322:{31,61}, :329:44, :358:47, :361:72, :362:31, :379:8, :380:10, :383:22
|
|
wire _io_new_entry_tailSlot_valid_output =
|
|
io_hit
|
|
? (is_new_br
|
|
? new_br_insert_onehot_1
|
|
| (_GEN_4 ? io_old_entry_tailSlot_valid : io_old_entry_brSlots_0_valid)
|
|
: io_old_entry_tailSlot_valid)
|
|
: io_pd_jmpInfo_valid
|
|
& (io_pd_jmpInfo_valid & ~io_pd_jmpInfo_bits_0 & io_cfiIndex_valid
|
|
| init_entry_isJalr); // src/main/scala/xiangshan/frontend/NewFtq.scala:250:28, :255:{42,62}, :256:62, :281:24, :283:{31,49}, :300:29, :309:83, :314:36, :317:36, :318:18, :322:61, :329:44, :379:8, :383:22
|
|
wire _io_mispred_mask_1_WIRE_1 =
|
|
_io_new_entry_tailSlot_valid_output & _io_new_entry_tailSlot_sharing_output; // src/main/scala/xiangshan/frontend/FTB.scala:203:47, src/main/scala/xiangshan/frontend/NewFtq.scala:383:22
|
|
wire [15:0] _GEN_8 =
|
|
{{io_mispredict_vec_15},
|
|
{io_mispredict_vec_14},
|
|
{io_mispredict_vec_13},
|
|
{io_mispredict_vec_12},
|
|
{io_mispredict_vec_11},
|
|
{io_mispredict_vec_10},
|
|
{io_mispredict_vec_9},
|
|
{io_mispredict_vec_8},
|
|
{io_mispredict_vec_7},
|
|
{io_mispredict_vec_6},
|
|
{io_mispredict_vec_5},
|
|
{io_mispredict_vec_4},
|
|
{io_mispredict_vec_3},
|
|
{io_mispredict_vec_2},
|
|
{io_mispredict_vec_1},
|
|
{io_mispredict_vec_0}}; // src/main/scala/xiangshan/frontend/NewFtq.scala:391:52
|
|
assign io_new_entry_valid = ~io_hit | io_old_entry_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:{22,23}
|
|
assign io_new_entry_brSlots_0_offset = _io_new_entry_brSlots_0_offset_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22
|
|
assign io_new_entry_brSlots_0_lower =
|
|
io_hit
|
|
? (_GEN_5 ? io_target[12:1] : io_old_entry_brSlots_0_lower)
|
|
: init_entry_always_taken_0 ? io_target[12:1] : 12'h0; // src/main/scala/xiangshan/frontend/FTB.scala:62:64, :68:16, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :250:{28,41}, :253:47, :273:20, :379:8, :383:22
|
|
assign io_new_entry_brSlots_0_tarStat =
|
|
io_hit
|
|
? (_GEN_5
|
|
? (io_target[38:13] > io_start_addr[38:13]
|
|
? 2'h1
|
|
: {io_target[38:13] < io_start_addr[38:13], 1'h0})
|
|
: io_old_entry_brSlots_0_tarStat)
|
|
: init_entry_always_taken_0
|
|
? (io_target[38:13] > io_start_addr[38:13]
|
|
? 2'h1
|
|
: {io_target[38:13] < io_start_addr[38:13], 1'h0})
|
|
: 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:60:{10,25}, :61:{12,27}, :64:23, :65:31, :69:18, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :250:{28,41}, :253:47, :273:20, :379:8, :383:22
|
|
assign io_new_entry_brSlots_0_sharing =
|
|
io_hit & (~is_new_br | ~new_br_insert_onehot_0) & io_old_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :300:29, :307:33, :314:36, :317:36, :379:8, :383:22
|
|
assign io_new_entry_brSlots_0_valid = _io_new_entry_brSlots_0_valid_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22
|
|
assign io_new_entry_tailSlot_offset = _io_new_entry_tailSlot_offset_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22
|
|
assign io_new_entry_tailSlot_lower =
|
|
io_hit
|
|
? (is_new_br
|
|
? (new_br_insert_onehot_1
|
|
? {8'h0, io_target[12:1]}
|
|
: _GEN_4
|
|
? io_old_entry_tailSlot_lower
|
|
: {8'h0, io_old_entry_brSlots_0_lower})
|
|
: jalr_target_modified ? io_target[20:1] : io_old_entry_tailSlot_lower)
|
|
: io_pd_jmpInfo_valid ? _GEN_0[19:0] : 20'h0; // src/main/scala/xiangshan/frontend/FTB.scala:62:64, :68:16, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :250:{28,41}, :281:24, :284:64, :300:29, :309:83, :314:36, :317:36, :322:61, :329:44, :361:72, :379:8, :380:10, :383:22, utility/src/main/scala/utility/BitUtils.scala:88:41
|
|
assign io_new_entry_tailSlot_tarStat =
|
|
io_hit
|
|
? (is_new_br
|
|
? (new_br_insert_onehot_1
|
|
? (io_target[38:13] > io_start_addr[38:13]
|
|
? 2'h1
|
|
: {io_target[38:13] < io_start_addr[38:13], 1'h0})
|
|
: _GEN_4 ? io_old_entry_tailSlot_tarStat : io_old_entry_brSlots_0_tarStat)
|
|
: jalr_target_modified
|
|
? (io_target[38:21] > io_start_addr[38:21]
|
|
? 2'h1
|
|
: {io_target[38:21] < io_start_addr[38:21], 1'h0})
|
|
: io_old_entry_tailSlot_tarStat)
|
|
: io_pd_jmpInfo_valid
|
|
? (_GEN_0[37:20] > io_start_addr[38:21]
|
|
? 2'h1
|
|
: {_GEN_0[37:20] < io_start_addr[38:21], 1'h0})
|
|
: 2'h0; // src/main/scala/xiangshan/frontend/FTB.scala:60:{10,25}, :61:{12,27}, :64:23, :65:31, :69:18, :76:32, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :250:{28,41}, :281:24, :284:64, :300:29, :309:83, :314:36, :317:36, :322:61, :329:44, :361:72, :379:8, :380:10, :383:22
|
|
assign io_new_entry_tailSlot_sharing = _io_new_entry_tailSlot_sharing_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22
|
|
assign io_new_entry_tailSlot_valid = _io_new_entry_tailSlot_valid_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22
|
|
assign io_new_entry_pftAddr =
|
|
io_hit
|
|
? (_GEN_6 ? 4'(io_start_addr[4:1] + new_pft_offset) : io_old_entry_pftAddr)
|
|
: io_pd_jmpInfo_valid & ~last_jmp_rvi ? jmpPft[3:0] : io_start_addr[4:1]; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :259:75, :266:30, :287:56, :288:{28,43,46}, :346:10, :350:59, :379:8, :383:22
|
|
assign io_new_entry_carry =
|
|
io_hit
|
|
? (_GEN_6 ? _old_entry_modified_carry_T_1[4] : io_old_entry_carry)
|
|
: ~(io_pd_jmpInfo_valid & ~last_jmp_rvi) | jmpPft[4]; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :259:75, :287:56, :288:46, :289:{28,43,67}, :351:{58,81}, :379:8, :383:22
|
|
assign io_new_entry_isCall =
|
|
io_hit
|
|
? _GEN_7 & io_old_entry_isCall
|
|
: io_pd_jmpInfo_valid & io_pd_jmpInfo_bits_1 & io_cfiIndex_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :257:62, :379:8, :383:22
|
|
assign io_new_entry_isRet =
|
|
io_hit
|
|
? _GEN_7 & io_old_entry_isRet
|
|
: io_pd_jmpInfo_valid & io_pd_jmpInfo_bits_2 & io_cfiIndex_valid; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :258:62, :379:8, :383:22
|
|
assign io_new_entry_isJalr = io_hit ? _GEN_7 & io_old_entry_isJalr : init_entry_isJalr; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :256:62, :379:8, :383:22
|
|
assign io_new_entry_last_may_be_rvi_call =
|
|
io_hit
|
|
? _GEN_7 & io_old_entry_last_may_be_rvi_call
|
|
: (&io_pd_jmpOffset) & ~_GEN_2[io_pd_jmpOffset]; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :259:52, :287:62, :294:{74,77}, :379:8, :383:22
|
|
assign io_new_entry_always_taken_0 =
|
|
io_hit
|
|
? (is_new_br
|
|
? new_br_insert_onehot_0 | ~_new_br_insert_onehot_T_3
|
|
& io_old_entry_always_taken_0
|
|
: jalr_target_modified
|
|
? ~jalr_target_modified & io_old_entry_always_taken_0
|
|
: old_entry_always_taken_always_taken_0)
|
|
: init_entry_always_taken_0; // src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :253:47, :300:29, :307:33, :309:53, :314:36, :317:36, :321:42, :322:61, :323:42, :358:47, :361:72, :362:31, :364:48, :371:65, :379:8, :380:10, :383:22
|
|
assign io_new_entry_always_taken_1 =
|
|
io_hit
|
|
& (is_new_br
|
|
? new_br_insert_onehot_1 | ~_GEN_3 & io_old_entry_always_taken_1
|
|
: jalr_target_modified
|
|
? ~jalr_target_modified & io_old_entry_always_taken_1
|
|
: old_entry_always_taken_always_taken_1); // src/main/scala/xiangshan/frontend/FTB.scala:70:18, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :300:29, :309:83, :314:36, :317:36, :321:42, :322:{31,61}, :323:42, :329:44, :358:47, :361:72, :362:31, :364:48, :371:65, :379:8, :380:10, :383:22
|
|
assign io_taken_mask_0 =
|
|
io_cfiIndex_bits == _io_new_entry_brSlots_0_offset_output & io_cfiIndex_valid
|
|
& _io_new_entry_brSlots_0_valid_output; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :387:{39,68}
|
|
assign io_taken_mask_1 =
|
|
io_cfiIndex_bits == _io_new_entry_tailSlot_offset_output & io_cfiIndex_valid
|
|
& _io_mispred_mask_1_WIRE_1; // src/main/scala/xiangshan/frontend/FTB.scala:203:47, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :387:{39,68}
|
|
assign io_jmp_taken =
|
|
_io_new_entry_tailSlot_valid_output & ~_io_new_entry_tailSlot_sharing_output
|
|
& _io_new_entry_tailSlot_offset_output == io_cfiIndex_bits; // src/main/scala/xiangshan/frontend/FTB.scala:217:23, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :389:{41,73}
|
|
assign io_mispred_mask_0 =
|
|
_io_new_entry_brSlots_0_valid_output & _GEN_8[_io_new_entry_brSlots_0_offset_output]; // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :391:52
|
|
assign io_mispred_mask_1 =
|
|
_io_mispred_mask_1_WIRE_1 & _GEN_8[_io_new_entry_tailSlot_offset_output]; // src/main/scala/xiangshan/frontend/FTB.scala:203:47, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :391:52
|
|
assign io_mispred_mask_2 =
|
|
_io_new_entry_tailSlot_valid_output & ~_io_new_entry_tailSlot_sharing_output
|
|
& _GEN_8[io_pd_jmpOffset]; // src/main/scala/xiangshan/frontend/FTB.scala:217:23, src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :383:22, :391:52, :393:49
|
|
assign io_is_old_entry =
|
|
io_hit & ~is_new_br & ~jalr_target_modified
|
|
& ~(io_old_entry_always_taken_0 & ~old_entry_always_taken_always_taken_0
|
|
| io_old_entry_always_taken_1 & ~old_entry_always_taken_always_taken_1); // src/main/scala/xiangshan/frontend/NewFtq.scala:221:7, :300:29, :361:72, :371:65, :372:{56,59}, :374:65, :397:{29,43,65,68}
|
|
endmodule
|
|
|