147 lines
7.9 KiB
Systemverilog
147 lines
7.9 KiB
Systemverilog
// Generated by CIRCT firtool-1.62.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module Folded1WDataModuleTemplate( // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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input clock, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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input reset, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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input io_ren_0, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14]
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input [7:0] io_raddr_0, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14]
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output io_rdata_0, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14]
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input io_wen, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14]
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input [7:0] io_waddr, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14]
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input io_wdata, // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14]
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input io_resetEn // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14]
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);
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wire [15:0] _data_ext_R0_data; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17]
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reg doing_reset; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:226:28]
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reg [3:0] resetRow; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:230:25]
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reg [7:0] raddr_0; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:236:69]
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wire [15:0] _GEN =
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{{_data_ext_R0_data[15]},
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{_data_ext_R0_data[14]},
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{_data_ext_R0_data[13]},
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{_data_ext_R0_data[12]},
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{_data_ext_R0_data[11]},
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{_data_ext_R0_data[10]},
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{_data_ext_R0_data[9]},
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{_data_ext_R0_data[8]},
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{_data_ext_R0_data[7]},
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{_data_ext_R0_data[6]},
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{_data_ext_R0_data[5]},
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{_data_ext_R0_data[4]},
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{_data_ext_R0_data[3]},
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{_data_ext_R0_data[2]},
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{_data_ext_R0_data[1]},
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{_data_ext_R0_data[0]}}; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17, :243:23]
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always @(posedge clock or posedge reset) begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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if (reset) begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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doing_reset <= 1'h1; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28]
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resetRow <= 4'h0; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:230:25]
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end
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else begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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doing_reset <= resetRow != 4'hF & (io_resetEn | doing_reset); // @[utility/src/main/scala/utility/DataModuleTemplate.scala:226:28, :228:{36,50}, :230:25, :232:{18,35,49}]
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if (doing_reset) // @[utility/src/main/scala/utility/DataModuleTemplate.scala:226:28]
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resetRow <= 4'(resetRow + 4'h1); // @[utility/src/main/scala/utility/DataModuleTemplate.scala:230:25, :231:45]
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end
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end // always @(posedge, posedge)
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always @(posedge clock) begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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if (io_ren_0) // @[utility/src/main/scala/utility/DataModuleTemplate.scala:209:14]
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raddr_0 <= io_raddr_0; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:236:69]
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end // always @(posedge)
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`ifdef ENABLE_INITIAL_REG_ // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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`ifdef FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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`FIRRTL_BEFORE_INITIAL // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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`endif // FIRRTL_BEFORE_INITIAL
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logic [31:0] _RANDOM[0:0]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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initial begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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`ifdef INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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`INIT_RANDOM_PROLOG_ // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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`endif // INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE_REG_INIT // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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doing_reset = _RANDOM[/*Zero width*/ 1'b0][0]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28]
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resetRow = _RANDOM[/*Zero width*/ 1'b0][4:1]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28, :230:25]
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raddr_0 = _RANDOM[/*Zero width*/ 1'b0][12:5]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28, :236:69]
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`endif // RANDOMIZE_REG_INIT
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if (reset) begin // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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doing_reset = 1'h1; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28]
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resetRow = 4'h0; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:230:25]
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end
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end // initial
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`ifdef FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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`FIRRTL_AFTER_INITIAL // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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`endif // FIRRTL_AFTER_INITIAL
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`endif // ENABLE_INITIAL_REG_
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data_16x16 data_ext ( // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17]
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.R0_addr (raddr_0[7:4]), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:236:69, :241:25]
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.R0_en (1'h1), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7]
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.R0_clk (clock),
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.R0_data (_data_ext_R0_data),
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.W0_addr (io_waddr[7:4]), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:246:24]
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.W0_en (~doing_reset & io_wen), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17, :226:28, :243:23, :250:21, :252:22]
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.W0_clk (clock),
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.W0_data ({16{io_wdata}}), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17]
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.W1_addr (resetRow), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:230:25]
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.W1_en (doing_reset), // @[utility/src/main/scala/utility/DataModuleTemplate.scala:226:28]
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.W1_clk (clock),
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.W1_data (16'h0) // @[utility/src/main/scala/utility/DataModuleTemplate.scala:224:17]
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);
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assign io_rdata_0 = ~doing_reset & _GEN[raddr_0[3:0]]; // @[utility/src/main/scala/utility/DataModuleTemplate.scala:207:7, :226:28, :236:69, :242:23, :243:23]
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endmodule
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