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add ittage, rename src to rtl_src, update gitignore

This commit is contained in:
Makiras 2024-04-19 06:50:22 +00:00
parent cc837105c9
commit aeea5bb381
86 changed files with 2241 additions and 43 deletions
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4
.gitignore vendored
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@ -1,2 +1,6 @@
out
split_verilogs
.vscode
**/__pycache__/
*.fst
**/UT_*

5
Makefile
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@ -21,7 +21,10 @@ ftb:
ras:
make -f ./mk/RAS.mk ras
ittage:
make -f ./mk/ITTAGE.mk ittage
filter:
cat log|grep Cannot |awk '{print $8}'| sort| uniq|tr -d "'"
all: uftb tage_sc ftb ras
all: uftb tage_sc ftb ras ittage

2
doc/env_cn.md
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@ -88,7 +88,7 @@ make tage_sc TL=python
make ftb TL=python
```
**支持的模块名称有：uftb、tage_sc、ftb、ras。也可以通过如下命令，一次性生成所有DUT模块。**
**支持的模块名称有：uftb、tage_sc、ftb、ras、ittage。也可以通过如下命令，一次性生成所有DUT模块。**
```bash
make all TL=python

4
mk/FTB.mk
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@ -1,5 +1,5 @@
TOP_ENTRY := ./src/FTB/FTB.sv
TOP_FILES := ./src/FTB.txt
TOP_ENTRY := ./rtl_src/FTB/FTB.sv
TOP_FILES := ./rtl_src/FTB.txt
TL ?= cpp
ifneq ($(TARGET),)

47
mk/ITTAGE.mk Normal file
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@ -0,0 +1,47 @@
TOP_ENTRY := ./rtl_src/ITTAGE/ITTage.sv
TOP_FILES := ./rtl_src/ITTAGE.txt
TL ?= cpp
ifneq ($(TARGET),)
TARGET := $(TARGET)
else
TARGET := out/picker_out_ITTAGE
endif
# if EXAMPLE is set, then _EXAMPLE is set to -e
ifneq ($(EXAMPLE), false)
_EXAMPLE := -e
endif
_EXAMPLE ?=
# if VERBOSE is set, then _VERBOSE is set to -v
ifneq ($(VERBOSE), false)
_VERBOSE := -v
endif
_VERBOSE ?=
# if WAVE is set, then _WAVEFORM is set to -w
ifneq ($(WAVE), false)
ifneq ($(WAVE), true)
_WAVEFORM := -w $(WAVE)
else
_WAVEFORM := -w ITTAGE.fst
endif
endif
_WAVEFORM ?=
ittage:
@echo "Building tage module with parameters: "
@echo "TL=${TL}"
@echo "TOP_ENTRY=${TOP_ENTRY}"
@echo "TOP_FILES=${TOP_FILES}"
@echo "TARGET=${TARGET}"
@echo "WAVEFORM=${_WAVEFORM}"
@echo "VERBOSE=${_VERBOSE}"
@echo "EXAMPLE=${_EXAMPLE}"
@mkdir -p out
rm -rf ${TARGET}
picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${TL} \
-t ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE}
cd ${TARGET} && make

4
mk/RAS.mk
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@ -1,5 +1,5 @@
TOP_ENTRY := ./src/RAS/RAS.sv
TOP_FILES := ./src/RAS.txt
TOP_ENTRY := ./rtl_src/RAS/RAS.sv
TOP_FILES := ./rtl_src/RAS.txt
TL ?= cpp
ifneq ($(TARGET),)

4
mk/Tage.mk
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@ -1,5 +1,5 @@
TOP_ENTRY := ./src/TageSC/Tage_SC.sv
TOP_FILES := ./src/Tage_SC.txt
TOP_ENTRY := ./rtl_src/TageSC/Tage_SC.sv
TOP_FILES := ./rtl_src/Tage_SC.txt
TL ?= cpp
ifneq ($(TARGET),)

4
mk/uFTB.mk
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@ -1,5 +1,5 @@
TOP_ENTRY := ./src/uFTB/FauFTB.sv
TOP_FILES := ./src/uFTB.txt
TOP_ENTRY := ./rtl_src/uFTB/FauFTB.sv
TOP_FILES := ./rtl_src/uFTB.txt
TL ?= cpp
ifneq ($(TARGET),)

0
src/FTB.txt → rtl_src/FTB.txt
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0
src/FTB/FTB.sv → rtl_src/FTB/FTB.sv
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0
src/FTB/FTBBank.sv → rtl_src/FTB/FTBBank.sv
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0
src/FTB/FTBEntryGen.sv → rtl_src/FTB/FTBEntryGen.sv
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0
src/FTB/SRAMTemplate_9.sv → rtl_src/FTB/SRAMTemplate_9.sv
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0
src/FTB/array_3.sv → rtl_src/FTB/array_3.sv
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24
rtl_src/ITTAGE.txt Normal file
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@ -0,0 +1,24 @@
./src/ITTAGE/CAMTemplate_41.sv
./src/ITTAGE/CAMTemplate_43.sv
./src/ITTAGE/Folded1WDataModuleTemplate.sv
./src/ITTAGE/Folded1WDataModuleTemplate_2.sv
./src/ITTAGE/FoldedSRAMTemplate_21.sv
./src/ITTAGE/FoldedSRAMTemplate_25.sv
./src/ITTAGE/ITTage.sv
./src/ITTAGE/ITTageTable.sv
./src/ITTAGE/ITTageTable_1.sv
./src/ITTAGE/ITTageTable_2.sv
./src/ITTAGE/ITTageTable_3.sv
./src/ITTAGE/ITTageTable_4.sv
./src/ITTAGE/SRAMTemplate_35.sv
./src/ITTAGE/SRAMTemplate_39.sv
./src/ITTAGE/WrBypass_41.sv
./src/ITTAGE/WrBypass_43.sv
./src/ITTAGE/array_0_0.sv
./src/ITTAGE/array_8.sv
./src/ITTAGE/data_16x16.sv
./src/ITTAGE/data_32x16.sv
./src/ITTAGE/data_mem_0_4x2.sv
#
./src/common/ext_sram.v
./src/common/DelayN_2.sv

110
rtl_src/ITTAGE/CAMTemplate_41.sv Normal file
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@ -0,0 +1,110 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module CAMTemplate_41( // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
input clock,
input [7:0] io_r_req_0_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_0, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_1, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_2, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_3, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
input io_w_valid, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
input [7:0] io_w_bits_data_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
input [1:0] io_w_bits_index // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
);
reg [7:0] array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [7:0] array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
always @(posedge clock) begin
if (io_w_valid & io_w_bits_index == 2'h0) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_0 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 2'h1) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_1 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 2'h2) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_2 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & (&io_w_bits_index)) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_3 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
initial begin // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
array_0 = _RANDOM[/*Zero width*/ 1'b0][7:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_1 = _RANDOM[/*Zero width*/ 1'b0][15:8]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_2 = _RANDOM[/*Zero width*/ 1'b0][23:16]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_3 = _RANDOM[/*Zero width*/ 1'b0][31:24]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
endmodule

112
rtl_src/ITTAGE/CAMTemplate_43.sv Normal file
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@ -0,0 +1,112 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module CAMTemplate_43( // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
input clock,
input [8:0] io_r_req_0_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_0, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_1, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_2, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
output io_r_resp_0_3, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
input io_w_valid, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
input [8:0] io_w_bits_data_idx, // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
input [1:0] io_w_bits_index // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:137:14
);
reg [8:0] array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [8:0] array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [8:0] array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
reg [8:0] array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
always @(posedge clock) begin
if (io_w_valid & io_w_bits_index == 2'h0) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :158:21, :159:28
array_0 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 2'h1) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :158:21, :159:28
array_1 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & io_w_bits_index == 2'h2) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :158:21, :159:28
array_2 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
if (io_w_valid & (&io_w_bits_index)) // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18, :158:21, :159:28
array_3 <= io_w_bits_data_idx; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:152:18
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:1]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
initial begin // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
for (logic [1:0] i = 2'h0; i < 2'h2; i += 2'h1) begin
_RANDOM[i[0]] = `RANDOM; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
end // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
array_0 = _RANDOM[1'h0][8:0]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_1 = _RANDOM[1'h0][17:9]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_2 = _RANDOM[1'h0][26:18]; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
array_3 = {_RANDOM[1'h0][31:27], _RANDOM[1'h1][3:0]}; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
assign io_r_resp_0_0 = io_r_req_0_idx == array_0; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_1 = io_r_req_0_idx == array_1; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_2 = io_r_req_0_idx == array_2; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
assign io_r_resp_0_3 = io_r_req_0_idx == array_3; // src/main/scala/xiangshan/cache/mmu/MMUBundle.scala:136:7, :152:18, :155:39
endmodule

142
rtl_src/ITTAGE/Folded1WDataModuleTemplate.sv Normal file
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@ -0,0 +1,142 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module Folded1WDataModuleTemplate( // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
input clock,
input reset,
input [7:0] io_raddr_0, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14
output io_rdata_0, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14
input io_wen, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14
input [7:0] io_waddr, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14
input io_wdata, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14
input io_resetEn // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14
);
wire [15:0] _data_ext_R0_data; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
reg doing_reset; // utility/src/main/scala/utility/DataModuleTemplate.scala:213:28
reg [3:0] resetRow; // utility/src/main/scala/utility/DataModuleTemplate.scala:217:25
reg [7:0] raddr_0; // utility/src/main/scala/utility/DataModuleTemplate.scala:221:34
wire [15:0] _GEN =
{{_data_ext_R0_data[15]},
{_data_ext_R0_data[14]},
{_data_ext_R0_data[13]},
{_data_ext_R0_data[12]},
{_data_ext_R0_data[11]},
{_data_ext_R0_data[10]},
{_data_ext_R0_data[9]},
{_data_ext_R0_data[8]},
{_data_ext_R0_data[7]},
{_data_ext_R0_data[6]},
{_data_ext_R0_data[5]},
{_data_ext_R0_data[4]},
{_data_ext_R0_data[3]},
{_data_ext_R0_data[2]},
{_data_ext_R0_data[1]},
{_data_ext_R0_data[0]}}; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17, :226:23
always @(posedge clock or posedge reset) begin
if (reset) begin
doing_reset <= 1'h1; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28
resetRow <= 4'h0; // utility/src/main/scala/utility/DataModuleTemplate.scala:217:25
end
else begin
doing_reset <= resetRow != 4'hF & (io_resetEn | doing_reset); // utility/src/main/scala/utility/DataModuleTemplate.scala:213:28, :215:{36,50}, :217:25, :219:{18,35,49}
resetRow <= 4'(resetRow + {3'h0, doing_reset}); // utility/src/main/scala/utility/DataModuleTemplate.scala:213:28, :217:25, :218:24
end
end // always @(posedge, posedge)
always @(posedge clock)
raddr_0 <= io_raddr_0; // utility/src/main/scala/utility/DataModuleTemplate.scala:221:34
`ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
`ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
`FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
initial begin // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
`ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
doing_reset = _RANDOM[/*Zero width*/ 1'b0][0]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28
resetRow = _RANDOM[/*Zero width*/ 1'b0][4:1]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28, :217:25
raddr_0 = _RANDOM[/*Zero width*/ 1'b0][12:5]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28, :221:34
`endif // RANDOMIZE_REG_INIT
if (reset) begin // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
doing_reset = 1'h1; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28
resetRow = 4'h0; // utility/src/main/scala/utility/DataModuleTemplate.scala:217:25
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
`FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
data_16x16 data_ext ( // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
.R0_addr (raddr_0[7:4]), // utility/src/main/scala/utility/DataModuleTemplate.scala:221:34, :224:25
.R0_en (1'h1), // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
.R0_clk (clock),
.R0_data (_data_ext_R0_data),
.W0_addr (io_waddr[7:4]), // utility/src/main/scala/utility/DataModuleTemplate.scala:229:24
.W0_en (~doing_reset & io_wen), // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17, :213:28, :226:23, :233:21, :235:22
.W0_clk (clock),
.W0_data ({16{io_wdata}}), // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
.W1_addr (resetRow), // utility/src/main/scala/utility/DataModuleTemplate.scala:217:25
.W1_en (doing_reset), // utility/src/main/scala/utility/DataModuleTemplate.scala:213:28
.W1_clk (clock),
.W1_data (16'h0) // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
);
assign io_rdata_0 = ~doing_reset & _GEN[raddr_0[3:0]]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28, :221:34, :225:23, :226:23
endmodule

142
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@ -0,0 +1,142 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module Folded1WDataModuleTemplate_2( // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
input clock,
input reset,
input [8:0] io_raddr_0, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14
output io_rdata_0, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14
input io_wen, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14
input [8:0] io_waddr, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14
input io_wdata, // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14
input io_resetEn // utility/src/main/scala/utility/DataModuleTemplate.scala:197:14
);
wire [15:0] _data_ext_R0_data; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
reg doing_reset; // utility/src/main/scala/utility/DataModuleTemplate.scala:213:28
reg [4:0] resetRow; // utility/src/main/scala/utility/DataModuleTemplate.scala:217:25
reg [8:0] raddr_0; // utility/src/main/scala/utility/DataModuleTemplate.scala:221:34
wire [15:0] _GEN =
{{_data_ext_R0_data[15]},
{_data_ext_R0_data[14]},
{_data_ext_R0_data[13]},
{_data_ext_R0_data[12]},
{_data_ext_R0_data[11]},
{_data_ext_R0_data[10]},
{_data_ext_R0_data[9]},
{_data_ext_R0_data[8]},
{_data_ext_R0_data[7]},
{_data_ext_R0_data[6]},
{_data_ext_R0_data[5]},
{_data_ext_R0_data[4]},
{_data_ext_R0_data[3]},
{_data_ext_R0_data[2]},
{_data_ext_R0_data[1]},
{_data_ext_R0_data[0]}}; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17, :226:23
always @(posedge clock or posedge reset) begin
if (reset) begin
doing_reset <= 1'h1; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28
resetRow <= 5'h0; // utility/src/main/scala/utility/DataModuleTemplate.scala:217:25
end
else begin
doing_reset <= resetRow != 5'h1F & (io_resetEn | doing_reset); // utility/src/main/scala/utility/DataModuleTemplate.scala:213:28, :215:{36,50}, :217:25, :219:{18,35,49}
resetRow <= 5'(resetRow + {4'h0, doing_reset}); // utility/src/main/scala/utility/DataModuleTemplate.scala:213:28, :217:25, :218:24
end
end // always @(posedge, posedge)
always @(posedge clock)
raddr_0 <= io_raddr_0; // utility/src/main/scala/utility/DataModuleTemplate.scala:221:34
`ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
`ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
`FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
initial begin // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
`ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
doing_reset = _RANDOM[/*Zero width*/ 1'b0][0]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28
resetRow = _RANDOM[/*Zero width*/ 1'b0][5:1]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28, :217:25
raddr_0 = _RANDOM[/*Zero width*/ 1'b0][14:6]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28, :221:34
`endif // RANDOMIZE_REG_INIT
if (reset) begin // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
doing_reset = 1'h1; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28
resetRow = 5'h0; // utility/src/main/scala/utility/DataModuleTemplate.scala:217:25
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
`FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
data_32x16 data_ext ( // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
.R0_addr (raddr_0[8:4]), // utility/src/main/scala/utility/DataModuleTemplate.scala:221:34, :224:25
.R0_en (1'h1), // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7
.R0_clk (clock),
.R0_data (_data_ext_R0_data),
.W0_addr (io_waddr[8:4]), // utility/src/main/scala/utility/DataModuleTemplate.scala:229:24
.W0_en (~doing_reset & io_wen), // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17, :213:28, :226:23, :233:21, :235:22
.W0_clk (clock),
.W0_data ({16{io_wdata}}), // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
.W1_addr (resetRow), // utility/src/main/scala/utility/DataModuleTemplate.scala:217:25
.W1_en (doing_reset), // utility/src/main/scala/utility/DataModuleTemplate.scala:213:28
.W1_clk (clock),
.W1_data (16'h0) // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
);
assign io_rdata_0 = ~doing_reset & _GEN[raddr_0[3:0]]; // utility/src/main/scala/utility/DataModuleTemplate.scala:195:7, :213:28, :221:34, :225:23, :226:23
endmodule

88
rtl_src/ITTAGE/FoldedSRAMTemplate_21.sv Normal file
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@ -0,0 +1,88 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FoldedSRAMTemplate_21( // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
input clock,
input reset,
input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [6:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
output [8:0] io_r_resp_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
output [1:0] io_r_resp_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
output [38:0] io_r_resp_data_0_target, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [6:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [8:0] io_w_req_bits_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [1:0] io_w_req_bits_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [38:0] io_w_req_bits_data_0_target // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
);
SRAMTemplate_35 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
.clock (clock),
.reset (reset),
.io_r_req_valid (io_r_req_valid),
.io_r_req_bits_setIdx (io_r_req_bits_setIdx),
.io_r_resp_data_0_tag (io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (io_r_resp_data_0_target),
.io_w_req_valid (io_w_req_valid),
.io_w_req_bits_setIdx (io_w_req_bits_setIdx),
.io_w_req_bits_data_0_tag (io_w_req_bits_data_0_tag),
.io_w_req_bits_data_0_ctr (io_w_req_bits_data_0_ctr),
.io_w_req_bits_data_0_target (io_w_req_bits_data_0_target)
);
endmodule

140
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@ -0,0 +1,140 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module FoldedSRAMTemplate_25( // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
input clock,
input reset,
input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [7:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
output [8:0] io_r_resp_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
output [1:0] io_r_resp_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
output [38:0] io_r_resp_data_0_target, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [7:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [8:0] io_w_req_bits_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [1:0] io_w_req_bits_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
input [38:0] io_w_req_bits_data_0_target // utility/src/main/scala/utility/SRAMTemplate.scala:165:14
);
wire [8:0] _array_io_r_resp_data_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire [1:0] _array_io_r_resp_data_0_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire [38:0] _array_io_r_resp_data_0_target; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire [8:0] _array_io_r_resp_data_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire [1:0] _array_io_r_resp_data_1_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
wire [38:0] _array_io_r_resp_data_1_target; // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
reg ridx; // utility/src/main/scala/utility/SRAMTemplate.scala:189:21
reg holdRidx_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44
reg holdRidx_hold_data; // utility/src/main/scala/utility/Hold.scala:24:82
wire holdRidx = holdRidx_REG ? ridx : holdRidx_hold_data; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:189:21, :198:44
always @(posedge clock) begin
ridx <= io_r_req_bits_setIdx[0]; // utility/src/main/scala/utility/SRAMTemplate.scala:189:{21,58}
holdRidx_REG <= io_r_req_valid; // utility/src/main/scala/utility/SRAMTemplate.scala:198:44
if (holdRidx_REG) // utility/src/main/scala/utility/SRAMTemplate.scala:198:44
holdRidx_hold_data <= ridx; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:189:21
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
ridx = _RANDOM[/*Zero width*/ 1'b0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21
holdRidx_REG = _RANDOM[/*Zero width*/ 1'b0][1]; // utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21, :198:44
holdRidx_hold_data = _RANDOM[/*Zero width*/ 1'b0][2]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :189:21
`endif // RANDOMIZE_REG_INIT
end // initial
`ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:162:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
SRAMTemplate_39 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:179:21
.clock (clock),
.reset (reset),
.io_r_req_valid (io_r_req_valid),
.io_r_req_bits_setIdx (io_r_req_bits_setIdx[7:1]), // utility/src/main/scala/utility/SRAMTemplate.scala:188:36
.io_r_resp_data_0_tag (_array_io_r_resp_data_0_tag),
.io_r_resp_data_0_ctr (_array_io_r_resp_data_0_ctr),
.io_r_resp_data_0_target (_array_io_r_resp_data_0_target),
.io_r_resp_data_1_tag (_array_io_r_resp_data_1_tag),
.io_r_resp_data_1_ctr (_array_io_r_resp_data_1_ctr),
.io_r_resp_data_1_target (_array_io_r_resp_data_1_target),
.io_w_req_valid (io_w_req_valid),
.io_w_req_bits_setIdx (io_w_req_bits_setIdx[7:1]), // utility/src/main/scala/utility/SRAMTemplate.scala:205:36
.io_w_req_bits_data_0_tag (io_w_req_bits_data_0_tag),
.io_w_req_bits_data_0_ctr (io_w_req_bits_data_0_ctr),
.io_w_req_bits_data_0_target (io_w_req_bits_data_0_target),
.io_w_req_bits_data_1_tag (io_w_req_bits_data_0_tag),
.io_w_req_bits_data_1_ctr (io_w_req_bits_data_0_ctr),
.io_w_req_bits_data_1_target (io_w_req_bits_data_0_target),
.io_w_req_bits_waymask (2'h1 << io_w_req_bits_setIdx[0]) // src/main/scala/chisel3/util/OneHot.scala:58:35, :65:12, utility/src/main/scala/utility/SRAMTemplate.scala:206:54
);
assign io_r_resp_data_0_tag =
(holdRidx ? 9'h0 : _array_io_r_resp_data_0_tag)
| (holdRidx ? _array_io_r_resp_data_1_tag : 9'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21
assign io_r_resp_data_0_ctr =
(holdRidx ? 2'h0 : _array_io_r_resp_data_0_ctr)
| (holdRidx ? _array_io_r_resp_data_1_ctr : 2'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21
assign io_r_resp_data_0_target =
(holdRidx ? 39'h0 : _array_io_r_resp_data_0_target)
| (holdRidx ? _array_io_r_resp_data_1_target : 39'h0); // src/main/scala/chisel3/util/Mux.scala:30:73, utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:162:7, :179:21
endmodule

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_35( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
input clock,
input reset,
input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [6:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [8:0] io_r_resp_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [38:0] io_r_resp_data_0_target, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [6:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [8:0] io_w_req_bits_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [38:0] io_w_req_bits_data_0_target // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
);
wire [6:0] writeAddr; // utility/src/main/scala/utility/SRAMTemplate.scala:125:19
wire readEnable; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38
wire writeEnable; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52
wire [49:0] _array_0_RW0_rdata; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
reg _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30
reg [6:0] _resetSet; // src/main/scala/chisel3/util/Counter.scala:61:40
assign writeEnable = io_w_req_valid | _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :122:52
assign readEnable = io_r_req_valid & ~writeEnable; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52, :123:{38,41}
assign writeAddr = _resetState ? _resetSet : io_w_req_bits_setIdx; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :125:19
reg rdata_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59
reg [49:0] rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82
wire [49:0] _rdata_WIRE = rdata_REG ? _array_0_RW0_rdata : rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :153:59
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
_resetSet <= 7'h0; // src/main/scala/chisel3/util/Counter.scala:61:40
end
else begin
_resetState <= ~(_resetState & (&_resetSet)) & _resetState; // src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :111:{24,38}
if (_resetState) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30
_resetSet <= 7'(_resetSet + 7'h1); // src/main/scala/chisel3/util/Counter.scala:61:40, :77:24
end
end // always @(posedge, posedge)
always @(posedge clock) begin
rdata_REG <= readEnable; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38, :153:59
if (rdata_REG) // utility/src/main/scala/utility/SRAMTemplate.scala:153:59
rdata_hold_data_0 <= _array_0_RW0_rdata; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:4]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
for (logic [2:0] i = 3'h0; i < 3'h5; i += 3'h1) begin
_RANDOM[i] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
end // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
_resetState = _RANDOM[3'h0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
_resetSet = _RANDOM[3'h0][7:1]; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
rdata_REG = _RANDOM[3'h2][24]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_0 = {_RANDOM[3'h2][31:25], _RANDOM[3'h3], _RANDOM[3'h4][10:0]}; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
`endif // RANDOMIZE_REG_INIT
if (reset) begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
_resetState = 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
_resetSet = 7'h0; // src/main/scala/chisel3/util/Counter.scala:61:40
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_0_0 array_0 ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
.RW0_addr (writeEnable ? writeAddr : io_r_req_bits_setIdx), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :125:19
.RW0_en (readEnable | writeEnable), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :123:38
.RW0_clk (clock),
.RW0_wmode (writeEnable), // utility/src/main/scala/utility/SRAMTemplate.scala:122:52
.RW0_wdata
({_resetState ? 9'h0 : io_w_req_bits_data_0_tag,
_resetState ? 2'h0 : io_w_req_bits_data_0_ctr,
_resetState ? 39'h0 : io_w_req_bits_data_0_target}), // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51,102}
.RW0_rdata (_array_0_RW0_rdata)
);
assign io_r_resp_data_0_tag = _rdata_WIRE[49:41]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45
assign io_r_resp_data_0_ctr = _rdata_WIRE[40:39]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45
assign io_r_resp_data_0_target = _rdata_WIRE[38:0]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45
endmodule

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module SRAMTemplate_39( // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
input clock,
input reset,
input io_r_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [6:0] io_r_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [8:0] io_r_resp_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [38:0] io_r_resp_data_0_target, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [8:0] io_r_resp_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [1:0] io_r_resp_data_1_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
output [38:0] io_r_resp_data_1_target, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input io_w_req_valid, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [6:0] io_w_req_bits_setIdx, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [8:0] io_w_req_bits_data_0_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_0_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [38:0] io_w_req_bits_data_0_target, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [8:0] io_w_req_bits_data_1_tag, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_data_1_ctr, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [38:0] io_w_req_bits_data_1_target, // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
input [1:0] io_w_req_bits_waymask // utility/src/main/scala/utility/SRAMTemplate.scala:98:14
);
wire [38:0] _wdata_T_1_target; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [1:0] _wdata_T_1_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [8:0] _wdata_T_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [38:0] _wdata_T_0_target; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [1:0] _wdata_T_0_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [8:0] _wdata_T_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:126:26
wire [6:0] array_MPORT_addr; // utility/src/main/scala/utility/SRAMTemplate.scala:125:19
wire array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38
wire array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52
wire [99:0] _array_RW0_rdata; // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
reg _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30
reg [6:0] _resetSet; // src/main/scala/chisel3/util/Counter.scala:61:40
assign array_MPORT_en = io_w_req_valid | _resetState; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :122:52
assign array_raw_rdata_en = io_r_req_valid & ~array_MPORT_en; // utility/src/main/scala/utility/SRAMTemplate.scala:122:52, :123:{38,41}
assign array_MPORT_addr = _resetState ? _resetSet : io_w_req_bits_setIdx; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :125:19
assign _wdata_T_0_tag = _resetState ? 9'h0 : io_w_req_bits_data_0_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_0_ctr = _resetState ? 2'h0 : io_w_req_bits_data_0_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_0_target = _resetState ? 39'h0 : io_w_req_bits_data_0_target; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_1_tag = _resetState ? 9'h0 : io_w_req_bits_data_1_tag; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_1_ctr = _resetState ? 2'h0 : io_w_req_bits_data_1_ctr; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
assign _wdata_T_1_target = _resetState ? 39'h0 : io_w_req_bits_data_1_target; // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :126:{26,51}
reg rdata_REG; // utility/src/main/scala/utility/SRAMTemplate.scala:153:59
reg [49:0] rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82
reg [49:0] rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82
wire [49:0] _rdata_WIRE = rdata_REG ? _array_RW0_rdata[49:0] : rdata_hold_data_0; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :153:59
wire [49:0] _rdata_WIRE_1 = rdata_REG ? _array_RW0_rdata[99:50] : rdata_hold_data_1; // utility/src/main/scala/utility/Hold.scala:24:82, :25:8, utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :153:59
always @(posedge clock or posedge reset) begin
if (reset) begin
_resetState <= 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
_resetSet <= 7'h0; // src/main/scala/chisel3/util/Counter.scala:61:40
end
else begin
_resetState <= ~(_resetState & (&_resetSet)) & _resetState; // src/main/scala/chisel3/util/Counter.scala:61:40, :73:24, :117:24, :118:{16,23}, utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :111:{24,38}
if (_resetState) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30
_resetSet <= 7'(_resetSet + 7'h1); // src/main/scala/chisel3/util/Counter.scala:61:40, :77:24
end
end // always @(posedge, posedge)
always @(posedge clock) begin
rdata_REG <= array_raw_rdata_en; // utility/src/main/scala/utility/SRAMTemplate.scala:123:38, :153:59
if (rdata_REG) begin // utility/src/main/scala/utility/SRAMTemplate.scala:153:59
rdata_hold_data_0 <= _array_RW0_rdata[49:0]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
rdata_hold_data_1 <= _array_RW0_rdata[99:50]; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:105:26
end
end // always @(posedge)
`ifdef ENABLE_INITIAL_REG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`ifdef FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`FIRRTL_BEFORE_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:7]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
initial begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`ifdef INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
for (logic [3:0] i = 4'h0; i < 4'h8; i += 4'h1) begin
_RANDOM[i[2:0]] = `RANDOM; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
end // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
_resetState = _RANDOM[3'h0][0]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
_resetSet = _RANDOM[3'h0][7:1]; // src/main/scala/chisel3/util/Counter.scala:61:40, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
rdata_REG = _RANDOM[3'h4][25]; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_0 = {_RANDOM[3'h4][31:26], _RANDOM[3'h5], _RANDOM[3'h6][11:0]}; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :153:59
rdata_hold_data_1 = {_RANDOM[3'h6][31:12], _RANDOM[3'h7][29:0]}; // utility/src/main/scala/utility/Hold.scala:24:82, utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // RANDOMIZE_REG_INIT
if (reset) begin // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
_resetState = 1'h1; // utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :109:30
_resetSet = 7'h0; // src/main/scala/chisel3/util/Counter.scala:61:40
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`FIRRTL_AFTER_INITIAL // utility/src/main/scala/utility/SRAMTemplate.scala:93:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
array_8 array ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
.RW0_addr (array_MPORT_en ? array_MPORT_addr : io_r_req_bits_setIdx), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :125:19
.RW0_en (array_raw_rdata_en | array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :122:52, :123:38
.RW0_clk (clock),
.RW0_wmode (array_MPORT_en), // utility/src/main/scala/utility/SRAMTemplate.scala:122:52
.RW0_wdata
({_wdata_T_1_tag,
_wdata_T_1_ctr,
_wdata_T_1_target,
_wdata_T_0_tag,
_wdata_T_0_ctr,
_wdata_T_0_target}), // utility/src/main/scala/utility/SRAMTemplate.scala:105:26, :126:26
.RW0_rdata (_array_RW0_rdata),
.RW0_wmask (_resetState ? 2'h3 : io_w_req_bits_waymask) // utility/src/main/scala/utility/SRAMTemplate.scala:109:30, :127:{20,37}
);
assign io_r_resp_data_0_tag = _rdata_WIRE[49:41]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45
assign io_r_resp_data_0_ctr = _rdata_WIRE[40:39]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45
assign io_r_resp_data_0_target = _rdata_WIRE[38:0]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45
assign io_r_resp_data_1_tag = _rdata_WIRE_1[49:41]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45
assign io_r_resp_data_1_ctr = _rdata_WIRE_1[40:39]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45
assign io_r_resp_data_1_target = _rdata_WIRE_1[38:0]; // utility/src/main/scala/utility/Hold.scala:25:8, utility/src/main/scala/utility/SRAMTemplate.scala:93:7, :154:45
endmodule

0
src/WrBypass/WrBypass_41.sv → rtl_src/ITTAGE/WrBypass_41.sv
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0
src/WrBypass/WrBypass_43.sv → rtl_src/ITTAGE/WrBypass_43.sv
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76
rtl_src/ITTAGE/array_0_0.sv Normal file
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@ -0,0 +1,76 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_0_0( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
input [6:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [49:0] RW0_wdata,
output [49:0] RW0_rdata
);
array_0_0_ext array_0_0_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata)
);
endmodule

78
rtl_src/ITTAGE/array_8.sv Normal file
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@ -0,0 +1,78 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module array_8( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
input [6:0] RW0_addr,
input RW0_en,
input RW0_clk,
input RW0_wmode,
input [99:0] RW0_wdata,
output [99:0] RW0_rdata,
input [1:0] RW0_wmask
);
array_8_ext array_8_ext ( // utility/src/main/scala/utility/SRAMTemplate.scala:105:26
.RW0_addr (RW0_addr),
.RW0_en (RW0_en),
.RW0_clk (RW0_clk),
.RW0_wmode (RW0_wmode),
.RW0_wdata (RW0_wdata),
.RW0_rdata (RW0_rdata),
.RW0_wmask (RW0_wmask)
);
endmodule

95
rtl_src/ITTAGE/data_16x16.sv Normal file
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@ -0,0 +1,95 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
// VCS coverage exclude_file
module data_16x16( // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
input [3:0] R0_addr,
input R0_en,
input R0_clk,
output [15:0] R0_data,
input [3:0] W0_addr,
input W0_en,
input W0_clk,
input [15:0] W0_data,
input [3:0] W1_addr,
input W1_en,
input W1_clk,
input [15:0] W1_data
);
reg [15:0] Memory[0:15]; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
always @(posedge W0_clk) begin // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
if (W0_en & 1'h1) // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
Memory[W0_addr] <= W0_data; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
if (W1_en & 1'h1) // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
Memory[W1_addr] <= W1_data; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_ // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
reg [31:0] _RANDOM_MEM; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
initial begin // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
`ifdef RANDOMIZE_MEM_INIT // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
for (logic [4:0] i = 5'h0; i < 5'h10; i += 5'h1) begin
_RANDOM_MEM = `RANDOM; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
Memory[i[3:0]] = _RANDOM_MEM[15:0]; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
end // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
`endif // RANDOMIZE_MEM_INIT
end // initial
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 16'bx; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
endmodule

95
rtl_src/ITTAGE/data_32x16.sv Normal file
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@ -0,0 +1,95 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
// VCS coverage exclude_file
module data_32x16( // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
input [4:0] R0_addr,
input R0_en,
input R0_clk,
output [15:0] R0_data,
input [4:0] W0_addr,
input W0_en,
input W0_clk,
input [15:0] W0_data,
input [4:0] W1_addr,
input W1_en,
input W1_clk,
input [15:0] W1_data
);
reg [15:0] Memory[0:31]; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
always @(posedge W0_clk) begin // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
if (W0_en & 1'h1) // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
Memory[W0_addr] <= W0_data; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
if (W1_en & 1'h1) // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
Memory[W1_addr] <= W1_data; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_ // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
reg [31:0] _RANDOM_MEM; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
initial begin // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
`INIT_RANDOM_PROLOG_ // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
`ifdef RANDOMIZE_MEM_INIT // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
for (logic [5:0] i = 6'h0; i < 6'h20; i += 6'h1) begin
_RANDOM_MEM = `RANDOM; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
Memory[i[4:0]] = _RANDOM_MEM[15:0]; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
end // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
`endif // RANDOMIZE_MEM_INIT
end // initial
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 16'bx; // utility/src/main/scala/utility/DataModuleTemplate.scala:211:17
endmodule

89
rtl_src/ITTAGE/data_mem_0_4x2.sv Normal file
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@ -0,0 +1,89 @@
// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
// VCS coverage exclude_file
module data_mem_0_4x2( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
input [1:0] R0_addr,
input R0_en,
input R0_clk,
output [1:0] R0_data,
input [1:0] W0_addr,
input W0_en,
input W0_clk,
input [1:0] W0_data
);
reg [1:0] Memory[0:3]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
always @(posedge W0_clk) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
if (W0_en & 1'h1) // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
Memory[W0_addr] <= W0_data; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
end // always @(posedge)
`ifdef ENABLE_INITIAL_MEM_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
reg [31:0] _RANDOM_MEM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
`ifdef RANDOMIZE_MEM_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
for (logic [2:0] i = 3'h0; i < 3'h4; i += 3'h1) begin
_RANDOM_MEM = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
Memory[i[1:0]] = _RANDOM_MEM[1:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
end // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
`endif // RANDOMIZE_MEM_INIT
end // initial
`endif // ENABLE_INITIAL_MEM_
assign R0_data = R0_en ? Memory[R0_addr] : 2'bx; // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
endmodule

0
src/RAS.txt → rtl_src/RAS.txt
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./src/ITTAGE/CAMTemplate_41.sv
./src/ITTAGE/CAMTemplate_43.sv
./src/ITTAGE/Folded1WDataModuleTemplate.sv
./src/ITTAGE/Folded1WDataModuleTemplate_2.sv
./src/ITTAGE/FoldedSRAMTemplate_21.sv
./src/ITTAGE/FoldedSRAMTemplate_25.sv
./src/ITTAGE/ITTage.sv
./src/ITTAGE/ITTageTable.sv
./src/ITTAGE/ITTageTable_1.sv
./src/ITTAGE/ITTageTable_2.sv
./src/ITTAGE/ITTageTable_3.sv
./src/ITTAGE/ITTageTable_4.sv
./src/ITTAGE/SRAMTemplate_35.sv
./src/ITTAGE/SRAMTemplate_39.sv
./src/ITTAGE/WrBypass_41.sv
./src/ITTAGE/WrBypass_43.sv
./src/ITTAGE/array_0_0.sv
./src/ITTAGE/array_8.sv
./src/ITTAGE/data_16x16.sv
./src/ITTAGE/data_32x16.sv
./src/ITTAGE/data_mem_0_4x2.sv
#
./src/WrBypass/WrBypass.sv
./src/WrBypass/WrBypass_32.sv
./src/WrBypass/WrBypass_33.sv
./src/common/ext_sram.v
./src/common/DelayN_2.sv

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module WrBypass_41( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
input clock,
input reset,
input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input [7:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input [1:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output [1:0] io_hit_data_0_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
);
wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire [1:0] data_mem_io_hit_data_0_bits_MPORT_addr =
{|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83
wire hit =
_idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83, :63:29
reg [2:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13
wire [1:0] state_reg_touch_way_sized =
hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37
always @(posedge clock or posedge reset) begin
if (reset) begin
ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
end
else begin
ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31
ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31
ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
if (io_wen) // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
state_reg <=
{~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1],
state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
`endif // RANDOMIZE_REG_INIT
if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
CAMTemplate_41 idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
.clock (clock),
.io_r_req_0_idx (io_write_idx),
.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
.io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26}
.io_w_bits_data_idx (io_write_idx),
.io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12
);
data_mem_0_4x2 data_mem_0_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
.R0_addr (data_mem_io_hit_data_0_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10
.R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
.R0_clk (clock),
.R0_data (io_hit_data_0_bits),
.W0_addr (hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29
.W0_en (io_wen),
.W0_clk (clock),
.W0_data (io_write_data_0)
);
assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29
endmodule

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// Generated by CIRCT firtool-1.61.0
// Standard header to adapt well known macros for register randomization.
`ifndef RANDOMIZE
`ifdef RANDOMIZE_MEM_INIT
`define RANDOMIZE
`endif // RANDOMIZE_MEM_INIT
`endif // not def RANDOMIZE
`ifndef RANDOMIZE
`ifdef RANDOMIZE_REG_INIT
`define RANDOMIZE
`endif // RANDOMIZE_REG_INIT
`endif // not def RANDOMIZE
// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
`ifndef RANDOM
`define RANDOM $random
`endif // not def RANDOM
// Users can define INIT_RANDOM as general code that gets injected into the
// initializer block for modules with registers.
`ifndef INIT_RANDOM
`define INIT_RANDOM
`endif // not def INIT_RANDOM
// If using random initialization, you can also define RANDOMIZE_DELAY to
// customize the delay used, otherwise 0.002 is used.
`ifndef RANDOMIZE_DELAY
`define RANDOMIZE_DELAY 0.002
`endif // not def RANDOMIZE_DELAY
// Define INIT_RANDOM_PROLOG_ for use in our modules below.
`ifndef INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE
`ifdef VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
`else // VERILATOR
`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
`endif // VERILATOR
`else // RANDOMIZE
`define INIT_RANDOM_PROLOG_
`endif // RANDOMIZE
`endif // not def INIT_RANDOM_PROLOG_
// Include register initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_REG_
`define ENABLE_INITIAL_REG_
`endif // not def ENABLE_INITIAL_REG_
`endif // not def SYNTHESIS
// Include rmemory initializers in init blocks unless synthesis is set
`ifndef SYNTHESIS
`ifndef ENABLE_INITIAL_MEM_
`define ENABLE_INITIAL_MEM_
`endif // not def ENABLE_INITIAL_MEM_
`endif // not def SYNTHESIS
module WrBypass_43( // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
input clock,
input reset,
input io_wen, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input [8:0] io_write_idx, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
input [1:0] io_write_data_0, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output io_hit, // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
output [1:0] io_hit_data_0_bits // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
);
wire _idx_tag_cam_io_r_resp_0_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
wire _idx_tag_cam_io_r_resp_0_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
reg ever_written_0; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
reg ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:57:29
wire hits_oh_1 = _idx_tag_cam_io_r_resp_0_1 & ever_written_1; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_2 = _idx_tag_cam_io_r_resp_0_2 & ever_written_2; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire hits_oh_3 = _idx_tag_cam_io_r_resp_0_3 & ever_written_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83
wire [1:0] data_mem_io_hit_data_0_bits_MPORT_addr =
{|{hits_oh_3, hits_oh_2}, hits_oh_3 | hits_oh_1}; // src/main/scala/chisel3/util/OneHot.scala:30:18, :32:{10,14,28}, src/main/scala/xiangshan/frontend/WrBypass.scala:61:83
wire hit =
_idx_tag_cam_io_r_resp_0_0 & ever_written_0 | hits_oh_1 | hits_oh_2 | hits_oh_3; // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27, :57:29, :61:83, :63:29
reg [2:0] state_reg; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
wire [1:0] enq_idx = {state_reg[2], state_reg[2] ? state_reg[1] : state_reg[0]}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :243:38, :245:38, :249:12, :250:16, rocket-chip/src/main/scala/util/package.scala:155:13
wire [1:0] state_reg_touch_way_sized =
hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :87:37
always @(posedge clock or posedge reset) begin
if (reset) begin
ever_written_0 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 <= 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg <= 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
end
else begin
ever_written_0 <= io_wen & ~hit & enq_idx == 2'h0 | ever_written_0; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:14, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
ever_written_1 <= io_wen & ~hit & enq_idx == 2'h1 | ever_written_1; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31
ever_written_2 <= io_wen & ~hit & enq_idx == 2'h2 | ever_written_2; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :95:30, :98:31
ever_written_3 <= io_wen & ~hit & (&enq_idx) | ever_written_3; // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/xiangshan/frontend/WrBypass.scala:57:29, :63:29, :92:19, :93:18, :98:31
if (io_wen) // src/main/scala/xiangshan/frontend/WrBypass.scala:34:14
state_reg <=
{~(state_reg_touch_way_sized[1]),
state_reg_touch_way_sized[1] ? ~(state_reg_touch_way_sized[0]) : state_reg[1],
state_reg_touch_way_sized[1] ? state_reg[0] : ~(state_reg_touch_way_sized[0])}; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, :196:{33,43}, :202:12, :203:16, :206:16, :218:7, :245:38, rocket-chip/src/main/scala/util/package.scala:155:13, src/main/scala/xiangshan/frontend/WrBypass.scala:87:37
end
end // always @(posedge, posedge)
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // FIRRTL_BEFORE_INITIAL
logic [31:0] _RANDOM[0:0]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
initial begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // INIT_RANDOM_PROLOG_
`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
_RANDOM[/*Zero width*/ 1'b0] = `RANDOM; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
ever_written_0 = _RANDOM[/*Zero width*/ 1'b0][4]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 = _RANDOM[/*Zero width*/ 1'b0][5]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 = _RANDOM[/*Zero width*/ 1'b0][6]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 = _RANDOM[/*Zero width*/ 1'b0][7]; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg = _RANDOM[/*Zero width*/ 1'b0][10:8]; // rocket-chip/src/main/scala/util/Replacement.scala:168:72, src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
`endif // RANDOMIZE_REG_INIT
if (reset) begin // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
ever_written_0 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_1 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_2 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
ever_written_3 = 1'h0; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :57:29
state_reg = 3'h0; // rocket-chip/src/main/scala/util/Replacement.scala:168:72
end
end // initial
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
`endif // FIRRTL_AFTER_INITIAL
`endif // ENABLE_INITIAL_REG_
CAMTemplate_43 idx_tag_cam ( // src/main/scala/xiangshan/frontend/WrBypass.scala:53:27
.clock (clock),
.io_r_req_0_idx (io_write_idx),
.io_r_resp_0_0 (_idx_tag_cam_io_r_resp_0_0),
.io_r_resp_0_1 (_idx_tag_cam_io_r_resp_0_1),
.io_r_resp_0_2 (_idx_tag_cam_io_r_resp_0_2),
.io_r_resp_0_3 (_idx_tag_cam_io_r_resp_0_3),
.io_w_valid (io_wen & ~hit), // src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :107:{23,26}
.io_w_bits_data_idx (io_write_idx),
.io_w_bits_index (enq_idx) // rocket-chip/src/main/scala/util/Replacement.scala:249:12
);
data_mem_0_4x2 data_mem_0_ext ( // src/main/scala/xiangshan/frontend/WrBypass.scala:54:21
.R0_addr (data_mem_io_hit_data_0_bits_MPORT_addr), // src/main/scala/chisel3/util/OneHot.scala:32:10
.R0_en (1'h1), // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7
.R0_clk (clock),
.R0_data (io_hit_data_0_bits),
.W0_addr (hit ? data_mem_io_hit_data_0_bits_MPORT_addr : enq_idx), // rocket-chip/src/main/scala/util/Replacement.scala:249:12, src/main/scala/chisel3/util/OneHot.scala:32:10, src/main/scala/xiangshan/frontend/WrBypass.scala:63:29, :83:29
.W0_en (io_wen),
.W0_clk (clock),
.W0_data (io_write_data_0)
);
assign io_hit = hit; // src/main/scala/xiangshan/frontend/WrBypass.scala:26:7, :63:29
endmodule

0
src/common/Composer.sv → rtl_src/common/Composer.sv
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0
src/common/DelayN_2.sv → rtl_src/common/DelayN_2.sv
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0
src/common/DelayN_4.sv → rtl_src/common/DelayN_4.sv
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0
src/common/DelayN_5.sv → rtl_src/common/DelayN_5.sv
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0
src/common/DelayN_6.sv → rtl_src/common/DelayN_6.sv
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0
src/common/Predictor.sv → rtl_src/common/Predictor.sv
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0
src/common/ext_sram.v → rtl_src/common/ext_sram.v
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0
src/uFTB.txt → rtl_src/uFTB.txt
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0
src/uFTB/FauFTB.sv → rtl_src/uFTB/FauFTB.sv
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0
src/uFTB/FauFTBWay.sv → rtl_src/uFTB/FauFTBWay.sv
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33
src/Tage_SC.txt
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@ -1,33 +0,0 @@
./src/TageSC/CAMTemplate.sv
./src/TageSC/CAMTemplate_32.sv
./src/TageSC/CAMTemplate_33.sv
./src/TageSC/FoldedSRAMTemplate.sv
./src/TageSC/FoldedSRAMTemplate_1.sv
./src/TageSC/FoldedSRAMTemplate_20.sv
./src/TageSC/SCTable.sv
./src/TageSC/SCTable_1.sv
./src/TageSC/SCTable_2.sv
./src/TageSC/SCTable_3.sv
./src/TageSC/SRAMTemplate_10.sv
./src/TageSC/SRAMTemplate_11.sv
./src/TageSC/SRAMTemplate_30.sv
./src/TageSC/SRAMTemplate_31.sv
./src/TageSC/TageBTable.sv
./src/TageSC/TageTable.sv
./src/TageSC/TageTable_1.sv
./src/TageSC/TageTable_2.sv
./src/TageSC/TageTable_3.sv
#./src/TageSC/Tage_SC.sv
./src/TageSC/array_4.sv
./src/TageSC/array_5.sv
./src/TageSC/array_6.sv
./src/TageSC/array_7.sv
./src/TageSC/data_mem_0_8x3.sv
./src/TageSC/data_mem_16x12.sv
./src/TageSC/data_mem_8x4.sv
#
./src/WrBypass/WrBypass.sv
./src/WrBypass/WrBypass_32.sv
./src/WrBypass/WrBypass_33.sv
./src/common/ext_sram.v
./src/common/DelayN_2.sv

63
test_src/uFTB_raw/FTBEntry.py Normal file
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from types import SimpleNamespace
import random
class FTBEntry:
class BrSlot:
valid=False
offset=0
target=0
targetCoA=0
alwaysTaken=False
class TailSlot:
valid=False
offset=0
target=0
targetCoA=0
alwaysTaken=False
is_br_sharing=False
def __init__(self):
self.valid = False
self.brSlot = self.BrSlot()
self.tailSlot = self.TailSlot()
self.pftAddr = 0
self.carry = False
self.isCall = False
self.isRet = False
self.isJalr = False
self.rviCall = False
self.brSlot.valid = False
self.tailSlot.valid = False
def gen_ftb_entry(pc, br_slotv, tail_slotv) -> FTBEntry:
entry = FTBEntry()
entry.valid = True
if br_slotv:
entry.brSlot.valid = True
entry.brSlot.target = random.randint(0, 2**20)
entry.brSlot.offset = random.randint(0, 2**12)
entry.brSlot.alwaysTaken = random.choice([True, False])
if tail_slotv:
entry.tailSlot.valid = True
entry.tailSlot.target = random.randint(0, 2**20)
entry.tailSlot.offset = random.randint(0, 2**12)
entry.tailSlot.is_br_sharing = random.choice([True, False])
entry.pftAddr = pc + random.randint(0, 2**12)
if tail_slotv and entry.tailSlot.is_br_sharing == False:
flag = random.randint(0, 3)
if flag == 0:
entry.isCall = True
elif flag == 1:
entry.isRet = True
elif flag == 2:
entry.isJalr = True
else:
entry.rviCall = True
return entry

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test_src/uFTB_raw/FauFTB.py Normal file
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from typing import Any, Tuple
from UT_FauFTB import *
from FTBEntry import *
from collections import namedtuple
class FauFTB(DUTFauFTB):
class Io_in_bits_s0_pc:
def __init__(self, outer_instance: "FauFTB"):
self.outer_instance = outer_instance
for i in range(4):
setattr(self, f"_{i}", getattr(outer_instance, f"io_in_bits_s0_pc_{i}"))
def set(self, arg):
for i in range(4):
getattr(self, f"_{i}").value = arg
class Io_out_s1_pc:
def __init__(self, outer_instance: "FauFTB"):
self.outer_instance = outer_instance
for i in range(4):
setattr(self, f"_{i}", getattr(outer_instance, f"io_out_s1_pc_{i}"))
def get(self):
assert all(self._0.value == getattr(self, f"_{i}").value for i in range(4))
return self._0
class Io_s0_fire:
def __init__(self, outer_instance: "FauFTB"):
self.outer_instance = outer_instance
for i in range(4):
setattr(self, f"_{i}", getattr(outer_instance, f"io_s0_fire_{i}"))
def set(self,arg):
for i in range(4):
getattr(self, f"_{i}").value = arg
class Io_out_s1_full_pred:
def __init__(self, outer_instance: "FauFTB"):
self.outer_instance = outer_instance
self.sig_array = [
"br_taken_mask_0",
"br_taken_mask_1",
"slot_valids_0",
"slot_valids_1",
"targets_0",
"targets_1",
"offsets_0",
"offsets_1",
"fallThroughAddr",
"is_br_sharing",
"hit",
]
for i in range(4):
setattr(
self,
f"_{i}",
namedtuple(f"_{i}", self.sig_array)(
*[
getattr(outer_instance, f"io_out_s1_full_pred_{i}_{sig}")
for sig in self.sig_array
]
),
)
def get(self):
for sig in self.sig_array:
assert all(
getattr(self, f"_{i}")._asdict()[sig].value
== getattr(self, f"_{i}")._asdict()[sig].value
for i in range(4)
)
return self._0
class Io_out_last_stage_meta:
def __init__(self, outer_instance: "FauFTB"):
self.outer_instance = outer_instance
self.resp_meta_hit_r_1 = xsp.XPin(
outer_instance.io_out_last_stage_meta.xdata.SubDataRef(
"resp_meta_hit_r_1",
0,
0
),
outer_instance.event,
)
self.resp_meta_pred_way_r_1 = xsp.XPin(
outer_instance.io_out_last_stage_meta.xdata.SubDataRef(
"resp_meta_pred_way_r_1",
1,
5
),
outer_instance.event,
)
pass
pass
class Io_update_bits_ftb_entry:
def __init__(self, outer_instance: "FauFTB"):
self.outer_instance = outer_instance
self.sig_array = [
"brSlots_0_valid",
"brSlots_0_offset",
"brSlots_0_lower",
"brSlots_0_tarStat",
"always_taken_0",
"tailSlot_valid",
"tailSlot_offset",
"tailSlot_lower",
"tailSlot_tarStat",
"tailSlot_sharing",
"always_taken_1",
"pftAddr",
"carry",
]
namedtuple(
"Io_update_bits_ftb_entry",
self.sig_array,
)(
*[
setattr(
self,
sig,
getattr(outer_instance, f"io_update_bits_ftb_entry_{sig}"),
)
for sig in self.sig_array
]
)
def __init__(self):
super().__init__()
self.io_in_bits_s0_pc = self.Io_in_bits_s0_pc(self)
self.io_out_s1_pc = self.Io_out_s1_pc(self)
self.io_s0_fire = self.Io_s0_fire(self)
self.io_out_s1_full_pred = self.Io_out_s1_full_pred(self)
self._io_out_last_stage_meta = self.Io_out_last_stage_meta(self)
self.io_update_bits_ftb_entry = self.Io_update_bits_ftb_entry(self)
self.init_clock("clock")
def finalize(self):
super().finalize()
def check_dup_equation(self, *inputs):
return all(i == inputs[0] for i in inputs)
def s1_full_pred(self) -> Tuple[int, FTBEntry, int, int]:
io_out_s1_full_pred = self.io_out_s1_full_pred.get()
entry = FTBEntry()
# FauFTB
entry.valid = io_out_s1_full_pred.hit.value
entry.pftAddr = io_out_s1_full_pred.fallThroughAddr.value
# Br slot
entry.brSlot.valid = io_out_s1_full_pred.slot_valids_0.value
entry.brSlot.offset = io_out_s1_full_pred.offsets_0.value
entry.brSlot.target = io_out_s1_full_pred.targets_0.value
entry.brSlot.targetCoA = None
entry.brSlot.alwaysTaken = io_out_s1_full_pred.br_taken_mask_0.value
# Tail slot
entry.tailSlot.valid = io_out_s1_full_pred.slot_valids_1.value
entry.tailSlot.offset = io_out_s1_full_pred.offsets_1.value
entry.tailSlot.target = io_out_s1_full_pred.targets_1.value
entry.tailSlot.targetCoA = None
entry.tailSlot.alwaysTaken = io_out_s1_full_pred.br_taken_mask_1.value
entry.tailSlot.is_br_sharing = io_out_s1_full_pred.is_br_sharing.value
return (self.io_out_s1_pc.get().value, entry, io_out_s1_full_pred.br_taken_mask_0.value, io_out_s1_full_pred.br_taken_mask_1.value)
def update_ftb_entry(self, update_pc: int, entry: FTBEntry, taken: Tuple[int, int]):
self.io_update_bits_pc.value = update_pc
self.io_update_bits_br_taken_mask_0.value = taken[0]
self.io_update_bits_br_taken_mask_1.value = taken[1]
update = self.io_update_bits_ftb_entry
update.brSlots_0_valid.value = entry.brSlot.valid
update.brSlots_0_offset.value = entry.brSlot.offset
update.brSlots_0_lower.value = entry.brSlot.target
update.brSlots_0_tarStat.value = entry.brSlot.targetCoA
update.always_taken_0.value = entry.brSlot.alwaysTaken
update.tailSlot_valid.value = entry.tailSlot.valid
update.tailSlot_offset.value = entry.tailSlot.offset
update.tailSlot_lower.value = entry.tailSlot.target
update.tailSlot_tarStat.value = entry.tailSlot.targetCoA
update.tailSlot_sharing.value = entry.tailSlot.is_br_sharing
update.always_taken_1.value = entry.tailSlot.alwaysTaken
update.pftAddr.value = entry.pftAddr
update.carry.value = entry.carry

59
test_src/uFTB_raw/main.py Normal file
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from typing import List, Tuple
from FauFTB import *
from FTBEntry import *
EntryList: List[Tuple[int, FTBEntry, bool, bool]] = []
def ftb_entry_list():
for i in range(100):
pc = random.randint(0, 2**39)
gentry = gen_ftb_entry(pc, True, True)
EntryList.append(
(pc, gentry, random.choice([True, False]), random.choice([True, False]))
)
# print("ftb_entry_list", EntryList[i][1].brSlot)
return EntryList
def get_pred(uFTB: FauFTB, pc: int) -> Tuple[int, FTBEntry, bool, bool]:
uFTB.io_in_bits_s0_pc.set(pc)
uFTB.io_ctrl_ubtb_enable.value = 1
uFTB.io_s0_fire.set(1)
uFTB.io_s1_fire_0.value = 1
uFTB.io_s2_fire_0.value = 1
return uFTB.s1_full_pred()
def set_update(uFTB: FauFTB, entry: Tuple[int, FTBEntry, bool, bool]):
uFTB.io_update_valid.value = True
uFTB.io_update_bits_pc.value = entry[0]
# print("set_update", entry[1].brSlot)
uFTB.update_ftb_entry(entry[0], entry[1], (entry[2], entry[3]))
def main():
uFTB: FauFTB = FauFTB()
ftb_entry_list()
uFTB.reset.value = 1
uFTB.Step(100)
uFTB.reset.value = 0
for i in range(100):
# print("main1", EntryList[i - 10][1].brSlot)
j = i % 40
pred = get_pred(uFTB, EntryList[j][0])
if i > 9:
# print("main2", EntryList[i - 10][1].brSlot)
set_update(uFTB, EntryList[(i - 10)%40])
pass
print("main", pred[0], pred[1].__dict__)
uFTB.Step(1)
uFTB.finalize()
if __name__ == "__main__":
main()