Optimize the directory structure and update the Makefile

mk/FTB.mk

@@ -1,5 +1,5 @@
-TOP_ENTRY := ./rtl_src/FTB/FTB.sv
-TOP_FILES := ./rtl_src/FTB.txt
+TOP_ENTRY := ./rtl/FTB/FTB.sv
+TOP_FILES := ./rtl/FTB.txt
 TL ?= cpp
 
 ifneq ($(TARGET),)
@@ -40,8 +40,6 @@ ftb:
 
 	@mkdir -p out
 	rm -rf ${TARGET} 
-	picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${TL} \
+	picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${TL} -c\
 		 -t ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE}
-		
-	cd ${TARGET} && make
 

mk/ITTAGE.mk

@@ -1,5 +1,5 @@
-TOP_ENTRY := ./rtl_src/ITTAGE/ITTage.sv
-TOP_FILES := ./rtl_src/ITTAGE.txt
+TOP_ENTRY := ./rtl/ITTAGE/ITTage.sv
+TOP_FILES := ./rtl/ITTAGE.txt
 TL ?= cpp
 
 ifneq ($(TARGET),)
@@ -40,8 +40,6 @@ ittage:
 
 	@mkdir -p out
 	rm -rf ${TARGET} 
-	picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${TL} \
+	picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${TL} -c\
 		 -t ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE}
-		
-	cd ${TARGET} && make
 

mk/RAS.mk

@@ -1,5 +1,5 @@
-TOP_ENTRY := ./rtl_src/RAS/RAS.sv
-TOP_FILES := ./rtl_src/RAS.txt
+TOP_ENTRY := ./rtl/RAS/RAS.sv
+TOP_FILES := ./rtl/RAS.txt
 TL ?= cpp
 
 ifneq ($(TARGET),)
@@ -40,8 +40,6 @@ ras:
 
 	@mkdir -p out
 	rm -rf ${TARGET} 
-	picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${TL} \
+	picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${TL} -c\
 		 -t ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE}
 		
-	cd ${TARGET} && make
-

mk/Tage.mk

@@ -1,5 +1,5 @@
-TOP_ENTRY := ./rtl_src/TageSC/Tage_SC.sv
-TOP_FILES := ./rtl_src/Tage_SC.txt
+TOP_ENTRY := ./rtl/TageSC/Tage_SC.sv
+TOP_FILES := ./rtl/Tage_SC.txt
 TL ?= cpp
 
 ifneq ($(TARGET),)
@@ -40,8 +40,6 @@ tage_sc:
 
 	@mkdir -p out
 	rm -rf ${TARGET} 
-	picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${TL} \
+	picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${TL} -c\
 		 -t ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE}
 		
-	cd ${TARGET} && make
-

mk/uFTB.mk

@@ -1,5 +1,5 @@
-TOP_ENTRY := ./rtl_src/uFTB/FauFTB.sv
-TOP_FILES := ./rtl_src/uFTB.txt
+TOP_ENTRY := ./rtl/uFTB/FauFTB.sv
+TOP_FILES := ./rtl/uFTB.txt
 TL ?= cpp
 
 ifneq ($(TARGET),)
@@ -40,8 +40,6 @@ uftb:
 
 	@mkdir -p out
 	rm -rf ${TARGET} 
-	picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${TL} \
+	picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${TL} -c\
 		 -t ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE}
 		
-	cd ${TARGET} && make
-

rtl/FTB.txt

@@ -0,0 +1,9 @@
+./rtl/FTB/FTBBank.sv
+./rtl/FTB/FTBEntryGen.sv
+./rtl/FTB/SRAMTemplate_9.sv
+./rtl/FTB/array_3.sv
+./rtl/common/ext_sram.v
+./rtl/common/DelayN_2.sv
+./rtl/common/DelayN_4.sv
+./rtl/common/DelayN_5.sv
+./rtl/common/DelayN_6.sv

rtl/ITTAGE.txt

@@ -0,0 +1,24 @@
+./rtl/ITTAGE/CAMTemplate_41.sv
+./rtl/ITTAGE/CAMTemplate_43.sv
+./rtl/ITTAGE/Folded1WDataModuleTemplate.sv
+./rtl/ITTAGE/Folded1WDataModuleTemplate_2.sv
+./rtl/ITTAGE/FoldedSRAMTemplate_21.sv
+./rtl/ITTAGE/FoldedSRAMTemplate_25.sv
+./rtl/ITTAGE/ITTage.sv
+./rtl/ITTAGE/ITTageTable.sv
+./rtl/ITTAGE/ITTageTable_1.sv
+./rtl/ITTAGE/ITTageTable_2.sv
+./rtl/ITTAGE/ITTageTable_3.sv
+./rtl/ITTAGE/ITTageTable_4.sv
+./rtl/ITTAGE/SRAMTemplate_35.sv
+./rtl/ITTAGE/SRAMTemplate_39.sv
+./rtl/ITTAGE/WrBypass_41.sv
+./rtl/ITTAGE/WrBypass_43.sv
+./rtl/ITTAGE/array_0_0.sv
+./rtl/ITTAGE/array_8.sv
+./rtl/ITTAGE/data_16x16.sv
+./rtl/ITTAGE/data_32x16.sv
+./rtl/ITTAGE/data_mem_0_4x2.sv
+#
+./rtl/common/ext_sram.v
+./rtl/common/DelayN_2.sv

rtl/RAS.txt

@@ -0,0 +1,3 @@
+./rtl/RAS/RASStack.sv
+./rtl/common/ext_sram.v
+./rtl/common/DelayN_2.sv

rtl/Tage_SC.txt

@@ -0,0 +1,27 @@
+./rtl/ITTAGE/CAMTemplate_41.sv
+./rtl/ITTAGE/CAMTemplate_43.sv
+./rtl/ITTAGE/Folded1WDataModuleTemplate.sv
+./rtl/ITTAGE/Folded1WDataModuleTemplate_2.sv
+./rtl/ITTAGE/FoldedSRAMTemplate_21.sv
+./rtl/ITTAGE/FoldedSRAMTemplate_25.sv
+./rtl/ITTAGE/ITTage.sv
+./rtl/ITTAGE/ITTageTable.sv
+./rtl/ITTAGE/ITTageTable_1.sv
+./rtl/ITTAGE/ITTageTable_2.sv
+./rtl/ITTAGE/ITTageTable_3.sv
+./rtl/ITTAGE/ITTageTable_4.sv
+./rtl/ITTAGE/SRAMTemplate_35.sv
+./rtl/ITTAGE/SRAMTemplate_39.sv
+./rtl/ITTAGE/WrBypass_41.sv
+./rtl/ITTAGE/WrBypass_43.sv
+./rtl/ITTAGE/array_0_0.sv
+./rtl/ITTAGE/array_8.sv
+./rtl/ITTAGE/data_16x16.sv
+./rtl/ITTAGE/data_32x16.sv
+./rtl/ITTAGE/data_mem_0_4x2.sv
+#
+./rtl/WrBypass/WrBypass.sv
+./rtl/WrBypass/WrBypass_32.sv
+./rtl/WrBypass/WrBypass_33.sv
+./rtl/common/ext_sram.v
+./rtl/common/DelayN_2.sv

rtl/uFTB.txt

@@ -0,0 +1,3 @@
+./rtl/uFTB/FauFTBWay.sv
+./rtl/common/ext_sram.v
+./rtl/common/DelayN_2.sv

rtl_src/FTB.txt

@@ -1,9 +0,0 @@
-./src/FTB/FTBBank.sv
-./src/FTB/FTBEntryGen.sv
-./src/FTB/SRAMTemplate_9.sv
-./src/FTB/array_3.sv
-./src/common/ext_sram.v
-./src/common/DelayN_2.sv
-./src/common/DelayN_4.sv
-./src/common/DelayN_5.sv
-./src/common/DelayN_6.sv

rtl_src/ITTAGE.txt

@@ -1,24 +0,0 @@
-./src/ITTAGE/CAMTemplate_41.sv
-./src/ITTAGE/CAMTemplate_43.sv
-./src/ITTAGE/Folded1WDataModuleTemplate.sv
-./src/ITTAGE/Folded1WDataModuleTemplate_2.sv
-./src/ITTAGE/FoldedSRAMTemplate_21.sv
-./src/ITTAGE/FoldedSRAMTemplate_25.sv
-./src/ITTAGE/ITTage.sv
-./src/ITTAGE/ITTageTable.sv
-./src/ITTAGE/ITTageTable_1.sv
-./src/ITTAGE/ITTageTable_2.sv
-./src/ITTAGE/ITTageTable_3.sv
-./src/ITTAGE/ITTageTable_4.sv
-./src/ITTAGE/SRAMTemplate_35.sv
-./src/ITTAGE/SRAMTemplate_39.sv
-./src/ITTAGE/WrBypass_41.sv
-./src/ITTAGE/WrBypass_43.sv
-./src/ITTAGE/array_0_0.sv
-./src/ITTAGE/array_8.sv
-./src/ITTAGE/data_16x16.sv
-./src/ITTAGE/data_32x16.sv
-./src/ITTAGE/data_mem_0_4x2.sv
-#
-./src/common/ext_sram.v
-./src/common/DelayN_2.sv

rtl_src/RAS.txt

@@ -1,3 +0,0 @@
-./src/RAS/RASStack.sv
-./src/common/ext_sram.v
-./src/common/DelayN_2.sv

rtl_src/Tage_SC.txt

@@ -1,27 +0,0 @@
-./src/ITTAGE/CAMTemplate_41.sv
-./src/ITTAGE/CAMTemplate_43.sv
-./src/ITTAGE/Folded1WDataModuleTemplate.sv
-./src/ITTAGE/Folded1WDataModuleTemplate_2.sv
-./src/ITTAGE/FoldedSRAMTemplate_21.sv
-./src/ITTAGE/FoldedSRAMTemplate_25.sv
-./src/ITTAGE/ITTage.sv
-./src/ITTAGE/ITTageTable.sv
-./src/ITTAGE/ITTageTable_1.sv
-./src/ITTAGE/ITTageTable_2.sv
-./src/ITTAGE/ITTageTable_3.sv
-./src/ITTAGE/ITTageTable_4.sv
-./src/ITTAGE/SRAMTemplate_35.sv
-./src/ITTAGE/SRAMTemplate_39.sv
-./src/ITTAGE/WrBypass_41.sv
-./src/ITTAGE/WrBypass_43.sv
-./src/ITTAGE/array_0_0.sv
-./src/ITTAGE/array_8.sv
-./src/ITTAGE/data_16x16.sv
-./src/ITTAGE/data_32x16.sv
-./src/ITTAGE/data_mem_0_4x2.sv
-#
-./src/WrBypass/WrBypass.sv
-./src/WrBypass/WrBypass_32.sv
-./src/WrBypass/WrBypass_33.sv
-./src/common/ext_sram.v
-./src/common/DelayN_2.sv

rtl_src/uFTB.txt

@@ -1,3 +0,0 @@
-./src/uFTB/FauFTBWay.sv
-./src/common/ext_sram.v
-./src/common/DelayN_2.sv