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2776 Commits

Author SHA1 Message Date
zhir 46aa158dcc AArch64: NEON omatcopy CT/RT kernels 2026-06-20 22:54:04 +03:00
Martin Kroeker ef20ea1644
Merge pull request #5828 from amritahs-ibm/fix_dcbt_constraints 
Fix incorrect inline assembly constraints in dcbt prefetch instructions
 2026-06-15 11:22:10 +02:00
Ayappan Perumal faf7ddbbea Fix AIX build with OpenXL (ibm-clang) 2026-06-10 04:22:48 -05:00
Martin Kroeker 94f85eb6b1
Merge pull request #5822 from ErnstPeng/la-dev 
optimize zgemm, ic/zamin and sdot lsx kernel for 2k3000 cpu
 2026-06-09 18:15:48 +02:00
amritahs-ibm 7e3877f263
Merge branch 'develop' into fix_dcbt_constraints 2026-06-09 14:45:02 +05:30
Martin Kroeker 901c214a9b
Merge pull request #5827 from amritahs-ibm/use_lxvp_builtins 
Power10: Replace vector pair loads with __builtin_vsx_lxvp
 2026-06-09 09:41:47 +02:00
pengxu 4850f86e3d optimize sdot lsx kernel 2026-06-08 14:26:03 +08:00
pengxu d1df5928ae optimize ic/zamin lsx kernel 2026-06-08 14:25:26 +08:00
Martin Kroeker 16a5ea5b4c
Merge pull request #5829 from martin-frbg/issue5825 
Fix OpenMP reentrancy issues in LLVM compilations with gmake on ARM64
 2026-06-06 10:55:52 +02:00
Martin Kroeker 1145c75a96
Comment out the libclang_rt.builtins kludge in preparation for removal 2026-06-05 23:06:28 +02:00
Amrita H S 831b822b94 Fix incorrect inline assembly constraints in dcbt prefetch instructions 
Corrected the register constraints for the PowerPC dcbt (Data Cache Block
Touch) instruction in Power10 kernel implementations. The dcbt instruction
has special behavior where if the first operand (RA) is r0, it uses the
value 0 instead of the register contents. Therefore, RA must use the "b"
constraint (any GPR except r0), while RB can use "r" (any GPR including r0).

Changes:
- Changed first operand constraint from "r" to "b" to exclude r0
- Changed second operand constraint from "b" to "r" for flexibility

This ensures correct prefetch behavior and compliance with PowerPC ISA
specifications, preventing potential issues where r0 might be incorrectly
used as the base address register.

Signed-off-by: Amrita H S <amritahs@linux.vnet.ibm.com>
 2026-06-04 01:49:08 -05:00
Amrita H S 3863a7778d Power10: Replace vector pair loads with __builtin_vsx_lxvp 
Replace normal vector pair pointer dereferences with the optimized
__builtin_vsx_lxvp builtin across DGEMM, ZGEMM, and DGEMV kernels.

Also done some identation corrections in dgemm_kernel_power10.c.
This is done as part of POWER code cleanup and may not have any
performance impact.

Signed-off-by: Amrita H S <amritahs@linux.vnet.ibm.com>
 2026-06-03 02:34:53 -05:00
Chip Kerchner 6a23c36313 Unroll inner loop - 2 rows at a time. Up to 1.5X faster. 2026-06-02 16:39:16 +00:00
pengxu 6731dac68b optimize zgemm lsx kernel for 2k3000 cpu 2026-05-29 10:05:39 +08:00
Martin Kroeker 70a5a53747
Fix contiguous memory check for SGEMM and DGEMM. (#5815) 2026-05-19 22:58:22 +02:00
Martin Kroeker fda55ad259
Fix gmake build of ARM64 DYNAMIC_ARCH on hosts lacking SVE (#5816) 
* Add march=armv8.4-a+sve(+bf16) to non-PGI options for SVE-capable ARM64 targets
 2026-05-19 22:46:13 +02:00
Chip Kerchner f3f718b228 Fix contiguous memory check for SGEMM and DGEMM. 2026-05-18 18:56:29 +00:00
Gražvydas Ignotas fc9d7c7fe3 rename arm32 sgemm_kernel to indicate neon support 2026-05-05 23:09:52 +03:00
Gražvydas Ignotas 9d58b8d64e provide a NEON version of arm/sgemm 
benchmark/sgemm.goto before:
 M= 200, N= 200, K= 200 :     9262.97 MFlops   0.001727 sec
after:
 M= 200, N= 200, K= 200 :    30223.64 MFlops   0.000529 sec

Conveniently the registers are already allocated suitably for vector
operation, so the conversion from vfpv3 was rather straightforward.

Prefetching was left out because it doesn't help Cortex-A76,
only hurts it slightly.
 2026-05-05 23:09:01 +03:00
Gražvydas Ignotas cd276c2c09 only save the required registers for arm/sgemm 
According to ARM AAPCS (Procedure Call Standard) 5.1.2.1, only registers
s16-s31 must be preserved across subroutine calls; registers s0-s15
do not need to be preserved.
 2026-05-05 22:36:08 +03:00
Gražvydas Ignotas d7aeae8933 convert labels to local labels for arm/sgemm 
Non-local labels interfere with profiling. Same thing was done for arm64 in
commit a0128aa489.
 2026-05-05 22:36:08 +03:00
Martin Kroeker 33c14c66c7
spell out ifdefined 2026-04-30 17:31:01 +02:00
Martin Kroeker 703710763d
Correct stack offset of FLAG on FreeBSD 2026-04-30 17:29:31 +02:00
Martin Kroeker 54efe8ae71
Correct stack offset of FLAG on FreeBSD 2026-04-30 17:28:10 +02:00
Martin Kroeker 57765364fc
Return to using assembly SCAL kernels on FreeBSD 2026-04-30 17:25:25 +02:00
teddygood ecca5e480d Add WASM128_GENERIC STRSM and DTRSM kernels 2026-04-16 17:52:37 +09:00
teddygood 2847354ffb Allow target-specific GEMM and TRSM overrides 2026-04-16 17:52:37 +09:00
Martin Kroeker 70faa9f19d
Merge pull request #5756 from OpenMathLib/issue5267 
Work around miscompilation of the AVX512 ?GEMM kernels by Windows LLVM
 2026-04-15 07:58:21 +02:00
Martin Kroeker c59578f314
fix conditionals 2026-04-14 21:32:36 +02:00
Martin Kroeker 172f41c818
Merge pull request #5674 from ChipKerchner/fasterRVVEdges 
Improve performance on edges of GEMM for RISC-V
 2026-04-11 22:04:21 +02:00
Martin Kroeker 94e053ac10
Work around miscompilation of the AVX512 ?GEMM kernels by Windows LLVM 2026-04-11 19:27:31 +02:00
Henry Chen 6a5d2142f4 Fix dsdot precision for arm/dot.c 2026-04-09 18:11:47 +08:00
Henry Chen e875a9cdd0 Remove redundant C implemetations from MIPS directories 2026-04-08 13:59:10 +08:00
Chip Kerchner 0a4d6b2e11 Forgot files from previous check-in. 2026-04-02 20:15:32 +00:00
Chip Kerchner cc1b5794a0 Reduce number of vectors in use from 32 to 24 for last stage of main block - now full LMUL2. 2026-04-02 20:14:57 +00:00
Chip Kerchner 22b7950baa Use LMUL2 for calculations in main block - just break them apart before last stage. 2026-04-02 16:24:15 +00:00
Chip Kerchner 3b1aef12c7 Use LMUL2 loads in main block. 2026-04-02 13:20:16 +00:00
Chip Kerchner daa3215fb4 Remove shadow variable. 2026-03-31 14:41:38 +00:00
Chip Kerchner d69be17b6f Convert 2X LMUL1 instructions to 1X LMUL2. Improved FP64 GEMM edges - up to more than 3X faster. 2026-03-30 18:50:27 +00:00
Martin Kroeker 0f9f6e4be5
Merge pull request #5710 from martin-frbg/issue5708 
Work around miscompilation of the ARM64 non-SVE DDOT kernel
 2026-03-27 22:09:08 +01:00
Martin Kroeker b8dbc4a1fc
Merge pull request #5716 from yuanjia111/develop 
[ARM64] Add optimized fp16 shgemm kernels for Neoverse N2
 2026-03-27 13:36:25 +01:00
yuanjia e6eba9fa21 Add optimized FP16 shgemm for for NEOVERSEN2 target 2026-03-27 17:55:06 +08:00
Murray Steele f6d4fe703b Fix incorrect cast from BF16 to FP32 in SBGEMM 
This change fixes a regression in SBGEMM where C is assumed to be BF16,
and so unconditionally casts the output to FP32 resulting in incorrect
outputs when beta=1.
 2026-03-26 12:10:52 +00:00
Martin Kroeker e3ce4623c2
Use volatile attribute for SDOT only, to avoid creating new miscompilations 2026-03-24 23:08:02 +01:00
Chip Kerchner 8fc0004024 Fix another typo. 2026-03-24 13:04:54 +00:00
Chip Kerchner ebf4cd1c6e Fix typo. 2026-03-22 18:28:21 +00:00
Martin Kroeker 4956446ca2
Merge pull request #5692 from teddygood/wasm-sum-followup 
Enable DSUM SIMD path for WASM128_GENERIC
 2026-03-21 12:39:30 +01:00
Martin Kroeker a89142fd5d
Merge pull request #5688 from martin-frbg/divlimit_dyn 
Make PREFERRED_SIZE, GEMM_DIVIDE_LIMIT and _RATE available to DYNAMIC_ARCH builds
 2026-03-20 22:23:15 +01:00
Chip Kerchner 1bb72b223d Only initialize unused variables to prevent GCC warnings. 2026-03-20 16:00:33 +00:00
Martin Kroeker 0dd501d794
Add GEMM_DIVIDE_RATE and GEMM_PREFERRED_SIZE to parameters 2026-03-20 15:32:06 +01:00