9 Commits

Author	SHA1	Message	Date
yuanjia	826cb4588f	remove unused variable	2025-09-13 11:35:49 +08:00
yuanjia	53d7452cdf	riscv: gemv_t_vector.c optimize	2025-09-13 11:24:49 +08:00
yuanjia	c2cc7a3602	riscv64: optimize gemv_t_vector.c	2025-08-22 16:14:14 +08:00
Sergei Lewis	9edb805e64	fix builds with t-head toolchains that use old versions of the intrinsics spec	2024-01-16 14:33:08 +00:00
Sergei Lewis	2406958629	* update intrinsics to match latest spec at https://github.com/riscv-non-isa/rvv-intrinsic-doc (in particular, __riscv_ prefixes for rvv intrinsics) ... * fix multiple numerical stability and corner case issues * add a script to generate arbitrary gemm kernel shapes * add a generic zvl256b target to demonstrate large gemm kernel unrolls	2023-02-24 10:45:03 +00:00
Xianyi Zhang	c19dff0a31	Fix T-Head RVV intrinsic API changes.	2023-01-25 19:33:32 +08:00
Xianyi Zhang	968e1f51d8	Update RISC-V Intrinsic API.	2022-06-06 13:52:21 +08:00
damonyu	ceb44bef14	update the intrinsic api to the offical name.	2021-04-27 11:12:29 +08:00
damonyu	ef8e7d0279	Add the support for RISC-V Vector. ... Change-Id: Iae7800a32f5af3903c330882cdf6f292d885f266	2020-10-15 16:09:02 +08:00