9 Commits

Author	SHA1	Message	Date
Chip Kerchner	36f9cb85b1	Fix pre-RVV 1.0.	2025-09-30 22:41:31 +00:00
Chip Kerchner	2d82d144e2	Tranverse matrix data in a cache friendly manner for GEMV_N (RISCV).	2025-09-30 21:22:10 +00:00
Chip Kerchner	72f082f31d	Fix bad vector zero initializer and other compiler warnings for RISC-V.	2025-07-30 14:04:43 +00:00
lglglglgy	1ff303f36e	Optimizing the Implementation of GEMV on the RISC-V V Extension ... Specialized some scenarios, performed loop unrolling, and reduced the number of multiplications.	2025-04-08 21:18:00 +08:00
Sergei Lewis	9edb805e64	fix builds with t-head toolchains that use old versions of the intrinsics spec	2024-01-16 14:33:08 +00:00
Sergei Lewis	2406958629	* update intrinsics to match latest spec at https://github.com/riscv-non-isa/rvv-intrinsic-doc (in particular, __riscv_ prefixes for rvv intrinsics) ... * fix multiple numerical stability and corner case issues * add a script to generate arbitrary gemm kernel shapes * add a generic zvl256b target to demonstrate large gemm kernel unrolls	2023-02-24 10:45:03 +00:00
Xianyi Zhang	c19dff0a31	Fix T-Head RVV intrinsic API changes.	2023-01-25 19:33:32 +08:00
damonyu	ceb44bef14	update the intrinsic api to the offical name.	2021-04-27 11:12:29 +08:00
damonyu	ef8e7d0279	Add the support for RISC-V Vector. ... Change-Id: Iae7800a32f5af3903c330882cdf6f292d885f266	2020-10-15 16:09:02 +08:00