6 Commits

Author	SHA1	Message	Date
Martin Kroeker	f6b0d48a39	Add BUILD_BFLOAT16/HFLOAT16 for RISCV_ZVL256B target	2025-10-09 12:42:36 +02:00
Martin Kroeker	de004136cd	Update riscv64_vector.yml	2025-10-09 12:27:07 +02:00
Martin Kroeker	acff97cef1	Ensure qemu is installed for running the tests	2025-10-09 12:04:14 +02:00
Martin Kroeker	4c1a4e60a6	Update toolchain to its latest nightly build	2025-09-02 14:54:08 +02:00
Mark Ryan	3b715e6162	Add autodetection for riscv64 ... Implement DYNAMIC_ARCH support for riscv64. Three cpu types are supported, riscv64_generic, riscv64_zvl256b, riscv64_zvl128b. The two non-generic kernels require CPU support for RVV 1.0 to function correctly. Detecting that a riscv64 device supports RVV 1.0 is a little complicated as there are some boards on the market that advertise support for V via hwcap but only support RVV 0.7.1, which is not binary compatible with RVV 1.0. The approach taken is to first try hwprobe. If hwprobe is not available, we fall back to hwcap + an additional check to distinguish between RVV 1.0 and RVV 0.7.1. Tested on a VM with VLEN=256, a CanMV K230 with VLEN=128 (with only the big core enabled), a Lichee Pi with RVV 0.7.1 and a VF2 with no vector. A compiler with RVV 1.0 support must be used to build OpenBLAS for riscv64 when DYNAMIC_ARCH=1. Signed-off-by: Mark Ryan <markdryan@rivosinc.com>	2024-07-15 14:24:22 +00:00
Sergei Lewis	461ecabb22	add RISCV64_ZVL128B and RISCV64_ZVL256B targets to CI flows and to README.md	2024-02-16 16:26:29 +00:00