6 Commits

Author	SHA1	Message	Date
Zhang Xianyi	2fb02626da	Update organization info.	2014-11-25 15:28:58 +08:00
Timothy Gu	6c2ead30f0	Remove all trailing whitespace except lapack-netlib ... Signed-off-by: Timothy Gu <timothygu99@gmail.com>	2014-06-27 12:05:18 -07:00
Xianyi Zhang	77b7020d69	changed prefetch order.	2011-01-29 03:03:34 +08:00
Xianyi Zhang	e003b811ab	load x & y contiguously in axpy.	2011-01-28 11:18:50 +08:00
Xianyi Zhang	ebe2da8474	Modified aligned size. Added additional prefetch instruction because of cache line is 32 bytes in Loongson 3A.	2011-01-27 23:07:06 +08:00
Xianyi Zhang	c0b5992fab	added axpy kernel with prefetch for Loongson3A. To-Do: tuning prefetch distance & instruction order.	2011-01-26 22:34:33 +08:00