5 Commits

Author	SHA1	Message	Date
Amrita H S	831b822b94	Fix incorrect inline assembly constraints in dcbt prefetch instructions ... Corrected the register constraints for the PowerPC dcbt (Data Cache Block Touch) instruction in Power10 kernel implementations. The dcbt instruction has special behavior where if the first operand (RA) is r0, it uses the value 0 instead of the register contents. Therefore, RA must use the "b" constraint (any GPR except r0), while RB can use "r" (any GPR including r0). Changes: - Changed first operand constraint from "r" to "b" to exclude r0 - Changed second operand constraint from "b" to "r" for flexibility This ensures correct prefetch behavior and compliance with PowerPC ISA specifications, preventing potential issues where r0 might be incorrectly used as the base address register. Signed-off-by: Amrita H S <amritahs@linux.vnet.ibm.com>	2026-06-04 01:49:08 -05:00
Gordon Fossum	0b7fb5c791	CGEMM & ZGEMM using C code.	2024-10-09 09:42:23 -05:00
Chip-Kerchner	99384933ff	Revert "Merge pull request #4532 from austinpagan/cgemm_zgemm_c_code" ... This reverts commit accea15551, reversing changes made to b925353006.	2024-03-01 07:57:39 -06:00
austinpagan	87ba528d8b	Changed C files to straighten out indentation. Removed commented lines from other file.	2024-02-01 18:46:07 -06:00
austinpagan	ddac75e0ef	Adding .C versions of CGEMM and ZGEMM	2024-02-01 12:24:25 -06:00