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6 Commits

Author SHA1 Message Date
Martin Kroeker dc3aa2cbd9
Fix non-SVE ARM64 potentially using non-zeroed register in SDOT/DDOT accumulation (#5918) 
* Zero d0 register as it may not be identical with OUT, amend clobber list

* Add sdot/ddot reproducer from issue 5917 as ARM64-specific utest
 2026-07-15 17:30:11 +02:00
Martin Kroeker e3ce4623c2
Use volatile attribute for SDOT only, to avoid creating new miscompilations 2026-03-24 23:08:02 +01:00
Martin Kroeker 3f6e928d34
Declare result as volatile to keep compilers from optimizing it out 2026-03-20 11:32:23 +01:00
Arne Juul 5442aff218 Accumulate results in output register explicitly 2025-06-09 19:03:22 +00:00
Martin Kroeker 87083fdbf6
[WIP] Work around assembler limitations in current LLVM for Windows on Arm (#5076) 
* Protect align directives in assembly files that are currently problematic with LLVM on WoA

* use the armv8 zdot on WoA to work around other LLVM issues
 2025-01-18 16:45:56 +01:00
Chris Sidebottom fd4f52c797 Add SVE implementation for sdot/ddot 
This adds an SVE implementation to sdot/ddot when available, falling back to the previous Advanced SIMD kernel where there's no SVE implementation for the kernel.

All the targets were essentially treating `dot_thunderx2t99.c` as the Advanced SIMD implementation so I've renamed it to better fit with the feature detection.
 2022-12-01 12:07:50 +00:00