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U74 target: build for the full JH7110 ISA (add Zba/Zbb) 

The StarFive JH7110's U74 cores implement rv64imafdc_..._zba_zbb, so the U74
target now compiles with -march=rv64imafdc_zba_zbb. The generic RISCV64_GENERIC
target stays at bare rv64imafdc for portability across unknown RV64GC cores.

Measured on the VisionFive 2 (GCC 13.3, -mtune=sifive-u74 held constant): GCC
emits Zba shift-add instructions in the packing routines, but DGEMM is unchanged
-- the 4x4 kernel holds 1.533 GF either way and packing 1.74 vs 1.75 GB/s. The
4x4 micro-kernel is FMA-bound (fused fmadd.d with immediate-offset loads) and
packing is LPDDR4-bandwidth-bound, so integer address generation is not on the
critical path. The flag is nonetheless the correct -march for the silicon, is
free, and can only help address-gen-bound code elsewhere in the library. The
remaining GEMM headroom on the U74 is microarchitectural scheduling (a
hand-written assembly micro-kernel), not the ISA.
This commit is contained in:
hmeiland 2026-07-09 20:21:40 +02:00
parent a3620c264a
commit b8949d1663
2 changed files with 3 additions and 3 deletions
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2
Makefile.prebuild
View File

@ -76,7 +76,7 @@ TARGET_FLAGS = -march=rv64imafdc -mabi=lp64d
endif
ifeq ($(TARGET), U74)
TARGET_FLAGS = -march=rv64imafdc -mabi=lp64d
TARGET_FLAGS = -march=rv64imafdc_zba_zbb -mabi=lp64d
endif
all: getarch_2nd

4
Makefile.riscv64
View File

@ -26,6 +26,6 @@ CCOMMON_OPT += -march=rv64imafdc -mabi=lp64d
FCOMMON_OPT += -march=rv64imafdc -mabi=lp64d
endif
ifeq ($(CORE), U74)
CCOMMON_OPT += -march=rv64imafdc -mabi=lp64d -mtune=sifive-u74
FCOMMON_OPT += -march=rv64imafdc -mabi=lp64d -mtune=sifive-u74
CCOMMON_OPT += -march=rv64imafdc_zba_zbb -mabi=lp64d -mtune=sifive-u74
FCOMMON_OPT += -march=rv64imafdc_zba_zbb -mabi=lp64d -mtune=sifive-u74
endif