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Added the configures of loongson 3a. refs #1
2011-01-25 06:45:35 +08:00
/*****************************************************************************
Update organization info.
2014-11-25 15:28:58 +08:00
Copyright (c) 2011-2014, The OpenBLAS Project
Added the configures of loongson 3a. refs #1
2011-01-25 06:45:35 +08:00
All rights reserved.
Redistribution and use in source and binary forms, with or without
modification, are permitted provided that the following conditions are
met:
1. Redistributions of source code must retain the above copyright
notice, this list of conditions and the following disclaimer.
2. Redistributions in binary form must reproduce the above copyright
notice, this list of conditions and the following disclaimer in
the documentation and/or other materials provided with the
distribution.
Update organization info.
2014-11-25 15:28:58 +08:00
3. Neither the name of the OpenBLAS project nor the names of
its contributors may be used to endorse or promote products
derived from this software without specific prior written
permission.
Added the configures of loongson 3a. refs #1
2011-01-25 06:45:35 +08:00
Remove all trailing whitespace except lapack-netlib Signed-off-by: Timothy Gu <timothygu99@gmail.com>
2014-06-28 03:05:18 +08:00
THIS SOFTWARE IS PROVIDED BY THE COPYRIGHT HOLDERS AND CONTRIBUTORS "AS IS"
AND ANY EXPRESS OR IMPLIED WARRANTIES, INCLUDING, BUT NOT LIMITED TO, THE
IMPLIED WARRANTIES OF MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE
ARE DISCLAIMED. IN NO EVENT SHALL THE COPYRIGHT OWNER OR CONTRIBUTORS BE
LIABLE FOR ANY DIRECT, INDIRECT, INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL
DAMAGES (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE GOODS OR
SERVICES; LOSS OF USE, DATA, OR PROFITS; OR BUSINESS INTERRUPTION) HOWEVER
CAUSED AND ON ANY THEORY OF LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY,
OR TORT (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT OF THE
Added the configures of loongson 3a. refs #1
2011-01-25 06:45:35 +08:00
USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE POSSIBILITY OF SUCH DAMAGE.
**********************************************************************************/
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
/*********************************************************************/
/* Copyright 2009, 2010 The University of Texas at Austin. */
/* All rights reserved. */
/* */
/* Redistribution and use in source and binary forms, with or */
/* without modification, are permitted provided that the following */
/* conditions are met: */
/* */
/* 1. Redistributions of source code must retain the above */
/* copyright notice, this list of conditions and the following */
/* disclaimer. */
/* */
/* 2. Redistributions in binary form must reproduce the above */
/* copyright notice, this list of conditions and the following */
/* disclaimer in the documentation and/or other materials */
/* provided with the distribution. */
/* */
/* THIS SOFTWARE IS PROVIDED BY THE UNIVERSITY OF TEXAS AT */
/* AUSTIN ``AS IS'' AND ANY EXPRESS OR IMPLIED WARRANTIES, */
/* INCLUDING, BUT NOT LIMITED TO, THE IMPLIED WARRANTIES OF */
/* MERCHANTABILITY AND FITNESS FOR A PARTICULAR PURPOSE ARE */
/* DISCLAIMED. IN NO EVENT SHALL THE UNIVERSITY OF TEXAS AT */
/* AUSTIN OR CONTRIBUTORS BE LIABLE FOR ANY DIRECT, INDIRECT, */
/* INCIDENTAL, SPECIAL, EXEMPLARY, OR CONSEQUENTIAL DAMAGES */
/* (INCLUDING, BUT NOT LIMITED TO, PROCUREMENT OF SUBSTITUTE */
/* GOODS OR SERVICES; LOSS OF USE, DATA, OR PROFITS; OR */
/* BUSINESS INTERRUPTION) HOWEVER CAUSED AND ON ANY THEORY OF */
/* LIABILITY, WHETHER IN CONTRACT, STRICT LIABILITY, OR TORT */
/* (INCLUDING NEGLIGENCE OR OTHERWISE) ARISING IN ANY WAY OUT */
/* OF THE USE OF THIS SOFTWARE, EVEN IF ADVISED OF THE */
/* POSSIBILITY OF SUCH DAMAGE. */
/* */
/* The views and conclusions contained in the software and */
/* documentation are those of the authors and should not be */
/* interpreted as representing official policies, either expressed */
/* or implied, of The University of Texas at Austin. */
/*********************************************************************/
Added MSVC defines to cpuid.h and getarch.c.
2015-01-02 11:01:28 +08:00
#if defined(__WIN32__) || defined(__WIN64__) || defined(__CYGWIN32__) || defined(__CYGWIN64__) || defined(_WIN32) || defined(_WIN64)
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define OS_WINDOWS
#endif
Added MSVC defines to cpuid.h and getarch.c.
2015-01-02 11:01:28 +08:00
#if defined(__i386__) || defined(__x86_64__) || defined(_M_IX86) || defined(_M_X64)
#define INTEL_AMD
#endif
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#include <stdio.h>
#include <string.h>
#ifdef OS_WINDOWS
#include <windows.h>
#endif
Add NetBSD
2019-10-25 18:51:06 +08:00
#if defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#include <sys/types.h>
#include <sys/sysctl.h>
#endif
make parallel make work on illumos
2016-01-23 00:48:50 +08:00
#if defined(linux) || defined(__sun__)
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#include <sys/sysinfo.h>
Refs #248. Fixed the LSB compatiable issue for BLAS only. For example, make CC=lsbcc NO_LAPACK=1.
2013-07-09 15:38:03 +08:00
#include <unistd.h>
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#endif
Obtain actual cpu count on AIX and suppress spurious NO_AVX512 on non-x86
2020-07-07 21:46:32 +08:00
#if defined(AIX)
#include <sys/sysinfo.h>
#endif
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
Obtain actual cpu count on AIX and suppress spurious NO_AVX512 on non-x86
2020-07-07 21:46:32 +08:00
#if defined(__x86_64__) || defined(_M_X64)
Report SkylakeX as Haswell if compiler does not support AVX512 ... or make was invoked with NO_AVX512=1
2019-01-23 01:47:12 +08:00
#if (( defined(__GNUC__) && __GNUC__ > 6 && defined(__AVX2__)) || (defined(__clang__) && __clang_major__ >= 6))
#else
#define NO_AVX512
#endif
Obtain actual cpu count on AIX and suppress spurious NO_AVX512 on non-x86
2020-07-07 21:46:32 +08:00
#endif
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
/* #define FORCE_P2 */
/* #define FORCE_KATMAI */
/* #define FORCE_COPPERMINE */
/* #define FORCE_NORTHWOOD */
/* #define FORCE_PRESCOTT */
/* #define FORCE_BANIAS */
/* #define FORCE_YONAH */
/* #define FORCE_CORE2 */
/* #define FORCE_PENRYN */
/* #define FORCE_DUNNINGTON */
/* #define FORCE_NEHALEM */
getarch.c: Minor re-ordering of architecture list
2013-03-17 23:07:48 +08:00
/* #define FORCE_SANDYBRIDGE */
/* #define FORCE_ATOM */
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
/* #define FORCE_ATHLON */
/* #define FORCE_OPTERON */
/* #define FORCE_OPTERON_SSE3 */
/* #define FORCE_BARCELONA */
/* #define FORCE_SHANGHAI */
/* #define FORCE_ISTANBUL */
getarch.c: Minor re-ordering of architecture list
2013-03-17 23:07:48 +08:00
/* #define FORCE_BOBCAT */
getarch.c: Minor re-ordering of architecture list
2013-03-17 23:09:23 +08:00
/* #define FORCE_BULLDOZER */
Support AMD Piledriver by bulldozer kernels.
2013-07-06 23:06:43 +08:00
/* #define FORCE_PILEDRIVER */
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
/* #define FORCE_SSE_GENERIC */
/* #define FORCE_VIAC3 */
/* #define FORCE_NANO */
/* #define FORCE_POWER3 */
/* #define FORCE_POWER4 */
/* #define FORCE_POWER5 */
/* #define FORCE_POWER6 */
Add POWER7/POWER8 as targets
2015-08-05 22:02:39 +08:00
/* #define FORCE_POWER7 */
/* #define FORCE_POWER8 */
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
/* #define FORCE_PPCG4 */
/* #define FORCE_PPC970 */
/* #define FORCE_PPC970MP */
/* #define FORCE_PPC440 */
/* #define FORCE_PPC440FP2 */
/* #define FORCE_CELL */
/* #define FORCE_SICORTEX */
getarch.c: Minor re-ordering of architecture list
2013-03-17 23:07:48 +08:00
/* #define FORCE_LOONGSON3A */
/* #define FORCE_LOONGSON3B */
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
/* #define FORCE_I6400 */
Added MSA optimization for GEMV_N, GEMV_T, ASUM, DOT functions Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-07-15 21:08:25 +08:00
/* #define FORCE_P6600 */
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
/* #define FORCE_P5600 */
Added mips I6500 core Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2017-09-22 14:27:43 +08:00
/* #define FORCE_I6500 */
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
/* #define FORCE_ITANIUM2 */
/* #define FORCE_SPARC */
/* #define FORCE_SPARCV7 */
Add support for TARGET=ZARCH_GENERIC and TARGET=Z13
2017-09-19 18:16:42 +08:00
/* #define FORCE_ZARCH_GENERIC */
/* #define FORCE_Z13 */
getarch.c: Minor re-ordering of architecture list
2013-03-17 23:07:48 +08:00
/* #define FORCE_GENERIC */
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#ifdef FORCE_P2
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "PENTIUM2"
#define ARCHCONFIG "-DPENTIUM2 " \
"-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_CMOV -DHAVE_MMX"
#define LIBNAME "p2"
#define CORENAME "P5"
#endif
getarch.c: Minor re-ordering of architecture list
2013-03-17 23:07:48 +08:00
#ifdef FORCE_KATMAI
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "PENTIUM3"
#define ARCHCONFIG "-DPENTIUM3 " \
"-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
getarch.c: Minor re-ordering of architecture list
2013-03-17 23:07:48 +08:00
"-DL2_SIZE=524288 -DL2_LINESIZE=32 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
getarch.c: Minor re-ordering of architecture list
2013-03-17 23:07:48 +08:00
#define LIBNAME "katmai"
#define CORENAME "KATMAI"
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#endif
getarch.c: Minor re-ordering of architecture list
2013-03-17 23:07:48 +08:00
#ifdef FORCE_COPPERMINE
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "PENTIUM3"
#define ARCHCONFIG "-DPENTIUM3 " \
"-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=32 " \
getarch.c: Minor re-ordering of architecture list
2013-03-17 23:07:48 +08:00
"-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE "
getarch.c: Minor re-ordering of architecture list
2013-03-17 23:07:48 +08:00
#define LIBNAME "coppermine"
#define CORENAME "COPPERMINE"
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#endif
#ifdef FORCE_NORTHWOOD
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "PENTIUM4"
#define ARCHCONFIG "-DPENTIUM4 " \
"-DL1_DATA_SIZE=8192 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
#define LIBNAME "northwood"
#define CORENAME "NORTHWOOD"
#endif
#ifdef FORCE_PRESCOTT
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "PENTIUM4"
#define ARCHCONFIG "-DPENTIUM4 " \
"-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
#define LIBNAME "prescott"
#define CORENAME "PRESCOTT"
#endif
#ifdef FORCE_BANIAS
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "BANIAS"
#define ARCHCONFIG "-DPENTIUMM " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
#define LIBNAME "banias"
#define CORENAME "BANIAS"
#endif
#ifdef FORCE_YONAH
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "YONAH"
#define ARCHCONFIG "-DPENTIUMM " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
#define LIBNAME "yonah"
#define CORENAME "YONAH"
#endif
#ifdef FORCE_CORE2
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "CONRORE"
#define ARCHCONFIG "-DCORE2 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
#define LIBNAME "core2"
#define CORENAME "CORE2"
#endif
#ifdef FORCE_PENRYN
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "PENRYN"
#define ARCHCONFIG "-DPENRYN " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
#define LIBNAME "penryn"
#define CORENAME "PENRYN"
#endif
#ifdef FORCE_DUNNINGTON
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "DUNNINGTON"
#define ARCHCONFIG "-DDUNNINGTON " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
"-DL3_SIZE=16777216 -DL3_LINESIZE=64 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1"
#define LIBNAME "dunnington"
#define CORENAME "DUNNINGTON"
#endif
#ifdef FORCE_NEHALEM
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "NEHALEM"
#define ARCHCONFIG "-DNEHALEM " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2"
#define LIBNAME "nehalem"
#define CORENAME "NEHALEM"
#endif
Init Sandybridge codes based on Nehalem.
2012-03-30 20:01:03 +08:00
#ifdef FORCE_SANDYBRIDGE
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "SANDYBRIDGE"
#define ARCHCONFIG "-DSANDYBRIDGE " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX"
#define LIBNAME "sandybridge"
#define CORENAME "SANDYBRIDGE"
#endif
Init code base for Intel Haswell.
2013-08-13 00:54:59 +08:00
#ifdef FORCE_HASWELL
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "HASWELL"
#define ARCHCONFIG "-DHASWELL " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
"-DFMA3"
#define LIBNAME "haswell"
#define CORENAME "HASWELL"
#endif
Initial support for SkylakeX / AVX512 This patch adds the basic infrastructure for adding the SkylakeX (Intel Skylake server) target. The SkylakeX target will use the AVX512 (AVX512VL level) instruction set, which brings 2 basic things: 1) 512 bit wide SIMD (2x width of AVX2) 2) 32 SIMD registers (2x the number on AVX2) This initial patch only contains a trivial transofrmation of the Haswell SGEMM kernel to AVX512VL; more will follow later but this patch aims to get the infrastructure in place for this "later". Full performance tuning has not been done yet; with more registers and wider SIMD it's in theory possible to retune the kernels but even without that there's an interesting enough performance increase (30-40% range) with just this change.
2018-06-03 15:24:29 +08:00
#ifdef FORCE_SKYLAKEX
Report SkylakeX as Haswell if compiler does not support AVX512 ... or make was invoked with NO_AVX512=1
2019-01-23 01:47:12 +08:00
#ifdef NO_AVX512
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "HASWELL"
#define ARCHCONFIG "-DHASWELL " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
"-DFMA3"
#define LIBNAME "haswell"
#define CORENAME "HASWELL"
#else
Initial support for SkylakeX / AVX512 This patch adds the basic infrastructure for adding the SkylakeX (Intel Skylake server) target. The SkylakeX target will use the AVX512 (AVX512VL level) instruction set, which brings 2 basic things: 1) 512 bit wide SIMD (2x width of AVX2) 2) 32 SIMD registers (2x the number on AVX2) This initial patch only contains a trivial transofrmation of the Haswell SGEMM kernel to AVX512VL; more will follow later but this patch aims to get the infrastructure in place for this "later". Full performance tuning has not been done yet; with more registers and wider SIMD it's in theory possible to retune the kernels but even without that there's an interesting enough performance increase (30-40% range) with just this change.
2018-06-03 15:24:29 +08:00
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "SKYLAKEX"
#define ARCHCONFIG "-DSKYLAKEX " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
"-DFMA3 -DHAVE_AVX512VL -march=skylake-avx512"
#define LIBNAME "skylakex"
#define CORENAME "SKYLAKEX"
#endif
Report SkylakeX as Haswell if compiler does not support AVX512 ... or make was invoked with NO_AVX512=1
2019-01-23 01:47:12 +08:00
#endif
Initial support for SkylakeX / AVX512 This patch adds the basic infrastructure for adding the SkylakeX (Intel Skylake server) target. The SkylakeX target will use the AVX512 (AVX512VL level) instruction set, which brings 2 basic things: 1) 512 bit wide SIMD (2x width of AVX2) 2) 32 SIMD registers (2x the number on AVX2) This initial patch only contains a trivial transofrmation of the Haswell SGEMM kernel to AVX512VL; more will follow later but this patch aims to get the infrastructure in place for this "later". Full performance tuning has not been done yet; with more registers and wider SIMD it's in theory possible to retune the kernels but even without that there's an interesting enough performance increase (30-40% range) with just this change.
2018-06-03 15:24:29 +08:00
Enable COOPERLAKE build target Enable new build target platform -- COOPERLAKE. This target platform supports all the SKYLAKEX supported ISAs + avx512bf16. So all the SKYLAKEX specific kernels/drivers and related code are now extended to be also active on COOPERLAKE. Besides, new BF16 related kernels are active under this target.
2020-08-13 06:17:34 +08:00
#ifdef FORCE_COOPERLAKE
#ifdef NO_AVX512
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "HASWELL"
#define ARCHCONFIG "-DHASWELL " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
"-DFMA3"
#define LIBNAME "haswell"
#define CORENAME "HASWELL"
#else
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "COOPERLAKE"
#define ARCHCONFIG "-DCOOPERLAKE " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 -DHAVE_AVX " \
"-DFMA3 -DHAVE_AVX512VL -DHAVE_AVX512BF16 -march=cooperlake"
#define LIBNAME "cooperlake"
#define CORENAME "COOPERLAKE"
#endif
#endif
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#ifdef FORCE_ATOM
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "ATOM"
#define ARCHCONFIG "-DATOM " \
"-DL1_DATA_SIZE=24576 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
#define LIBNAME "atom"
#define CORENAME "ATOM"
#endif
#ifdef FORCE_ATHLON
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "ATHLON"
#define ARCHCONFIG "-DATHLON " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE "
#define LIBNAME "athlon"
#define CORENAME "ATHLON"
#endif
#ifdef FORCE_OPTERON
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "OPTERON"
#define ARCHCONFIG "-DOPTERON " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 "
#define LIBNAME "opteron"
#define CORENAME "OPTERON"
#endif
#ifdef FORCE_OPTERON_SSE3
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "OPTERON"
#define ARCHCONFIG "-DOPTERON " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DHAVE_3DNOW " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_3DNOWEX -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3"
#define LIBNAME "opteron"
#define CORENAME "OPTERON"
#endif
Enable bulldozer kernels.
2013-08-05 16:07:54 +08:00
#if defined(FORCE_BARCELONA) || defined(FORCE_SHANGHAI) || defined(FORCE_ISTANBUL)
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "BARCELONA"
#define ARCHCONFIG "-DBARCELONA " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL3_SIZE=2097152 " \
Refs #118. Detect AMD Bulldozer as Barcelona.
2012-06-25 17:28:49 +08:00
"-DDTB_DEFAULT_ENTRIES=48 -DDTB_SIZE=4096 " \
"-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU"
#define LIBNAME "barcelona"
#define CORENAME "BARCELONA"
#endif
Remove all trailing whitespace except lapack-netlib Signed-off-by: Timothy Gu <timothygu99@gmail.com>
2014-06-28 03:05:18 +08:00
#if defined(FORCE_BOBCAT)
Refs #113. Support AMD Bobcate using Barcelona kernel codes. Replace 3DNow! with MMX.
2012-05-31 18:17:45 +08:00
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
Refs #113. Fixed the typo BOBCATE -> BOBCAT
2012-05-31 22:40:15 +08:00
#define SUBARCHITECTURE "BOBCAT"
#define ARCHCONFIG "-DBOBCAT " \
Refs #113. Support AMD Bobcate using Barcelona kernel codes. Replace 3DNow! with MMX.
2012-05-31 18:17:45 +08:00
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
"-DDTB_DEFAULT_ENTRIES=40 -DDTB_SIZE=4096 " \
"-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3 " \
"-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_CFLUSH -DHAVE_CMOV"
Refs #113. Fixed the typo BOBCATE -> BOBCAT
2012-05-31 22:40:15 +08:00
#define LIBNAME "bobcat"
#define CORENAME "BOBCAT"
Refs #113. Support AMD Bobcate using Barcelona kernel codes. Replace 3DNow! with MMX.
2012-05-31 18:17:45 +08:00
#endif
Enable bulldozer kernels.
2013-08-05 16:07:54 +08:00
#if defined (FORCE_BULLDOZER)
Init AMD Bulldozer codebase.
2012-12-06 20:29:54 +08:00
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "BULLDOZER"
Added BULLDOZER target. So far it uses barcelona kernels.
2012-12-07 00:53:31 +08:00
#define ARCHCONFIG "-DBULLDOZER " \
Init AMD Bulldozer codebase.
2012-12-06 20:29:54 +08:00
"-DL1_DATA_SIZE=49152 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=1024000 -DL2_LINESIZE=64 -DL3_SIZE=16777216 " \
"-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 " \
"-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 " \
Added BULLDOZER target. So far it uses barcelona kernels.
2012-12-07 00:53:31 +08:00
"-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU " \
remove default support for FMA4 on zen architect
2020-09-27 09:35:50 +08:00
"-DHAVE_AVX"
Init AMD Bulldozer codebase.
2012-12-06 20:29:54 +08:00
#define LIBNAME "bulldozer"
#define CORENAME "BULLDOZER"
#endif
Enable bulldozer kernels.
2013-08-05 16:07:54 +08:00
#if defined (FORCE_PILEDRIVER)
Support AMD Piledriver by bulldozer kernels.
2013-07-06 23:06:43 +08:00
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "PILEDRIVER"
#define ARCHCONFIG "-DPILEDRIVER " \
"-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL3_SIZE=12582912 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
Fixed the typo in getarch.c
2013-07-09 16:26:59 +08:00
"-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
"-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
remove default support for FMA4 on zen architect
2020-09-27 09:35:50 +08:00
"-DHAVE_AVX -DHAVE_FMA3"
Support AMD Piledriver by bulldozer kernels.
2013-07-06 23:06:43 +08:00
#define LIBNAME "piledriver"
#define CORENAME "PILEDRIVER"
#endif
added target processor STEAMROLLER
2014-12-28 20:16:46 +08:00
#if defined (FORCE_STEAMROLLER)
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "STEAMROLLER"
#define ARCHCONFIG "-DSTEAMROLLER " \
"-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL3_SIZE=12582912 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
"-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
"-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
remove default support for FMA4 on zen architect
2020-09-27 09:35:50 +08:00
"-DHAVE_AVX -DHAVE_FMA3"
added target processor STEAMROLLER
2014-12-28 20:16:46 +08:00
#define LIBNAME "steamroller"
#define CORENAME "STEAMROLLER"
#endif
Add AMD Excavator target.
2015-05-14 05:16:30 +08:00
#if defined (FORCE_EXCAVATOR)
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "EXCAVATOR"
#define ARCHCONFIG "-DEXCAVATOR " \
"-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL3_SIZE=12582912 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
"-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
"-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
remove default support for FMA4 on zen architect
2020-09-27 09:35:50 +08:00
"-DHAVE_AVX -DHAVE_FMA3"
Add AMD Excavator target.
2015-05-14 05:16:30 +08:00
#define LIBNAME "excavator"
#define CORENAME "EXCAVATOR"
#endif
Add ZEN support (tested for auto-detected static backend)
2017-03-19 22:32:50 +08:00
#if defined (FORCE_ZEN)
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "ZEN"
#define ARCHCONFIG "-DZEN " \
"-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL2_CODE_ASSOCIATIVE=8 " \
"-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
"-DL3_SIZE=16777216 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=8 " \
"-DITB_DEFAULT_ENTRIES=64 -DITB_SIZE=4096 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
"-DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSE4_1 -DHAVE_SSE4_2 " \
"-DHAVE_SSE4A -DHAVE_MISALIGNSSE -DHAVE_128BITFPU -DHAVE_FASTMOVU -DHAVE_CFLUSH " \
"-DHAVE_AVX -DHAVE_FMA3 -DFMA3"
Fix FORCE_ZEN option in getarch.c
2017-04-19 20:20:42 +08:00
#define LIBNAME "zen"
#define CORENAME "ZEN"
Add ZEN support (tested for auto-detected static backend)
2017-03-19 22:32:50 +08:00
#endif
added target processor STEAMROLLER
2014-12-28 20:16:46 +08:00
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#ifdef FORCE_SSE_GENERIC
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "GENERIC"
#define ARCHCONFIG "-DGENERIC " \
"-DL1_DATA_SIZE=16384 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=524288 -DL2_LINESIZE=64 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2"
#define LIBNAME "generic"
#define CORENAME "GENERIC"
#endif
#ifdef FORCE_VIAC3
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "VIAC3"
#define ARCHCONFIG "-DVIAC3 " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=65536 -DL2_LINESIZE=32 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_MMX -DHAVE_SSE "
#define LIBNAME "viac3"
#define CORENAME "VIAC3"
#endif
#ifdef FORCE_NANO
#define FORCE
#define FORCE_INTEL
#define ARCHITECTURE "X86"
#define SUBARCHITECTURE "NANO"
#define ARCHCONFIG "-DNANO " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=64 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 " \
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
"-DHAVE_CMOV -DHAVE_MMX -DHAVE_SSE -DHAVE_SSE2 -DHAVE_SSE3 -DHAVE_SSSE3"
#define LIBNAME "nano"
#define CORENAME "NANO"
#endif
#ifdef FORCE_POWER3
#define FORCE
#define ARCHITECTURE "POWER"
#define SUBARCHITECTURE "POWER3"
#define SUBDIRNAME "power"
#define ARCHCONFIG "-DPOWER3 " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
"-DL2_SIZE=2097152 -DL2_LINESIZE=128 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=256 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define LIBNAME "power3"
#define CORENAME "POWER3"
#endif
#ifdef FORCE_POWER4
#define FORCE
#define ARCHITECTURE "POWER"
#define SUBARCHITECTURE "POWER4"
#define SUBDIRNAME "power"
#define ARCHCONFIG "-DPOWER4 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
"-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define LIBNAME "power4"
#define CORENAME "POWER4"
#endif
#ifdef FORCE_POWER5
#define FORCE
#define ARCHITECTURE "POWER"
#define SUBARCHITECTURE "POWER5"
#define SUBDIRNAME "power"
#define ARCHCONFIG "-DPOWER5 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
"-DL2_SIZE=1509949 -DL2_LINESIZE=128 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=6 "
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define LIBNAME "power5"
#define CORENAME "POWER5"
#endif
added dgemm-, dtrmm-, zgemm- and ztrmm-kernel for power8
2016-03-01 14:33:56 +08:00
#if defined(FORCE_POWER6) || defined(FORCE_POWER7)
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define FORCE
#define ARCHITECTURE "POWER"
#define SUBARCHITECTURE "POWER6"
#define SUBDIRNAME "power"
#define ARCHCONFIG "-DPOWER6 " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
"-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define LIBNAME "power6"
#define CORENAME "POWER6"
#endif
added dgemm-, dtrmm-, zgemm- and ztrmm-kernel for power8
2016-03-01 14:33:56 +08:00
#if defined(FORCE_POWER8)
Init POWER8 kernels by POWER6.
2015-11-03 12:25:05 +08:00
#define FORCE
#define ARCHITECTURE "POWER"
#define SUBARCHITECTURE "POWER8"
#define SUBDIRNAME "power"
#define ARCHCONFIG "-DPOWER8 " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=128 " \
"-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
"-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
#define LIBNAME "power8"
#define CORENAME "POWER8"
#endif
power9 makefile. dgemm based on power8 kernel with following changes : 32x unrolled 16x4 kernel and 8x4 kernel using (lxv stxv butterfly rank1 update). improvement from 17 to 22-23gflops. dtrmm cases were added into dgemm itself
2019-03-14 18:42:04 +08:00
#if defined(FORCE_POWER9)
#define FORCE
#define ARCHITECTURE "POWER"
#define SUBARCHITECTURE "POWER9"
#define SUBDIRNAME "power"
#define ARCHCONFIG "-DPOWER9 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
"-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
"-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
#define LIBNAME "power9"
#define CORENAME "POWER9"
#endif
added dgemm-, dtrmm-, zgemm- and ztrmm-kernel for power8
2016-03-01 14:33:56 +08:00
powerpc: Add support for future processor This is the initial patch to support build infrastructure for POWER10 architecture.
2020-06-12 04:47:20 +08:00
#if defined(FORCE_POWER10)
#define FORCE
#define ARCHITECTURE "POWER"
#define SUBARCHITECTURE "POWER10"
#define SUBDIRNAME "power"
#define ARCHCONFIG "-DPOWER10 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
"-DL2_SIZE=4194304 -DL2_LINESIZE=128 " \
"-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
#define LIBNAME "power10"
#define CORENAME "POWER10"
#endif
Added RISCV build
2018-04-17 03:34:43 +08:00
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#ifdef FORCE_PPCG4
#define FORCE
#define ARCHITECTURE "POWER"
#define SUBARCHITECTURE "PPCG4"
#define SUBDIRNAME "power"
#define ARCHCONFIG "-DPPCG4 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define LIBNAME "ppcg4"
#define CORENAME "PPCG4"
#endif
#ifdef FORCE_PPC970
#define FORCE
#define ARCHITECTURE "POWER"
#define SUBARCHITECTURE "PPC970"
#define SUBDIRNAME "power"
#define ARCHCONFIG "-DPPC970 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
"-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define LIBNAME "ppc970"
#define CORENAME "PPC970"
#endif
#ifdef FORCE_PPC970MP
#define FORCE
#define ARCHITECTURE "POWER"
#define SUBARCHITECTURE "PPC970"
#define SUBDIRNAME "power"
#define ARCHCONFIG "-DPPC970 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
"-DL2_SIZE=1024976 -DL2_LINESIZE=128 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define LIBNAME "ppc970mp"
#define CORENAME "PPC970"
#endif
#ifdef FORCE_PPC440
#define FORCE
#define ARCHITECTURE "POWER"
#define SUBARCHITECTURE "PPC440"
#define SUBDIRNAME "power"
#define ARCHCONFIG "-DPPC440 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define LIBNAME "ppc440"
#define CORENAME "PPC440"
#endif
#ifdef FORCE_PPC440FP2
#define FORCE
#define ARCHITECTURE "POWER"
#define SUBARCHITECTURE "PPC440FP2"
#define SUBDIRNAME "power"
#define ARCHCONFIG "-DPPC440FP2 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=16384 -DL2_LINESIZE=128 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=16 "
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define LIBNAME "ppc440FP2"
#define CORENAME "PPC440FP2"
#endif
#ifdef FORCE_CELL
#define FORCE
#define ARCHITECTURE "POWER"
#define SUBARCHITECTURE "CELL"
#define SUBDIRNAME "power"
#define ARCHCONFIG "-DCELL " \
"-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
"-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define LIBNAME "cell"
#define CORENAME "CELL"
#endif
#ifdef FORCE_SICORTEX
#define FORCE
#define ARCHITECTURE "MIPS"
#define SUBARCHITECTURE "SICORTEX"
#define SUBDIRNAME "mips"
#define ARCHCONFIG "-DSICORTEX " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=32 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define LIBNAME "mips"
#define CORENAME "sicortex"
#endif
Added the configures of loongson 3a. refs #1
2011-01-25 06:45:35 +08:00
#ifdef FORCE_LOONGSON3A
#define FORCE
#define ARCHITECTURE "MIPS"
#define SUBARCHITECTURE "LOONGSON3A"
#define SUBDIRNAME "mips64"
#define ARCHCONFIG "-DLOONGSON3A " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
Added the configures of loongson 3a. refs #1
2011-01-25 06:45:35 +08:00
#define LIBNAME "loongson3a"
#define CORENAME "LOONGSON3A"
fixed a typo.
2011-01-25 15:55:56 +08:00
#else
Added the configures of loongson 3a. refs #1
2011-01-25 06:45:35 +08:00
#endif
Support detecting ICT Loongson-3B CPU.
2011-11-10 03:28:22 +08:00
#ifdef FORCE_LOONGSON3B
#define FORCE
#define ARCHITECTURE "MIPS"
#define SUBARCHITECTURE "LOONGSON3B"
#define SUBDIRNAME "mips64"
#define ARCHCONFIG "-DLOONGSON3B " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
#define LIBNAME "loongson3b"
#define CORENAME "LOONGSON3B"
#else
#endif
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
#ifdef FORCE_I6400
#define FORCE
#define ARCHITECTURE "MIPS"
#define SUBARCHITECTURE "I6400"
#define SUBDIRNAME "mips64"
#define ARCHCONFIG "-DI6400 " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
#define LIBNAME "i6400"
#define CORENAME "I6400"
#else
#endif
Added MSA optimization for GEMV_N, GEMV_T, ASUM, DOT functions Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-07-15 21:08:25 +08:00
#ifdef FORCE_P6600
#define FORCE
#define ARCHITECTURE "MIPS"
#define SUBARCHITECTURE "P6600"
#define SUBDIRNAME "mips64"
#define ARCHCONFIG "-DP6600 " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
#define LIBNAME "p6600"
#define CORENAME "P6600"
#else
#endif
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
#ifdef FORCE_P5600
#define FORCE
#define ARCHITECTURE "MIPS"
#define SUBARCHITECTURE "P5600"
#define SUBDIRNAME "mips"
#define ARCHCONFIG "-DP5600 " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
#define LIBNAME "p5600"
#define CORENAME "P5600"
#else
#endif
Rename the FORCE entries for 24K and 1004K to include the MIPS prefix
2020-04-19 19:22:19 +08:00
#ifdef FORCE_MIPS1004K
Handle MIPS24K like P5600 and allow enforcing TARGET=1004K as well (omission from earlier 1004K merge and later introduction of TARGET check)
2020-04-19 03:09:32 +08:00
#define FORCE
#define ARCHITECTURE "MIPS"
Update getarch.c
2020-04-19 19:52:58 +08:00
#define SUBARCHITECTURE "MIPS1004K"
Handle MIPS24K like P5600 and allow enforcing TARGET=1004K as well (omission from earlier 1004K merge and later introduction of TARGET check)
2020-04-19 03:09:32 +08:00
#define SUBDIRNAME "mips"
Update getarch.c
2020-04-19 20:55:31 +08:00
#define ARCHCONFIG "-DMIPS1004K " \
Handle MIPS24K like P5600 and allow enforcing TARGET=1004K as well (omission from earlier 1004K merge and later introduction of TARGET check)
2020-04-19 03:09:32 +08:00
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=262144 -DL2_LINESIZE=32 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
Update getarch.c
2020-04-19 19:52:58 +08:00
#define LIBNAME "mips1004K"
#define CORENAME "MIPS1004K"
Handle MIPS24K like P5600 and allow enforcing TARGET=1004K as well (omission from earlier 1004K merge and later introduction of TARGET check)
2020-04-19 03:09:32 +08:00
#else
#endif
Rename the FORCE entries for 24K and 1004K to include the MIPS prefix
2020-04-19 19:22:19 +08:00
#ifdef FORCE_MIPS24K
Handle MIPS24K like P5600 and allow enforcing TARGET=1004K as well (omission from earlier 1004K merge and later introduction of TARGET check)
2020-04-19 03:09:32 +08:00
#define FORCE
#define ARCHITECTURE "MIPS"
Update getarch.c
2020-04-19 19:52:58 +08:00
#define SUBARCHITECTURE "MIPS24K"
Handle MIPS24K like P5600 and allow enforcing TARGET=1004K as well (omission from earlier 1004K merge and later introduction of TARGET check)
2020-04-19 03:09:32 +08:00
#define SUBDIRNAME "mips"
Update getarch.c
2020-04-19 20:55:31 +08:00
#define ARCHCONFIG "-DMIPS24K " \
Handle MIPS24K like P5600 and allow enforcing TARGET=1004K as well (omission from earlier 1004K merge and later introduction of TARGET check)
2020-04-19 03:09:32 +08:00
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=32768 -DL2_LINESIZE=32 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
Update getarch.c
2020-04-19 19:52:58 +08:00
#define LIBNAME "mips24K"
#define CORENAME "MIPS24K"
Handle MIPS24K like P5600 and allow enforcing TARGET=1004K as well (omission from earlier 1004K merge and later introduction of TARGET check)
2020-04-19 03:09:32 +08:00
#else
#endif
Added mips I6500 core Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2017-09-22 14:27:43 +08:00
#ifdef FORCE_I6500
#define FORCE
#define ARCHITECTURE "MIPS"
#define SUBARCHITECTURE "I6500"
#define SUBDIRNAME "mips64"
#define ARCHCONFIG "-DI6500 " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
#define LIBNAME "i6500"
#define CORENAME "I6500"
#else
#endif
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#ifdef FORCE_ITANIUM2
#define FORCE
#define ARCHITECTURE "IA64"
#define SUBARCHITECTURE "ITANIUM2"
#define SUBDIRNAME "ia64"
#define ARCHCONFIG "-DITANIUM2 " \
"-DL1_DATA_SIZE=262144 -DL1_DATA_LINESIZE=128 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DL2_SIZE=1572864 -DL2_LINESIZE=128 -DDTB_SIZE=16384 -DDTB_DEFAULT_ENTRIES=128 "
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define LIBNAME "itanium2"
#define CORENAME "itanium2"
#endif
#ifdef FORCE_SPARC
#define FORCE
#define ARCHITECTURE "SPARC"
#define SUBARCHITECTURE "SPARC"
#define SUBDIRNAME "sparc"
#define ARCHCONFIG "-DSPARC -DV9 " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define LIBNAME "sparc"
#define CORENAME "sparc"
#endif
#ifdef FORCE_SPARCV7
#define FORCE
#define ARCHITECTURE "SPARC"
#define SUBARCHITECTURE "SPARC"
#define SUBDIRNAME "sparc"
#define ARCHCONFIG "-DSPARC -DV7 " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DL2_SIZE=1572864 -DL2_LINESIZE=64 -DDTB_SIZE=8192 -DDTB_DEFAULT_ENTRIES=64 "
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define LIBNAME "sparcv7"
#define CORENAME "sparcv7"
#endif
#ifdef FORCE_GENERIC
#define FORCE
#define ARCHITECTURE "GENERIC"
#define SUBARCHITECTURE "GENERIC"
#define SUBDIRNAME "generic"
#define ARCHCONFIG "-DGENERIC " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
"-DL2_SIZE=512488 -DL2_LINESIZE=128 " \
refs #55. Added DTB_ENTRIES into dynamic arch setting parameters. Now, it can read DTB_ENTRIES on runtime.
2011-09-05 17:37:07 +08:00
"-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=8 "
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#define LIBNAME "generic"
#define CORENAME "generic"
#endif
modified getarch.c
2013-12-02 00:31:22 +08:00
#ifdef FORCE_ARMV7
#define FORCE
#define ARCHITECTURE "ARM"
#define SUBARCHITECTURE "ARMV7"
#define SUBDIRNAME "arm"
#define ARCHCONFIG "-DARMV7 " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
"-DHAVE_VFPV3 -DHAVE_VFP"
#define LIBNAME "armv7"
#define CORENAME "ARMV7"
#else
#endif
Add cortex-a9 and cortex-a15 targets.
2015-01-12 16:55:29 +08:00
#ifdef FORCE_CORTEXA9
#define FORCE
#define ARCHITECTURE "ARM"
#define SUBARCHITECTURE "CORTEXA9"
#define SUBDIRNAME "arm"
Fixed make TARGET=CORTEXA9 and CORTEXA15 bug.
2015-09-26 22:42:44 +08:00
#define ARCHCONFIG "-DCORTEXA9 -DARMV7 " \
Add cortex-a9 and cortex-a15 targets.
2015-01-12 16:55:29 +08:00
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
"-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
"-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
#define LIBNAME "cortexa9"
#define CORENAME "CORTEXA9"
#else
#endif
Change default RISC-V 64-bit corename to RISCV64_GENERIC e.g. make CC=riscv64-unknown-linux-gnu-gcc FC=riscv64-unknown-linux-gnu-gfortran TARGET=RISCV64_GENERIC HOSTCC=gcc
2020-02-27 14:46:15 +08:00
#ifdef FORCE_RISCV64_GENERIC
Added RISCV build
2018-04-17 03:34:43 +08:00
#define FORCE
#define ARCHITECTURE "RISCV64"
Change default RISC-V 64-bit corename to RISCV64_GENERIC e.g. make CC=riscv64-unknown-linux-gnu-gcc FC=riscv64-unknown-linux-gnu-gfortran TARGET=RISCV64_GENERIC HOSTCC=gcc
2020-02-27 14:46:15 +08:00
#define SUBARCHITECTURE "RISCV64_GENERIC"
Added RISCV build
2018-04-17 03:34:43 +08:00
#define SUBDIRNAME "riscv64"
Change default RISC-V 64-bit corename to RISCV64_GENERIC e.g. make CC=riscv64-unknown-linux-gnu-gcc FC=riscv64-unknown-linux-gnu-gfortran TARGET=RISCV64_GENERIC HOSTCC=gcc
2020-02-27 14:46:15 +08:00
#define ARCHCONFIG "-DRISCV64_GENERIC " \
Added RISCV build
2018-04-17 03:34:43 +08:00
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
"-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
Change default RISC-V 64-bit corename to RISCV64_GENERIC e.g. make CC=riscv64-unknown-linux-gnu-gcc FC=riscv64-unknown-linux-gnu-gfortran TARGET=RISCV64_GENERIC HOSTCC=gcc
2020-02-27 14:46:15 +08:00
#define LIBNAME "riscv64_generic"
#define CORENAME "RISCV64_GENERIC"
Added RISCV build
2018-04-17 03:34:43 +08:00
#else
#endif
Add cortex-a9 and cortex-a15 targets.
2015-01-12 16:55:29 +08:00
#ifdef FORCE_CORTEXA15
#define FORCE
#define ARCHITECTURE "ARM"
#define SUBARCHITECTURE "CORTEXA15"
#define SUBDIRNAME "arm"
Fixed make TARGET=CORTEXA9 and CORTEXA15 bug.
2015-09-26 22:42:44 +08:00
#define ARCHCONFIG "-DCORTEXA15 -DARMV7 " \
Add cortex-a9 and cortex-a15 targets.
2015-01-12 16:55:29 +08:00
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=32 " \
"-DDTB_DEFAULT_ENTRIES=128 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
"-DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON"
Add ARM targets.
2015-03-25 01:17:04 +08:00
#define LIBNAME "cortexa15"
#define CORENAME "CORTEXA15"
Add cortex-a9 and cortex-a15 targets.
2015-01-12 16:55:29 +08:00
#else
#endif
modified getarch.c
2013-12-02 00:31:22 +08:00
#ifdef FORCE_ARMV6
#define FORCE
#define ARCHITECTURE "ARM"
#define SUBARCHITECTURE "ARMV6"
#define SUBDIRNAME "arm"
#define ARCHCONFIG "-DARMV6 " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 " \
"-DHAVE_VFP"
#define LIBNAME "armv6"
#define CORENAME "ARMV6"
#else
#endif
added ARMV5 as reference platform
2014-05-13 23:25:19 +08:00
#ifdef FORCE_ARMV5
#define FORCE
#define ARCHITECTURE "ARM"
#define SUBARCHITECTURE "ARMV5"
#define SUBDIRNAME "arm"
#define ARCHCONFIG "-DARMV5 " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=32 " \
"-DL2_SIZE=512488 -DL2_LINESIZE=32 " \
use real armv5 support there is no more requirement for ARMv6 instructions, and VFP on ARMv5 is uncommon
2015-08-17 00:13:30 +08:00
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=4 "
added ARMV5 as reference platform
2014-05-13 23:25:19 +08:00
#define LIBNAME "armv5"
#define CORENAME "ARMV5"
#else
#endif
modified getarch.c
2013-12-02 00:31:22 +08:00
#ifdef FORCE_ARMV8
#define FORCE
#define ARCHITECTURE "ARM64"
#define SUBARCHITECTURE "ARMV8"
#define SUBDIRNAME "arm64"
#define ARCHCONFIG "-DARMV8 " \
# The first commit's message is: Optimizations for APM's xgene-1 (aarch64). 1) general system updates to support armv8 better. Make all did not work, one needed to supply TARGET=ARMV8. 2) sgem 4x4 kernel in assembler using SIMD, and configuration changes to use it. 3) strmm 4x4 kernel in C. Since the sgem kernel does 4x4, the trmm kernel must also do 4xN. Added Dave Nuechterlein to the contributors list.
2014-10-09 21:52:10 +08:00
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 " \
"-DL2_SIZE=262144 -DL2_LINESIZE=64 " \
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
2018-11-16 23:45:12 +08:00
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 -DL2_ASSOCIATIVE=32 " \
"-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
modified getarch.c
2013-12-02 00:31:22 +08:00
#define LIBNAME "armv8"
Adding arm64 target CORTEXA57 Co-Authored-By: Ralph Campbell <ralph.campbell@broadcom.com>
2015-09-04 15:56:52 +08:00
#define CORENAME "ARMV8"
modified getarch.c
2013-12-02 00:31:22 +08:00
#endif
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
2018-11-16 23:45:12 +08:00
#ifdef FORCE_CORTEXA53
#define FORCE
#define ARCHITECTURE "ARM64"
#define SUBARCHITECTURE "CORTEXA53"
#define SUBDIRNAME "arm64"
#define ARCHCONFIG "-DCORTEXA53 " \
"-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
"-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
"-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
#define LIBNAME "cortexa53"
#define CORENAME "CORTEXA53"
#else
#endif
Adding arm64 target CORTEXA57 Co-Authored-By: Ralph Campbell <ralph.campbell@broadcom.com>
2015-09-04 15:56:52 +08:00
#ifdef FORCE_CORTEXA57
#define FORCE
#define ARCHITECTURE "ARM64"
ARM64: Add Cavium THUNDERX Target
2017-01-10 14:27:36 +08:00
#define SUBARCHITECTURE "CORTEXA57"
Adding arm64 target CORTEXA57 Co-Authored-By: Ralph Campbell <ralph.campbell@broadcom.com>
2015-09-04 15:56:52 +08:00
#define SUBDIRNAME "arm64"
#define ARCHCONFIG "-DCORTEXA57 " \
"-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
"-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
2018-11-16 23:45:12 +08:00
"-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
Adding arm64 target CORTEXA57 Co-Authored-By: Ralph Campbell <ralph.campbell@broadcom.com>
2015-09-04 15:56:52 +08:00
#define LIBNAME "cortexa57"
#define CORENAME "CORTEXA57"
#else
#endif
modified getarch.c
2013-12-02 00:31:22 +08:00
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
2018-11-16 23:45:12 +08:00
#ifdef FORCE_CORTEXA72
ARM64: Add the VULCAN Target
2016-10-04 16:50:20 +08:00
#define FORCE
#define ARCHITECTURE "ARM64"
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
2018-11-16 23:45:12 +08:00
#define SUBARCHITECTURE "CORTEXA72"
ARM64: Add the VULCAN Target
2016-10-04 16:50:20 +08:00
#define SUBDIRNAME "arm64"
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
2018-11-16 23:45:12 +08:00
#define ARCHCONFIG "-DCORTEXA72 " \
"-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
"-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
"-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
#define LIBNAME "cortexa72"
#define CORENAME "CORTEXA72"
#else
#endif
#ifdef FORCE_CORTEXA73
#define FORCE
#define ARCHITECTURE "ARM64"
#define SUBARCHITECTURE "CORTEXA73"
#define SUBDIRNAME "arm64"
#define ARCHCONFIG "-DCORTEXA73 " \
"-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
"-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
"-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
#define LIBNAME "cortexa73"
#define CORENAME "CORTEXA73"
#else
#endif
Add Neoverse-N1 core The implementation is a hybird of the ARMV8 one with some of the improved TX2 rountines along with specifying -march=v8.2-a
2020-02-22 06:46:58 +08:00
#ifdef FORCE_NEOVERSEN1
#define FORCE
#define ARCHITECTURE "ARM64"
#define SUBARCHITECTURE "NEOVERSEN1"
#define SUBDIRNAME "arm64"
#define ARCHCONFIG "-DNEOVERSEN1 " \
"-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
"-DL2_SIZE=1048576 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
Fix ARCHCONFIG for Neoverse-N1 ../config_kernel.h:24:9: warning: missing whitespace after the macro name 24 | #define ARMV8-march armv8.2-a | ^~~~~
2020-03-22 00:33:33 +08:00
"-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8 " \
Add Neoverse-N1 core The implementation is a hybird of the ARMV8 one with some of the improved TX2 rountines along with specifying -march=v8.2-a
2020-02-22 06:46:58 +08:00
"-march=armv8.2-a -mtune=cortex-a72"
#define LIBNAME "neoversen1"
#define CORENAME "NEOVERSEN1"
#else
#endif
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
2018-11-16 23:45:12 +08:00
#ifdef FORCE_FALKOR
#define FORCE
#define ARCHITECTURE "ARM64"
#define SUBARCHITECTURE "FALKOR"
#define SUBDIRNAME "arm64"
#define ARCHCONFIG "-DFALKOR " \
"-DL1_CODE_SIZE=49152 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=3 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=2 " \
"-DL2_SIZE=2097152 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=16 " \
ARM64: Add the VULCAN Target
2016-10-04 16:50:20 +08:00
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
2018-11-16 23:45:12 +08:00
"-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
#define LIBNAME "falkor"
#define CORENAME "FALKOR"
ARM64: Add the VULCAN Target
2016-10-04 16:50:20 +08:00
#else
#endif
ARM64: Add Cavium THUNDERX Target
2017-01-10 14:27:36 +08:00
#ifdef FORCE_THUNDERX
#define FORCE
#define ARCHITECTURE "ARM64"
#define SUBARCHITECTURE "THUNDERX"
#define SUBDIRNAME "arm64"
#define ARCHCONFIG "-DTHUNDERX " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=128 " \
"-DL2_SIZE=16777216 -DL2_LINESIZE=128 -DL2_ASSOCIATIVE=16 " \
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
2018-11-16 23:45:12 +08:00
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
"-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
ARM64: Add Cavium THUNDERX Target
2017-01-10 14:27:36 +08:00
#define LIBNAME "thunderx"
#define CORENAME "THUNDERX"
#else
#endif
ARM64: Add Cavium THUNDERX2T99 Target
2017-01-10 16:55:55 +08:00
#ifdef FORCE_THUNDERX2T99
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
2018-11-16 23:45:12 +08:00
#define ARMV8
ARM64: Add Cavium THUNDERX2T99 Target
2017-01-10 16:55:55 +08:00
#define FORCE
#define ARCHITECTURE "ARM64"
#define SUBARCHITECTURE "THUNDERX2T99"
#define SUBDIRNAME "arm64"
#define ARCHCONFIG "-DTHUNDERX2T99 " \
"-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
"-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
"-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
2018-11-16 23:45:12 +08:00
"-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
ARM64: Add Cavium THUNDERX2T99 Target
2017-01-10 16:55:55 +08:00
#define LIBNAME "thunderx2t99"
#define CORENAME "THUNDERX2T99"
#else
#endif
add TARGET support for HiSilicon tsv110 CPUs
2019-03-04 16:45:22 +08:00
#ifdef FORCE_TSV110
#define FORCE
#define ARCHITECTURE "ARM64"
#define SUBARCHITECTURE "TSV110"
#define SUBDIRNAME "arm64"
#define ARCHCONFIG "-DTSV110 " \
"-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=4 " \
"-DL1_DATA_SIZE=65536 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=4 " \
"-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
"-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
#define LIBNAME "tsv110"
#define CORENAME "TSV110"
#else
#endif
Add Ampere EMAG8180
2020-02-25 21:30:00 +08:00
#ifdef FORCE_EMAG8180
#define ARMV8
#define FORCE
#define ARCHITECTURE "ARM64"
#define SUBARCHITECTURE "EMAG8180"
#define SUBDIRNAME "arm64"
#define ARCHCONFIG "-DEMAG8180 " \
"-DL1_CODE_SIZE=32768 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
"-DL2_SIZE=262144 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
"-DL3_SIZE=33554432 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
"-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
#define LIBNAME "emag8180"
#define CORENAME "EMAG8180"
#endif
add TARGET support for HiSilicon tsv110 CPUs
2019-03-04 16:45:22 +08:00
ARM64: Add THUNDERX3T110 Target
2020-06-11 19:12:49 +08:00
#ifdef FORCE_THUNDERX3T110
#define ARMV8
#define FORCE
#define ARCHITECTURE "ARM64"
#define SUBARCHITECTURE "THUNDERX3T110"
#define SUBDIRNAME "arm64"
#define ARCHCONFIG "-DTHUNDERX3T110 " \
"-DL1_CODE_SIZE=65536 -DL1_CODE_LINESIZE=64 -DL1_CODE_ASSOCIATIVE=8 " \
"-DL1_DATA_SIZE=32768 -DL1_DATA_LINESIZE=64 -DL1_DATA_ASSOCIATIVE=8 " \
"-DL2_SIZE=524288 -DL2_LINESIZE=64 -DL2_ASSOCIATIVE=8 " \
"-DL3_SIZE=94371840 -DL3_LINESIZE=64 -DL3_ASSOCIATIVE=32 " \
"-DDTB_DEFAULT_ENTRIES=64 -DDTB_SIZE=4096 " \
"-DHAVE_VFPV4 -DHAVE_VFPV3 -DHAVE_VFP -DHAVE_NEON -DARMV8"
#define LIBNAME "thunderx3t110"
#define CORENAME "THUNDERX3T110"
#else
#endif
Add support for TARGET=ZARCH_GENERIC and TARGET=Z13
2017-09-19 18:16:42 +08:00
#ifdef FORCE_ZARCH_GENERIC
#define FORCE
#define ARCHITECTURE "ZARCH"
#define SUBARCHITECTURE "ZARCH_GENERIC"
#define ARCHCONFIG "-DZARCH_GENERIC " \
"-DDTB_DEFAULT_ENTRIES=64"
#define LIBNAME "zarch_generic"
#define CORENAME "ZARCH_GENERIC"
#endif
#ifdef FORCE_Z13
#define FORCE
#define ARCHITECTURE "ZARCH"
#define SUBARCHITECTURE "Z13"
#define ARCHCONFIG "-DZ13 " \
"-DDTB_DEFAULT_ENTRIES=64"
#define LIBNAME "z13"
#define CORENAME "Z13"
#endif
Add FORCE Z14 from patch provided by aarnez in #991
2019-02-01 04:15:50 +08:00
#ifdef FORCE_Z14
#define FORCE
#define ARCHITECTURE "ZARCH"
#define SUBARCHITECTURE "Z14"
#define ARCHCONFIG "-DZ14 " \
"-DDTB_DEFAULT_ENTRIES=64"
#define LIBNAME "z14"
#define CORENAME "Z14"
#endif
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#ifndef FORCE
Validate user supplied TARGET (#1941) the build will now abort with an error message when an undefined build TARGET is named Fixes #1938
2019-01-01 06:19:44 +08:00
#ifdef USER_TARGET
#error "The TARGET specified on the command line or in Makefile.rule is not supported. Please choose a target from TargetList.txt"
#endif
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#if defined(__powerpc__) || defined(__powerpc) || defined(powerpc) || \
defined(__PPC__) || defined(PPC) || defined(_POWER) || defined(__POWERPC__)
#ifndef POWER
#define POWER
#endif
Fixed #19. Provided an error msg when the arch is not supported.
2011-04-22 20:21:42 +08:00
#define OPENBLAS_SUPPORTED
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#endif
Init IBM z system (s390x) porting.
2016-04-16 06:02:24 +08:00
#if defined(__zarch__) || defined(__s390x__)
#define ZARCH
#include "cpuid_zarch.c"
#define OPENBLAS_SUPPORTED
#endif
Added MSVC defines to cpuid.h and getarch.c.
2015-01-02 11:01:28 +08:00
#ifdef INTEL_AMD
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#include "cpuid_x86.c"
Fixed #19. Provided an error msg when the arch is not supported.
2011-04-22 20:21:42 +08:00
#define OPENBLAS_SUPPORTED
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#endif
#ifdef __ia64__
#include "cpuid_ia64.c"
Fixed #19. Provided an error msg when the arch is not supported.
2011-04-22 20:21:42 +08:00
#define OPENBLAS_SUPPORTED
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#endif
#ifdef __alpha
#include "cpuid_alpha.c"
Fixed #19. Provided an error msg when the arch is not supported.
2011-04-22 20:21:42 +08:00
#define OPENBLAS_SUPPORTED
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#endif
#ifdef POWER
#include "cpuid_power.c"
Fixed #19. Provided an error msg when the arch is not supported.
2011-04-22 20:21:42 +08:00
#define OPENBLAS_SUPPORTED
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#endif
#ifdef sparc
#include "cpuid_sparc.c"
Fixed #19. Provided an error msg when the arch is not supported.
2011-04-22 20:21:42 +08:00
#define OPENBLAS_SUPPORTED
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#endif
#ifdef __mips__
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
#ifdef __mips64
#include "cpuid_mips64.c"
#else
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#include "cpuid_mips.c"
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
#endif
Fixed #19. Provided an error msg when the arch is not supported.
2011-04-22 20:21:42 +08:00
#define OPENBLAS_SUPPORTED
#endif
Added RISCV build
2018-04-17 03:34:43 +08:00
#ifdef __riscv
#include "cpuid_riscv64.c"
#endif
modified getarch.c
2013-12-02 00:31:22 +08:00
#ifdef __arm__
#include "cpuid_arm.c"
#define OPENBLAS_SUPPORTED
#endif
# The first commit's message is: Optimizations for APM's xgene-1 (aarch64). 1) general system updates to support armv8 better. Make all did not work, one needed to supply TARGET=ARMV8. 2) sgem 4x4 kernel in assembler using SIMD, and configuration changes to use it. 3) strmm 4x4 kernel in C. Since the sgem kernel does 4x4, the trmm kernel must also do 4xN. Added Dave Nuechterlein to the contributors list.
2014-10-09 21:52:10 +08:00
#ifdef __aarch64__
#include "cpuid_arm64.c"
#define OPENBLAS_SUPPORTED
#endif
modified getarch.c
2013-12-02 00:31:22 +08:00
Fixed #19. Provided an error msg when the arch is not supported.
2011-04-22 20:21:42 +08:00
#ifndef OPENBLAS_SUPPORTED
#error "This arch/CPU is not supported by OpenBLAS."
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#endif
#else
#endif
static int get_num_cores(void) {
#ifdef OS_WINDOWS
SYSTEM_INFO sysinfo;
Add NetBSD
2019-10-25 18:51:06 +08:00
#elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
int m[2], count;
size_t len;
#endif
Remove all trailing whitespace except lapack-netlib Signed-off-by: Timothy Gu <timothygu99@gmail.com>
2014-06-28 03:05:18 +08:00
make parallel make work on illumos
2016-01-23 00:48:50 +08:00
#if defined(linux) || defined(__sun__)
Refs #248. Fixed the LSB compatiable issue for BLAS only. For example, make CC=lsbcc NO_LAPACK=1.
2013-07-09 15:38:03 +08:00
//returns the number of processors which are currently online
USE NPROCESSOR_CONF instaed of NPORCESSOR_ONLN to determine the number of CPU. In ARM platform, online CPU will increasing when there is more workload. while configure cpu is the max number of CPU.
2016-10-13 20:37:50 +08:00
return sysconf(_SC_NPROCESSORS_CONF);
Remove all trailing whitespace except lapack-netlib Signed-off-by: Timothy Gu <timothygu99@gmail.com>
2014-06-28 03:05:18 +08:00
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#elif defined(OS_WINDOWS)
GetSystemInfo(&sysinfo);
return sysinfo.dwNumberOfProcessors;
Add NetBSD
2019-10-25 18:51:06 +08:00
#elif defined(__FreeBSD__) || defined(__OpenBSD__) || defined(__NetBSD__) || defined(__DragonFly__) || defined(__APPLE__)
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
m[0] = CTL_HW;
m[1] = HW_NCPU;
len = sizeof(int);
sysctl(m, 2, &count, &len, NULL, 0);
return count;
Obtain actual cpu count on AIX and suppress spurious NO_AVX512 on non-x86
2020-07-07 21:46:32 +08:00
#elif defined(AIX)
//returns the number of processors which are currently online
return sysconf(_SC_NPROCESSORS_ONLN);
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#else
return 2;
#endif
}
int main(int argc, char *argv[]){
#ifdef FORCE
char buffer[8192], *p, *q;
int length;
#endif
if (argc == 1) return 0;
switch (argv[1][0]) {
case '0' : /* for Makefile */
#ifdef FORCE
printf("CORE=%s\n", CORENAME);
Remove all trailing whitespace except lapack-netlib Signed-off-by: Timothy Gu <timothygu99@gmail.com>
2014-06-28 03:05:18 +08:00
#else
Use get_corename for SPARC as well
2018-02-02 01:20:38 +08:00
#if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc)
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
printf("CORE=%s\n", get_corename());
#endif
#endif
#ifdef FORCE
printf("LIBCORE=%s\n", LIBNAME);
#else
printf("LIBCORE=");
get_libname();
printf("\n");
#endif
printf("NUM_CORES=%d\n", get_num_cores());
modified getarch.c
2013-12-02 00:31:22 +08:00
#if defined(__arm__) && !defined(FORCE)
get_features();
#endif
Added MSVC defines to cpuid.h and getarch.c.
2015-01-02 11:01:28 +08:00
#ifdef INTEL_AMD
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
#ifndef FORCE
get_sse();
#else
sprintf(buffer, "%s", ARCHCONFIG);
p = &buffer[0];
while (*p) {
if ((*p == '-') && (*(p + 1) == 'D')) {
p += 2;
while ((*p != ' ') && (*p != '\0')) {
if (*p == '=') {
printf("=");
p ++;
while ((*p != ' ') && (*p != '\0')) {
printf("%c", *p);
p ++;
}
} else {
printf("%c", *p);
p ++;
if ((*p == ' ') || (*p =='\0')) printf("=1");
}
}
printf("\n");
} else p ++;
}
#endif
#endif
Get endianness into Makefile variable
2020-02-20 01:08:20 +08:00
#if defined(__BYTE_ORDER__) && __BYTE_ORDER__ == __ORDER_BIG_ENDIAN__
printf("__BYTE_ORDER__=__ORDER_BIG_ENDIAN__\n");
Avoid duplicate printout of byte order and report ELF_VERSION
2020-04-22 20:12:27 +08:00
#elif defined(__BIG_ENDIAN__) && __BIG_ENDIAN__ > 0
Get endianness into Makefile variable
2020-02-20 01:08:20 +08:00
printf("__BYTE_ORDER__=__ORDER_BIG_ENDIAN__\n");
#endif
Avoid duplicate printout of byte order and report ELF_VERSION
2020-04-22 20:12:27 +08:00
#if defined(_CALL_ELF) && (_CALL_ELF == 2)
printf("ELF_VERSION=2\n");
#endif
Get endianness into Makefile variable
2020-02-20 01:08:20 +08:00
Allow to force the number of parallel make job This is particularly useful when using distcc
2015-12-29 02:28:42 +08:00
#ifdef MAKE_NB_JOBS
Allow to force to do not use -j as make argument Close #828 (hopefully)
2016-04-01 05:03:52 +08:00
#if MAKE_NB_JOBS > 0
Allow to force the number of parallel make job This is particularly useful when using distcc
2015-12-29 02:28:42 +08:00
printf("MAKE += -j %d\n", MAKE_NB_JOBS);
Allow to force to do not use -j as make argument Close #828 (hopefully)
2016-04-01 05:03:52 +08:00
#else
// Let make use parent -j argument or -j1 if there
// is no make parent
#endif
Allow to force the number of parallel make job This is particularly useful when using distcc
2015-12-29 02:28:42 +08:00
#elif NO_PARALLEL_MAKE==1
Added NO_PARALLEL_MAKE flag to disable parallel make.
2013-04-15 21:37:30 +08:00
printf("MAKE += -j 1\n");
#else
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
printf("MAKE += -j %d\n", get_num_cores());
#endif
break;
case '1' : /* For config.h */
#ifdef FORCE
sprintf(buffer, "%s -DCORE_%s\n", ARCHCONFIG, CORENAME);
p = &buffer[0];
while (*p) {
if ((*p == '-') && (*(p + 1) == 'D')) {
p += 2;
printf("#define ");
while ((*p != ' ') && (*p != '\0')) {
if (*p == '=') {
printf(" ");
p ++;
while ((*p != ' ') && (*p != '\0')) {
printf("%c", *p);
p ++;
}
} else {
Fix spurious define in openblas_config.h TARGET as specified with make is already return-terminated when getarch reads it. This led to an empty line written to config_last.h that awk in Makefile.install then expanded to a spurious "#define OPENBLAS_" in openblas_config.h (as noted by "kmb" on the mailing list)
2016-11-07 00:29:33 +08:00
if (*p != '\n')
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
printf("%c", *p);
p ++;
}
}
printf("\n");
} else p ++;
}
#else
get_cpuconfig();
#endif
Fixed #407. Support outputing the CPU corename on runtime. The user can use char * openblas_get_config() or char * openblas_get_corename().
2014-07-08 12:48:08 +08:00
#ifdef FORCE
printf("#define CHAR_CORENAME \"%s\"\n", CORENAME);
#else
Use get_corename for SPARC as well
2018-02-02 01:20:38 +08:00
#if defined(INTEL_AMD) || defined(POWER) || defined(__mips__) || defined(__arm__) || defined(__aarch64__) || defined(ZARCH) || defined(sparc)
Fixed #407. Support outputing the CPU corename on runtime. The user can use char * openblas_get_config() or char * openblas_get_corename().
2014-07-08 12:48:08 +08:00
printf("#define CHAR_CORENAME \"%s\"\n", get_corename());
#endif
#endif
Import GotoBLAS2 1.13 BSD version codes.
2011-01-24 22:54:24 +08:00
break;
case '2' : /* SMP */
if (get_num_cores() > 1) printf("SMP=1\n");
break;
}
fflush(stdout);
return 0;
}