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OpenBLAS/TargetList.txt

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Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
Force Target Examples:
make TARGET=NEHALEM
make TARGET=LOONGSON3A BINARY=64
make TARGET=ISTANBUL
Supported List:
1.X86/X86_64
a)Intel CPU:
P2
KATMAI
TargetList.txt: minor re-ordering
2013-03-17 23:03:05 +08:00
COPPERMINE
Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
NORTHWOOD
PRESCOTT
BANIAS
YONAH
CORE2
PENRYN
DUNNINGTON
NEHALEM
Init Sandybridge codes based on Nehalem.
2012-03-30 20:01:03 +08:00
SANDYBRIDGE
Add HASWELL to TargetList.txt The Intel "Haswell" architecture is missing from the list of build targets.
2014-09-17 06:26:45 +08:00
HASWELL
Initial support for SkylakeX / AVX512 This patch adds the basic infrastructure for adding the SkylakeX (Intel Skylake server) target. The SkylakeX target will use the AVX512 (AVX512VL level) instruction set, which brings 2 basic things: 1) 512 bit wide SIMD (2x width of AVX2) 2) 32 SIMD registers (2x the number on AVX2) This initial patch only contains a trivial transofrmation of the Haswell SGEMM kernel to AVX512VL; more will follow later but this patch aims to get the infrastructure in place for this "later". Full performance tuning has not been done yet; with more registers and wider SIMD it's in theory possible to retune the kernels but even without that there's an interesting enough performance increase (30-40% range) with just this change.
2018-06-03 15:24:29 +08:00
SKYLAKEX
Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
ATOM
Enable COOPERLAKE build target Enable new build target platform -- COOPERLAKE. This target platform supports all the SKYLAKEX supported ISAs + avx512bf16. So all the SKYLAKEX specific kernels/drivers and related code are now extended to be also active on COOPERLAKE. Besides, new BF16 related kernels are active under this target.
2020-08-13 06:17:34 +08:00
COOPERLAKE
Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
b)AMD CPU:
ATHLON
OPTERON
OPTERON_SSE3
BARCELONA
SHANGHAI
ISTANBUL
Refs #113. Fixed the typo BOBCATE -> BOBCAT
2012-05-31 22:40:15 +08:00
BOBCAT
Added BULLDOZER target. So far it uses barcelona kernels.
2012-12-07 00:53:31 +08:00
BULLDOZER
Update the doc for target list.
2014-09-17 14:29:21 +08:00
PILEDRIVER
added target processor STEAMROLLER
2014-12-28 20:16:46 +08:00
STEAMROLLER
Add AMD Excavator target.
2015-05-14 05:16:30 +08:00
EXCAVATOR
Add ZEN support (tested for auto-detected static backend)
2017-03-19 22:32:50 +08:00
ZEN
Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
c)VIA CPU:
SSE_GENERIC
VIAC3
NANO
2.Power CPU:
POWER4
POWER5
POWER6
Add POWER7/POWER8 as targets
2015-08-05 22:02:39 +08:00
POWER7
POWER8
power9 makefile. dgemm based on power8 kernel with following changes : 32x unrolled 16x4 kernel and 8x4 kernel using (lxv stxv butterfly rank1 update). improvement from 17 to 22-23gflops. dtrmm cases were added into dgemm itself
2019-03-14 18:42:04 +08:00
POWER9
powerpc: Add support for future processor This is the initial patch to support build infrastructure for POWER10 architecture.
2020-06-12 04:47:20 +08:00
POWER10
Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
PPCG4
PPC970
PPC970MP
PPC440
PPC440FP2
CELL
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
3.MIPS CPU:
P5600
Update TargetList.txt
2020-04-19 12:51:57 +08:00
MIPS1004K
MIPS24K
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
4.MIPS64 CPU:
Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
SICORTEX
LOONGSON3A
Init Sandybridge codes based on Nehalem.
2012-03-30 20:01:03 +08:00
LOONGSON3B
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
I6400
Added MSA optimization for GEMV_N, GEMV_T, ASUM, DOT functions Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-07-15 21:08:25 +08:00
P6600
Added mips I6500 core Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2017-09-22 14:27:43 +08:00
I6500
Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
5.IA64 CPU:
Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
ITANIUM2
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
6.SPARC CPU:
Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
SPARC
SPARCV7
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
7.ARM CPU:
Add ARM targets.
2015-03-25 01:17:04 +08:00
CORTEXA15
CORTEXA9
Update the doc for target list.
2014-09-17 14:29:21 +08:00
ARMV7
ARMV6
ARMV5
Add ARM targets.
2015-03-25 01:17:04 +08:00
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
8.ARM 64-bit CPU:
Add ARM targets.
2015-03-25 01:17:04 +08:00
ARMV8
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
2018-11-16 23:45:12 +08:00
CORTEXA53
Adding arm64 target CORTEXA57 Co-Authored-By: Ralph Campbell <ralph.campbell@broadcom.com>
2015-09-04 15:56:52 +08:00
CORTEXA57
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
2018-11-16 23:45:12 +08:00
CORTEXA72
CORTEXA73
Add Neoverse-N1 core The implementation is a hybird of the ARMV8 one with some of the improved TX2 rountines along with specifying -march=v8.2-a
2020-02-22 06:46:58 +08:00
NEOVERSEN1
Add Ampere EMAG8180
2020-03-02 07:02:36 +08:00
EMAG8180
Simplifying ARMv8 build parameters ARMv8 builds were a bit mixed up, with ThunderX2 code in ARMv8 mode (which is not right because TX2 is ARMv8.1) as well as requiring a few redundancies in the defines, making it harder to maintain and understand what core has what. A few other minor issues were also fixed. Tests were made on the following cores: A53, A57, A72, Falkor, ThunderX, ThunderX2, and XGene. Tests were: OpenBLAS/test, OpenBLAS/benchmark, BLAS-Tester. A summary: * Removed TX2 code from ARMv8 build, to make sure it is compatible with all ARMv8 cores, not just v8.1. Also, the TX2 code has actually harmed performance on big cores. * Commoned up ARMv8 architectures' defines in params.h, to make sure that all will benefit from ARMv8 settings, in addition to their own. * Adding a few more cores, using ARMv8's include strategy, to benefit from compiler optimisations using mtune. Also updated cache information from the manuals, making sure we set good conservative values by default. Removed Vulcan, as it's an alias to TX2. * Auto-detecting most of those cores, but also updating the forced compilation in getarch.c, to make sure the parameters are the same whether compiled natively or forced arch. Benefits: * ARMv8 build is now guaranteed to work on all ARMv8 cores * Improved performance for ARMv8 builds on some cores (A72, Falkor, ThunderX1 and 2: up to 11%) over current develop * Improved performance for *all* cores comparing to develop branch before TX2's patch (9% ~ 36%) * ThunderX1 builds are 14% faster than ARMv8 on TX1, 9% faster than current develop's branch and 8% faster than deveop before tx2 patches Issues: * Regression from current develop branch for A53 (-12%) and A57 (-3%) with ARMv8 builds, but still faster than before TX2's commit (+15% and +24% respectively). This can be improved with a simplification of TX2's code, to be done in future patches. At least the code is guaranteed to be ARMv8.0 now. Comments: * CortexA57 builds are unchanged on A57 hardware from develop's branch, which makes sense, as it's untouched. * CortexA72 builds improve over A57 on A72 hardware, even if they're using the same includes due to new compiler tunning in the makefile.
2018-11-16 23:45:12 +08:00
FALKOR
ARM64: Add Cavium THUNDERX Target
2017-01-10 14:27:36 +08:00
THUNDERX
ARM64: Add Cavium THUNDERX2T99 Target
2017-01-10 16:55:55 +08:00
THUNDERX2T99
add TARGET support for HiSilicon tsv110 CPUs
2019-03-04 16:48:49 +08:00
TSV110
ARM64: Add THUNDERX3T110 Target
2020-06-11 19:12:49 +08:00
THUNDERX3T110
Rename SILICON to VORTEX
2020-09-03 14:38:53 +08:00
VORTEX
Adding arm64 target CORTEXA57 Co-Authored-By: Ralph Campbell <ralph.campbell@broadcom.com>
2015-09-04 15:56:52 +08:00
Add support for TARGET=ZARCH_GENERIC and TARGET=Z13
2017-09-19 18:16:42 +08:00
9.System Z:
ZARCH_GENERIC
Z13
Add Z14 target from patch provided by aarnez in #991
2019-02-01 04:13:46 +08:00
Z14
Change default RISC-V 64-bit corename to RISCV64_GENERIC e.g. make CC=riscv64-unknown-linux-gnu-gcc FC=riscv64-unknown-linux-gnu-gfortran TARGET=RISCV64_GENERIC HOSTCC=gcc
2020-02-27 14:46:15 +08:00
10.RISC-V 64:
RISCV64_GENERIC