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OpenBLAS/TargetList.txt

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Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
Force Target Examples:
make TARGET=NEHALEM
make TARGET=LOONGSON3A BINARY=64
make TARGET=ISTANBUL
Supported List:
1.X86/X86_64
a)Intel CPU:
P2
KATMAI
TargetList.txt: minor re-ordering
2013-03-17 23:03:05 +08:00
COPPERMINE
Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
NORTHWOOD
PRESCOTT
BANIAS
YONAH
CORE2
PENRYN
DUNNINGTON
NEHALEM
Init Sandybridge codes based on Nehalem.
2012-03-30 20:01:03 +08:00
SANDYBRIDGE
Add HASWELL to TargetList.txt The Intel "Haswell" architecture is missing from the list of build targets.
2014-09-17 06:26:45 +08:00
HASWELL
Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
ATOM
b)AMD CPU:
ATHLON
OPTERON
OPTERON_SSE3
BARCELONA
SHANGHAI
ISTANBUL
Refs #113. Fixed the typo BOBCATE -> BOBCAT
2012-05-31 22:40:15 +08:00
BOBCAT
Added BULLDOZER target. So far it uses barcelona kernels.
2012-12-07 00:53:31 +08:00
BULLDOZER
Update the doc for target list.
2014-09-17 14:29:21 +08:00
PILEDRIVER
added target processor STEAMROLLER
2014-12-28 20:16:46 +08:00
STEAMROLLER
Add AMD Excavator target.
2015-05-14 05:16:30 +08:00
EXCAVATOR
Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
c)VIA CPU:
SSE_GENERIC
VIAC3
NANO
2.Power CPU:
POWER4
POWER5
POWER6
Add POWER7/POWER8 as targets
2015-08-05 22:02:39 +08:00
POWER7
POWER8
Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
PPCG4
PPC970
PPC970MP
PPC440
PPC440FP2
CELL
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
3.MIPS CPU:
P5600
4.MIPS64 CPU:
Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
SICORTEX
LOONGSON3A
Init Sandybridge codes based on Nehalem.
2012-03-30 20:01:03 +08:00
LOONGSON3B
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
I6400
Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
5.IA64 CPU:
Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
ITANIUM2
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
6.SPARC CPU:
Added docs for make TARGET=your_cpu_target.
2011-04-22 22:07:46 +08:00
SPARC
SPARCV7
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
7.ARM CPU:
Add ARM targets.
2015-03-25 01:17:04 +08:00
CORTEXA15
CORTEXA9
Update the doc for target list.
2014-09-17 14:29:21 +08:00
ARMV7
ARMV6
ARMV5
Add ARM targets.
2015-03-25 01:17:04 +08:00
MIPS P5600(32 bit) and I6400(64 bit) cores support added. Seperated mips and mips64 files. Configurations support for mips 32 bit. Signed-off-by: Shivraj Patil <shivraj.patil@imgtec.com>
2016-04-22 16:33:18 +08:00
8.ARM 64-bit CPU:
Add ARM targets.
2015-03-25 01:17:04 +08:00
ARMV8
Adding arm64 target CORTEXA57 Co-Authored-By: Ralph Campbell <ralph.campbell@broadcom.com>
2015-09-04 15:56:52 +08:00
CORTEXA57