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734 Commits

Author SHA1 Message Date
mindspore-ci-bot 093c2caed4 !337 optimize execute order sort 
Merge pull request !337 from kisnwang/optimize-execute-order-sort
 2020-04-18 17:27:55 +08:00
liuxiao 5c9791a802 Add Abs\AbsGrad\Sign\SmoothL1Loss\SmoothL1LossGrad and modify TopKV2->TopK for VM 2020-04-18 15:21:44 +08:00
kswang 6775190e48 add cpu one hot 2020-04-18 14:44:03 +08:00
ougongchang 0ed6d9178e add Histogram summary operator 
clean clang format errors and cpplint errors

add some test cases for histogram summary operator
 2020-04-18 09:56:45 +08:00
wilfChen 5432fcb43f gpu support RMSProp kernel 2020-04-18 09:26:45 +08:00
wilfChen 9a7702b807 gpu support batchmatmul kernel 2020-04-18 09:21:12 +08:00
kswang 83eeac9310 optimize execute order sort 2020-04-17 15:09:48 +08:00
mindspore-ci-bot 87be386581 !314 GPU add kernel assign 
Merge pull request !314 from VectorSL/assign
 2020-04-16 19:36:30 +08:00
ZPaC 4cd237eee4 Add GPU NCCL ci test cases. 2020-04-16 10:47:39 +08:00
chujinjin b804d9103d set default execution mode to pynative 2020-04-15 14:11:25 +08:00
wilfChen cc93646207 gpu concat kernel support 4 inputs 2020-04-15 09:46:36 +08:00
wilfChen 5b7790a2a7 Gpu Slice kernel performance improvement 2020-04-15 09:11:07 +08:00
mindspore-ci-bot 7d7c9c4fee !311 GPU add akg kernel select 
Merge pull request !311 from VectorSL/select
 2020-04-14 21:25:16 +08:00
dengwentao 48f90eb7bc add custom op st to ci 2020-04-14 20:16:14 +08:00
VectorSL 9e372073e2 gpu add assigin 2020-04-14 20:11:44 +08:00
VectorSL d248b05a98 gpu add kernel select 2020-04-14 20:03:33 +08:00
mindspore-ci-bot 94589ce611 !226 expend conv stride and dilation to 2d 
Merge pull request !226 from wangnan39/expend_conv_stride_to_2d
 2020-04-14 14:58:22 +08:00
chenzomi 652ab6c386 add test case for aware quantizaiton 2020-04-14 14:00:35 +08:00
wangnan39@huawei.com 2604acedcb extend conv stride and dilation to 2d 2020-04-14 13:16:27 +08:00
zjun f5ee197b6c Modify custom op register 2020-04-10 16:52:31 +08:00
mindspore-ci-bot 3e36982314 !99 Develop op MaxPoolWithArgMax 
Merge pull request !99 from zhangbuxue/Dock_MaxPoolWithArgMax
 2020-04-08 22:40:00 +08:00
buxue 7541d3b067 Develop op MaxPoolWithArgMax 2020-04-08 20:47:49 +08:00
mindspore-ci-bot 3f5136302a !149 Use TFRecordDataset instead of StorageDataset in Bert model integration test and add absolute position embedding code in bert model 
Merge pull request !149 from yoonlee666/master
 2020-04-08 20:28:06 +08:00
yoonlee666 c5bfbc3556 use TFRecordDataset in bert ci script and add absolute position embedding code in bert model 2020-04-08 14:31:18 +08:00
zhaozhenlong f9d180d413 add api image gradients 2020-04-08 11:50:22 +08:00
wanghua 5b176f258b modify bert test file 2020-04-03 18:20:50 +08:00
wanghua da123c5b3e fix bert precison bug 2020-04-03 14:55:25 +08:00
xiefangqi bc4602b58e fix and remove useless import of example, st, ut 2020-04-02 22:13:36 +08:00
lvliang ff4f935e40 pynative-add-lenet 2020-04-02 09:25:25 +08:00
mindspore-ci-bot a42eee52ba !67 add cpu st lenet 
Merge pull request !67 from kisnwang/add-cpu-st
 2020-04-01 15:15:13 +08:00
VectorSL aea6b0c974 update tests/st/ops/gpu/test_tensoradd.py. 
fix pytest.mark for testcase
 2020-04-01 11:49:37 +08:00
kswang 2dc9f632c1 add cpu st lenet 2020-03-31 21:25:48 +08:00
lichenever 30231eab2f fix auto parallel st 2020-03-31 11:19:06 +08:00
zhunaipan 930a1fb0a8 initial version 
Signed-off-by: leonwanghui <leon.wanghui@huawei.com>
 2020-03-27 22:54:54 +08:00