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!7025 [MS][LITE][Develop]syc op_base act type with schema 

Merge pull request !7025 from mengyuanli/syc_act_type
This commit is contained in:
mindspore-ci-bot 2020-09-30 09:24:16 +08:00 committed by Gitee
parent 6c3cfe3036 d56eb90044
commit dc5adf0137
10 changed files with 19 additions and 19 deletions
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2
mindspore/lite/nnacl/assembly/arm32/MatmulFp32.S
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@ -91,7 +91,7 @@ LoopCol:
Activation: Activation:
ldr lr, [sp] ldr lr, [sp]
cmp lr, #2 cmp lr, #3
beq Relu6 beq Relu6
cmp lr, #1 cmp lr, #1
beq Relu beq Relu

2
mindspore/lite/nnacl/assembly/arm32/MatmulFp32Opt.S
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@ -106,7 +106,7 @@ LoopRow:
Activation: Activation:
ldr lr, [sp] ldr lr, [sp]
cmp lr, #2 cmp lr, #3
beq Relu6 beq Relu6
cmp lr, #1 cmp lr, #1
beq Relu beq Relu

2
mindspore/lite/nnacl/assembly/arm64/MatmulFp32.S
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@ -171,7 +171,7 @@ Bias:
fadd v31.4s, v31.4s, v1.4s fadd v31.4s, v31.4s, v1.4s
Activation: Activation:
cmp w4, #2 cmp w4, #3
beq Relu6 beq Relu6
cmp w4, #1 cmp w4, #1
beq Relu beq Relu

12
mindspore/lite/nnacl/assembly/arm64/MatmulFp32Opt.S
View File

@ -159,7 +159,7 @@ LoopRow:
fadd v31.4s, v31.4s, v1.4s fadd v31.4s, v31.4s, v1.4s
Activation: Activation:
cmp x4, #2 cmp x4, #3
beq Relu6 beq Relu6
cmp x4, #1 cmp x4, #1
beq Relu beq Relu
@ -278,7 +278,7 @@ LoopRow:
fadd v30.4s, v30.4s, v0.4s fadd v30.4s, v30.4s, v0.4s
ActivationHalf: ActivationHalf:
cmp x4, #2 cmp x4, #3
beq Relu6Half beq Relu6Half
cmp x4, #1 cmp x4, #1
beq ReluHalf beq ReluHalf
@ -401,7 +401,7 @@ LoopRow8:
fadd v23.4s, v23.4s, v1.4s fadd v23.4s, v23.4s, v1.4s
Activation8: Activation8:
cmp x4, #2 cmp x4, #3
beq Relu68 beq Relu68
cmp x4, #1 cmp x4, #1
beq Relu8 beq Relu8
@ -492,7 +492,7 @@ LoopRow8:
fadd v22.4s, v22.4s, v0.4s fadd v22.4s, v22.4s, v0.4s
ActivationHalf8: ActivationHalf8:
cmp x4, #2 cmp x4, #3
beq Relu6Half8 beq Relu6Half8
cmp x4, #1 cmp x4, #1
beq ReluHalf8 beq ReluHalf8
@ -582,7 +582,7 @@ LoopRow4:
fadd v15.4s, v15.4s, v1.4s fadd v15.4s, v15.4s, v1.4s
Activation4: Activation4:
cmp x4, #2 cmp x4, #3
beq Relu64 beq Relu64
cmp x4, #1 cmp x4, #1
beq Relu4 beq Relu4
@ -645,7 +645,7 @@ LoopRow4:
fadd v14.4s, v14.4s, v0.4s fadd v14.4s, v14.4s, v0.4s
ActivationHalf4: ActivationHalf4:
cmp x4, #2 cmp x4, #3
beq Relu6Half4 beq Relu6Half4
cmp x4, #1 cmp x4, #1
beq ReluHalf4 beq ReluHalf4

2
mindspore/lite/nnacl/assembly/arm64/PostFuncBiasReluC8.S
View File

@ -67,7 +67,7 @@ Loop8x8:
fadd v14.4s, v14.4s, v16.4s fadd v14.4s, v14.4s, v16.4s
fadd v15.4s, v15.4s, v17.4s fadd v15.4s, v15.4s, v17.4s
cmp w7, #2 cmp w7, #3
beq Relu6_8x8 beq Relu6_8x8
cmp w7, #1 cmp w7, #1
beq Relu_8x8 beq Relu_8x8

2
mindspore/lite/nnacl/assembly/fp16/MatmulFp16.S
View File

@ -249,7 +249,7 @@ Bias:
fadd v31.8h, v31.8h, v0.8h fadd v31.8h, v31.8h, v0.8h
Activation: Activation:
cmp w4, #2 cmp w4, #3
beq Relu6 beq Relu6
cmp w4, #1 cmp w4, #1
beq Relu beq Relu

10
mindspore/lite/nnacl/assembly/fp16/MatmulFp16Opt.S
View File

@ -205,7 +205,7 @@ LoopRow16:
fadd v31.8h, v31.8h, v0.8h fadd v31.8h, v31.8h, v0.8h
Activation16: Activation16:
cmp x4, #2 cmp x4, #3
beq Relu616 beq Relu616
cmp x4, #1 cmp x4, #1
beq Relu16 beq Relu16
@ -344,7 +344,7 @@ LoopRow8:
fadd v23.8h, v23.8h, v0.8h fadd v23.8h, v23.8h, v0.8h
Activation8: Activation8:
cmp x4, #2 cmp x4, #3
beq Relu68 beq Relu68
cmp x4, #1 cmp x4, #1
beq Relu8 beq Relu8
@ -439,7 +439,7 @@ LoopRow4:
fadd v19.8h, v19.8h, v0.8h fadd v19.8h, v19.8h, v0.8h
Activation4: Activation4:
cmp x4, #2 cmp x4, #3
beq Relu64 beq Relu64
cmp x4, #1 cmp x4, #1
beq Relu4 beq Relu4
@ -512,7 +512,7 @@ LoopRow2:
fadd v17.8h, v17.8h, v0.8h fadd v17.8h, v17.8h, v0.8h
Activation2: Activation2:
cmp x4, #2 cmp x4, #3
beq Relu62 beq Relu62
cmp x4, #1 cmp x4, #1
beq Relu2 beq Relu2
@ -574,7 +574,7 @@ LoopRow:
fadd v16.8h, v16.8h, v0.8h fadd v16.8h, v16.8h, v0.8h
Activation: Activation:
cmp x4, #2 cmp x4, #3
beq Relu6 beq Relu6
cmp x4, #1 cmp x4, #1
beq Relu beq Relu

2
mindspore/lite/nnacl/fp16/deconv_fp16.c
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@ -44,7 +44,7 @@ void PostConvFuncFp16C8(const float16_t *c8_out_ptr, float16_t *out_ptr, const f
size_t oc8div = output_channel - oc8mod; size_t oc8div = output_channel - oc8mod;
size_t stride_size = stride * sizeof(float16_t); size_t stride_size = stride * sizeof(float16_t);
size_t relu_type = is_relu ? 1 : 0; size_t relu_type = is_relu ? 1 : 0;
relu_type = is_relu6 ? 2 : relu_type; relu_type = is_relu6 ? 3 : relu_type;
PostFuncBiasReluC8Fp16(out_ptr, c8_out_ptr, bias_ptr, oc8div, oc8mod, plane_size, stride_size, relu_type); PostFuncBiasReluC8Fp16(out_ptr, c8_out_ptr, bias_ptr, oc8div, oc8mod, plane_size, stride_size, relu_type);
return; return;
} }

2
mindspore/lite/nnacl/fp32/common_func.c
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@ -49,7 +49,7 @@ void PostConvFuncFp32C8(const float *c8_out_ptr, float *out_ptr, const float *bi
size_t oc8div = output_channel - oc8mod; size_t oc8div = output_channel - oc8mod;
size_t stride_size = stride * sizeof(float); size_t stride_size = stride * sizeof(float);
size_t relu_type = is_relu ? 1 : 0; size_t relu_type = is_relu ? 1 : 0;
relu_type = is_relu6 ? 2 : relu_type; relu_type = is_relu6 ? 3 : relu_type;
PostFuncBiasReluC8(out_ptr, c8_out_ptr, bias_ptr, oc8div, oc8mod, plane_size, stride_size, relu_type); PostFuncBiasReluC8(out_ptr, c8_out_ptr, bias_ptr, oc8div, oc8mod, plane_size, stride_size, relu_type);
#endif #endif
return; return;

2
mindspore/lite/nnacl/op_base.h
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@ -68,6 +68,6 @@ typedef struct OpParameter {
int thread_num_; int thread_num_;
} OpParameter; } OpParameter;
typedef enum ActType { ActType_No, ActType_Relu, ActType_Relu6, ActType_Prelu } ActType; typedef enum ActType { ActType_No, ActType_Relu, ActType_Sigmod, ActType_Relu6, ActType_Prelu } ActType;
#endif // MINDSPORE_LITE_NNACL_OP_BASE_H_ #endif // MINDSPORE_LITE_NNACL_OP_BASE_H_