forked from mindspore-Ecosystem/mindspore
!7670 add l2normalize gpu kernel.
Merge pull request !7670 from linqingke/gpu_ops
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b6b254f6e4
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/**
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* Copyright 2020 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "l2normalize_impl.cuh"
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#include "runtime/device/gpu/cuda_common.h"
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#include "include/cuda_fp16.h"
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template <typename T>
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__global__ void AssignEps(const size_t size, const float eps, T* value) {
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for (size_t pos = blockIdx.x * blockDim.x + threadIdx.x; pos < (size); pos += blockDim.x * gridDim.x) {
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float v = static_cast<float>(value[pos]);
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float max = v > eps ? v : eps;
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value[pos] = static_cast<T>(max);
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}
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return;
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}
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template <typename T>
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void GetMaxWithEpsAndValue(const size_t size, const float eps, T* value, cudaStream_t cuda_stream) {
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AssignEps<<<GET_BLOCKS(size), GET_THREADS, 0, cuda_stream>>>(size, eps, value);
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return;
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}
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template void GetMaxWithEpsAndValue<float>(const size_t size, const float eps, float* value, cudaStream_t cuda_stream);
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template void GetMaxWithEpsAndValue<half>(const size_t size, const float eps, half* value, cudaStream_t cuda_stream);
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template void GetMaxWithEpsAndValue<int>(const size_t size, const float eps, int* value, cudaStream_t cuda_stream);
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/**
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* Copyright 2020 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MINDSPORE_CCSRC_KERNEL_GPU_CUDA_IMP_L2NORMALIZE_H_
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#define MINDSPORE_CCSRC_KERNEL_GPU_CUDA_IMP_L2NORMALIZE_H_
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template <typename T>
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void GetMaxWithEpsAndValue(const size_t size, const float eps, T* value, cudaStream_t cuda_stream);
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#endif // MINDSPORE_CCSRC_KERNEL_GPU_CUDA_IMP_L2NORMALIZE_H_
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/**
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* Copyright 2020 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#include "backend/kernel_compiler/gpu/nn/l2normalize_gpu_kernel.h"
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namespace mindspore {
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namespace kernel {
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MS_REG_GPU_KERNEL_ONE(L2Normalize, KernelAttr().AddInputAttr(kNumberTypeFloat32).AddOutputAttr(kNumberTypeFloat32),
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L2NormalizeGpuKernel, float)
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MS_REG_GPU_KERNEL_ONE(L2Normalize, KernelAttr().AddInputAttr(kNumberTypeFloat16).AddOutputAttr(kNumberTypeFloat16),
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L2NormalizeGpuKernel, half)
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MS_REG_GPU_KERNEL_ONE(L2Normalize, KernelAttr().AddInputAttr(kNumberTypeInt32).AddOutputAttr(kNumberTypeInt32),
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L2NormalizeGpuKernel, int)
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} // namespace kernel
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} // namespace mindspore
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/**
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* Copyright 2020 Huawei Technologies Co., Ltd
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*
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* Licensed under the Apache License, Version 2.0 (the "License");
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* you may not use this file except in compliance with the License.
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* You may obtain a copy of the License at
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*
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* http://www.apache.org/licenses/LICENSE-2.0
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*
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* Unless required by applicable law or agreed to in writing, software
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* distributed under the License is distributed on an "AS IS" BASIS,
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* WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
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* See the License for the specific language governing permissions and
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* limitations under the License.
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*/
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#ifndef MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_L2NORMALIZE_GPU_KERNEL_H_
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#define MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_L2NORMALIZE_GPU_KERNEL_H_
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#include <map>
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#include <string>
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#include <vector>
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#include "backend/kernel_compiler/gpu/gpu_kernel.h"
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#include "backend/kernel_compiler/gpu/gpu_kernel_factory.h"
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#include "backend/kernel_compiler/gpu/cuda_impl/broadcast_impl.cuh"
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#include "backend/kernel_compiler/gpu/cuda_impl/l2normalize_impl.cuh"
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#include "backend/kernel_compiler/gpu/kernel_constants.h"
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namespace mindspore {
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namespace kernel {
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constexpr int MAX_DIMS = 7;
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template <typename T>
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class L2NormalizeGpuKernel : public GpuKernel {
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public:
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L2NormalizeGpuKernel()
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: cudnn_handle_(nullptr),
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data_type_(CUDNN_DATA_FLOAT),
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nan_prop_(CUDNN_NOT_PROPAGATE_NAN),
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reduce_indices_(CUDNN_REDUCE_TENSOR_NO_INDICES),
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reduce_tensor_descriptor_(nullptr),
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inputA_descriptor_(nullptr),
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outputC_descriptor_(nullptr),
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all_match_(false),
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is_null_input_(false),
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input_size_(0),
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output_size_(0),
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workspace_size_(0),
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epsilon_(0.0),
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axis_(0) {}
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~L2NormalizeGpuKernel() override { DestroyResource(); }
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const std::vector<size_t> &GetInputSizeList() const override { return input_size_list_; }
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const std::vector<size_t> &GetOutputSizeList() const override { return output_size_list_; }
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const std::vector<size_t> &GetWorkspaceSizeList() const override { return workspace_size_list_; }
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bool Launch(const std::vector<AddressPtr> &inputs, const std::vector<AddressPtr> &workspace,
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const std::vector<AddressPtr> &outputs, void *stream_ptr) override {
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if (is_null_input_) {
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return true;
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}
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T *input_addr = GetDeviceAddress<T>(inputs, 0);
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T *output_addr = GetDeviceAddress<T>(outputs, 0);
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T *reduce_workspace_addr = GetDeviceAddress<T>(workspace, 0);
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T *workspace_addr = GetDeviceAddress<T>(workspace, 1);
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const float alpha = 1;
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const float beta = 0;
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if (all_match_) {
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CHECK_CUDA_RET_WITH_EXCEPT(cudaMemcpyAsync(reduce_workspace_addr, input_addr, input_size_list_[0],
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cudaMemcpyDeviceToDevice, reinterpret_cast<cudaStream_t>(stream_ptr)),
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"cudaMemcpyAsync failed in L2Normalize::Launch.");
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} else {
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CHECK_CUDNN_RET_WITH_EXCEPT(
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cudnnReduceTensor(cudnn_handle_, reduce_tensor_descriptor_, nullptr, 0, workspace_addr, workspace_size_, &alpha,
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inputA_descriptor_, input_addr, &beta, outputC_descriptor_, reduce_workspace_addr),
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"cudnnReduceTensor failed.");
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}
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GetMaxWithEpsAndValue(workspace_size_list_[0] / sizeof(T), epsilon_, reduce_workspace_addr,
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reinterpret_cast<cudaStream_t>(stream_ptr));
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BroadcastArith(lhs_shape_, rhs_shape_, output_shape_, BROADCAST_TYPE_REALDIV, input_addr, reduce_workspace_addr,
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output_addr, reinterpret_cast<cudaStream_t>(stream_ptr));
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return true;
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}
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bool Init(const CNodePtr &kernel_node) override {
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InitResource();
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data_type_ = GetCudnnDataType(TypeIdLabel(AnfAlgo::GetInputDeviceDataType(kernel_node, 0)));
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size_t input_num = AnfAlgo::GetInputTensorNum(kernel_node);
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if (input_num != 1) {
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MS_LOG(ERROR) << "Input number is " << input_num << ", but l2normalize op needs 1 inputs.";
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return false;
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}
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size_t output_num = AnfAlgo::GetOutputTensorNum(kernel_node);
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if (output_num != 1) {
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MS_LOG(ERROR) << "Output number is " << output_num << ", but l2normalize op needs 1 output.";
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return false;
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}
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int input_dim_length = SizeToInt(AnfAlgo::GetPrevNodeOutputInferShape(kernel_node, 0).size());
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int axis = GetAttr<int>(kernel_node, "axis");
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axis_ = axis < 0 ? (axis + input_dim_length) : axis;
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epsilon_ = GetAttr<float>(kernel_node, "epsilon");
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auto inputA_shape = AnfAlgo::GetPrevNodeOutputInferShape(kernel_node, 0);
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auto output_shape = AnfAlgo::GetOutputInferShape(kernel_node, 0);
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output_size_ = sizeof(T);
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for (auto dim : output_shape) {
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output_size_ *= dim;
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}
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is_null_input_ = CHECK_NULL_INPUT(inputA_shape);
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if (is_null_input_) {
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MS_LOG(WARNING) << "L2NormalizeGPUKernel input is null";
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InitSizeLists();
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return true;
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}
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if (inputA_shape.size() > MAX_DIMS) {
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MS_LOG(EXCEPTION) << "Broadcast operation not support dim greater than 7";
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}
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std::vector<size_t> outputC_shape = output_shape;
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outputC_shape[axis_] = 1;
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if (inputA_shape.size() != output_shape.size() || inputA_shape.size() != outputC_shape.size()) {
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MS_LOG(ERROR) << "Input shape size need equal to output shape size";
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return false;
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}
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lhs_shape_.resize(MAX_DIMS, 1);
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rhs_shape_.resize(MAX_DIMS, 1);
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output_shape_.resize(MAX_DIMS, 1);
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all_match_ = true;
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for (size_t i = 0; i < output_shape.size(); i++) {
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output_shape_[i] = output_shape[i];
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lhs_shape_[i] = inputA_shape[i];
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rhs_shape_[i] = outputC_shape[i];
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if (lhs_shape_[i] != rhs_shape_[i]) {
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all_match_ = false;
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}
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}
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InferInAndOutDesc(inputA_shape, outputC_shape);
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InferArrayReduceType(kernel_node);
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InitSizeLists();
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return true;
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}
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protected:
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void InitResource() override {
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cudnn_handle_ = device::gpu::GPUDeviceManager::GetInstance().GetCudnnHandle();
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CHECK_CUDNN_RET_WITH_EXCEPT(cudnnCreateReduceTensorDescriptor(&reduce_tensor_descriptor_),
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"cudnnCreateReduceTensorDescriptor failed.");
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CHECK_CUDNN_RET_WITH_EXCEPT(cudnnCreateTensorDescriptor(&inputA_descriptor_),
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"cudnnCreateTensorDescriptor failed.");
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CHECK_CUDNN_RET_WITH_EXCEPT(cudnnCreateTensorDescriptor(&outputC_descriptor_),
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"cudnnCreateTensorDescriptor failed.");
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}
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void InitSizeLists() override {
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CHECK_CUDNN_RET_WITH_EXCEPT(cudnnGetTensorSizeInBytes(inputA_descriptor_, &input_size_),
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"cudnnGetTensorSizeInBytes failed.");
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input_size_list_.push_back(input_size_);
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MS_LOG(ERROR) << "input size: " << input_size_;
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output_size_list_.push_back(output_size_);
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MS_LOG(ERROR) << "output size: " << output_size_;
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CHECK_CUDNN_RET_WITH_EXCEPT(cudnnGetTensorSizeInBytes(outputC_descriptor_, &workspace_size_),
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"cudnnGetTensorSizeInBytes failed.");
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workspace_size_list_.push_back(workspace_size_);
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MS_LOG(ERROR) << "workspace_size_1 size: " << workspace_size_;
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CHECK_CUDNN_RET_WITH_EXCEPT(
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cudnnGetReductionWorkspaceSize(cudnn_handle_, reduce_tensor_descriptor_, inputA_descriptor_, outputC_descriptor_,
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&workspace_size_),
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"cudnnGetReductionWorkspaceSize failed.");
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workspace_size_list_.push_back(workspace_size_);
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MS_LOG(ERROR) << "workspace_size_2 size: " << workspace_size_;
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return;
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}
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private:
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void DestroyResource() noexcept {
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CHECK_CUDNN_RET_WITH_ERROR(cudnnDestroyReduceTensorDescriptor(reduce_tensor_descriptor_),
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"cudnnDestroyReduceTensorDescriptor failed.");
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CHECK_CUDNN_RET_WITH_ERROR(cudnnDestroyTensorDescriptor(inputA_descriptor_),
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"cudnnDestroyTensorDescriptor failed.");
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CHECK_CUDNN_RET_WITH_ERROR(cudnnDestroyTensorDescriptor(outputC_descriptor_),
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"cudnnDestroyTensorDescriptor failed.");
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}
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void InferArrayReduceType(const CNodePtr &kernel_node) {
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CHECK_CUDNN_RET_WITH_EXCEPT(
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cudnnSetReduceTensorDescriptor(reduce_tensor_descriptor_, CUDNN_REDUCE_TENSOR_NORM2, CUDNN_DATA_FLOAT, nan_prop_,
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reduce_indices_, CUDNN_32BIT_INDICES),
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"cudnnSetReduceTensorDescriptor failed");
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return;
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}
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void InferInAndOutDesc(const std::vector<size_t> &input_shape, const std::vector<size_t> &output_shape) {
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std::vector<size_t> inputA;
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std::vector<size_t> outputC_shape = output_shape;
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const int split_dim = 4;
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if (input_shape.size() <= split_dim) {
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ShapeNdTo4d(input_shape, &inputA);
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CHECK_CUDNN_RET_WITH_EXCEPT(cudnnSetTensor4dDescriptor(inputA_descriptor_, CUDNN_TENSOR_NCHW, data_type_,
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inputA[0], inputA[1], inputA[2], inputA[3]),
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"cudnnSetTensor4dDescriptor failed");
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} else {
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CudnnSetTensorNdDescriptor(input_shape, inputA_descriptor_, data_type_);
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for (auto dim : input_shape) {
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inputA.emplace_back(dim);
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}
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}
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std::vector<size_t> outputC;
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if (outputC_shape.size() <= split_dim) {
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ShapeNdTo4d(outputC_shape, &outputC);
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CHECK_CUDNN_RET_WITH_EXCEPT(cudnnSetTensor4dDescriptor(outputC_descriptor_, CUDNN_TENSOR_NCHW, data_type_,
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outputC[0], outputC[1], outputC[2], outputC[3]),
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"cudnnSetTensor4dDescriptor failed");
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} else {
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CudnnSetTensorNdDescriptor(outputC_shape, outputC_descriptor_, data_type_);
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for (auto dim : outputC_shape) {
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outputC.emplace_back(dim);
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}
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}
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return;
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}
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cudnnHandle_t cudnn_handle_;
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cudnnDataType_t data_type_;
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cudnnNanPropagation_t nan_prop_;
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cudnnReduceTensorIndices_t reduce_indices_;
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cudnnReduceTensorDescriptor_t reduce_tensor_descriptor_;
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cudnnTensorDescriptor_t inputA_descriptor_;
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cudnnTensorDescriptor_t outputC_descriptor_;
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bool all_match_;
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bool is_null_input_;
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std::vector<size_t> input_size_list_;
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std::vector<size_t> output_size_list_;
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std::vector<size_t> workspace_size_list_;
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size_t input_size_;
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size_t output_size_;
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size_t workspace_size_;
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float epsilon_;
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int axis_;
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std::vector<size_t> lhs_shape_;
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std::vector<size_t> rhs_shape_;
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std::vector<size_t> output_shape_;
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};
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} // namespace kernel
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} // namespace mindspore
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#endif // MINDSPORE_CCSRC_BACKEND_KERNEL_COMPILER_GPU_L2NORMALIZE_GPU_KERNEL_H_
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@ -0,0 +1,47 @@
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# Copyright 2020 Huawei Technologies Co., Ltd
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#
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# Licensed under the Apache License, Version 2.0 (the "License");
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# you may not use this file except in compliance with the License.
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# You may obtain a copy of the License at
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#
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# http://www.apache.org/licenses/LICENSE-2.0
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#
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# Unless required by applicable law or agreed to in writing, software
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# distributed under the License is distributed on an "AS IS" BASIS,
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# WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.
|
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# See the License for the specific language governing permissions and
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# limitations under the License.
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# ============================================================================
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import numpy as np
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import pytest
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import mindspore.context as context
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from mindspore.common.tensor import Tensor
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from mindspore.nn import Cell
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from mindspore.ops import operations as P
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class Net(Cell):
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def __init__(self, axis=0, epsilon=1e-4):
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super(Net, self).__init__()
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self.norm = P.L2Normalize(axis=axis, epsilon=epsilon)
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def construct(self, x):
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return self.norm(x)
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@pytest.mark.level0
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@pytest.mark.platform_x86_gpu_training
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@pytest.mark.env_onecard
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def test_l2normalize():
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x = np.random.randint(1, 10, (2, 3, 4, 4)).astype(np.float32)
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expect = x / np.sqrt(np.sum(x**2, axis=0, keepdims=True))
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x = Tensor(x)
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error = np.ones(shape=[2, 3, 4, 4]) * 1.0e-5
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context.set_context(mode=context.GRAPH_MODE, device_target="GPU")
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norm_op = Net(axis=0)
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output = norm_op(x)
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diff = output.asnumpy() - expect
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assert np.all(diff < error)
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assert np.all(-diff < error)
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