forked from mindspore-Ecosystem/mindspore
add example for reg ops
This commit is contained in:
lianliguang
parent
7ff4909f61
commit
2c836f0dec
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@ -15,10 +15,12 @@
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"""Operators info register."""
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import os
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import json
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import inspect
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import json
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import os
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from mindspore._c_expression import Oplib
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from mindspore._checkparam import Validator as validator
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# path of built-in op info register.
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@ -37,9 +39,32 @@ def op_info_register(op_info):
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Args:
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op_info (str or dict): operator information in json format.
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Examples:
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>>> from mindspore.ops.op_info_register import op_info_register, TBERegOp, DataType
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>>> abs_op_info = TBERegOp("Abs") \
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... .fusion_type("ELEMWISE") \
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... .async_flag(False) \
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... .binfile_name("abs.so") \
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... .compute_cost(10) \
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... .kernel_name("abs") \
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... .partial_flag(True) \
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... .op_pattern("formatAgnostic") \
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... .input(0, "x", None, "required", None) \
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... .output(0, "y", True, "required", "all") \
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... .dtype_format(DataType.F16_None, DataType.F16_None) \
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... .dtype_format(DataType.F32_None, DataType.F32_None) \
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... .dtype_format(DataType.I32_None, DataType.I32_None) \
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... .get_op_info()
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>>>
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>>> @op_info_register(abs_op_info)
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... def _abs_tbe():
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... return
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...
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Returns:
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Function, returns a decorator for op info register.
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"""
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def register_decorator(func):
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if isinstance(op_info, dict):
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op_info_real = json.dumps(op_info)
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@ -58,7 +83,9 @@ def op_info_register(op_info):
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def wrapped_function(*args, **kwargs):
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return func(*args, **kwargs)
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return wrapped_function
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return register_decorator
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@ -329,12 +356,14 @@ class AkgRegOp(RegOp):
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class AkgGpuRegOp(AkgRegOp):
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"""Class for AkgGpu op info register"""
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def __init__(self, op_name):
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super(AkgGpuRegOp, self).__init__(op_name, "CUDA")
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class AkgAscendRegOp(AkgRegOp):
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"""Class for AkgAscend op info register"""
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def __init__(self, op_name):
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super(AkgAscendRegOp, self).__init__(op_name, "AiCore")
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@ -348,7 +377,12 @@ class AiCPURegOp(CpuRegOp):
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class TBERegOp(RegOp):
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"""Class for TBE operator information register."""
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"""
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Class for TBE operator information register.
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Args:
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op_name (string):kernel name.
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"""
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def __init__(self, op_name):
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super(TBERegOp, self).__init__(op_name)
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@ -535,9 +569,169 @@ class TBERegOp(RegOp):
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class DataType:
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"""
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Various combinations of dtype and format.
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Ascend ops various combinations of dtype and format.
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The current list below may be incomplete. Please add it if necessary.
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The current list below may be incomplete.
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Please add it if necessary.
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current support:
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None_None = ("", "")
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None_Default = ("", "DefaultFormat")
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BOOL_None = ("bool", "")
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BOOL_Default = ("bool", "DefaultFormat")
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BOOL_5HD = ("bool", "NC1HWC0")
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BOOL_FracZ = ("bool", "FracZ")
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BOOL_FracNZ = ("bool", "FRACTAL_NZ")
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BOOL_C1HWNCoC0 = ("bool", "C1HWNCoC0")
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BOOL_NCHW = ("bool", "NCHW")
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BOOL_NHWC = ("bool", "NHWC")
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BOOL_HWCN = ("bool", "HWCN")
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BOOL_NDHWC = ("bool", "NDHWC")
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BOOL_ChannelLast = ("bool", "ChannelLast")
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I8_None = ("int8", "")
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I8_Default = ("int8", "DefaultFormat")
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I8_5HD = ("int8", "NC1HWC0")
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I8_FracZ = ("int8", "FracZ")
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I8_FracNZ = ("int8", "FRACTAL_NZ")
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I8_C1HWNCoC0 = ("int8", "C1HWNCoC0")
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I8_NCHW = ("int8", "NCHW")
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I8_NHWC = ("int8", "NHWC")
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I8_HWCN = ("int8", "HWCN")
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I8_NDHWC = ("int8", "NDHWC")
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I8_ChannelLast = ("int8", "ChannelLast")
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U8_None = ("uint8", "")
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U8_Default = ("uint8", "DefaultFormat")
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U8_5HD = ("uint8", "NC1HWC0")
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U8_FracZ = ("uint8", "FracZ")
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U8_FracNZ = ("uint8", "FRACTAL_NZ")
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U8_C1HWNCoC0 = ("uint8", "C1HWNCoC0")
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U8_NCHW = ("uint8", "NCHW")
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U8_NHWC = ("uint8", "NHWC")
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U8_HWCN = ("uint8", "HWCN")
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U8_NDHWC = ("uint8", "NDHWC")
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U8_ChannelLast = ("uint8", "ChannelLast")
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I16_None = ("int16", "")
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I16_Default = ("int16", "DefaultFormat")
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I16_5HD = ("int16", "NC1HWC0")
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I16_FracZ = ("int16", "FracZ")
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I16_FracNZ = ("int16", "FRACTAL_NZ")
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I16_C1HWNCoC0 = ("int16", "C1HWNCoC0")
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I16_NCHW = ("int16", "NCHW")
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I16_NHWC = ("int16", "NHWC")
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I16_HWCN = ("int16", "HWCN")
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I16_NDHWC = ("int16", "NDHWC")
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I16_ChannelLast = ("int16", "ChannelLast")
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U16_None = ("uint16", "")
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U16_Default = ("uint16", "DefaultFormat")
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U16_5HD = ("uint16", "NC1HWC0")
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U16_FracZ = ("uint16", "FracZ")
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U16_FracNZ = ("uint16", "FRACTAL_NZ")
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U16_C1HWNCoC0 = ("uint16", "C1HWNCoC0")
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U16_NCHW = ("uint16", "NCHW")
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U16_NHWC = ("uint16", "NHWC")
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U16_HWCN = ("uint16", "HWCN")
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U16_NDHWC = ("uint16", "NDHWC")
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U16_ChannelLast = ("uint16", "ChannelLast")
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I32_None = ("int32", "")
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I32_Default = ("int32", "DefaultFormat")
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I32_5HD = ("int32", "NC1HWC0")
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I32_FracZ = ("int32", "FracZ")
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I32_FracNZ = ("int32", "FRACTAL_NZ")
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I32_C1HWNCoC0 = ("int32", "C1HWNCoC0")
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I32_NCHW = ("int32", "NCHW")
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I32_NHWC = ("int32", "NHWC")
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I32_HWCN = ("int32", "HWCN")
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I32_NDHWC = ("int32", "NDHWC")
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I32_ChannelLast = ("int32", "ChannelLast")
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U32_None = ("uint32", "")
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U32_Default = ("uint32", "DefaultFormat")
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U32_5HD = ("uint32", "NC1HWC0")
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U32_FracZ = ("uint32", "FracZ")
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U32_FracNZ = ("uint32", "FRACTAL_NZ")
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U32_C1HWNCoC0 = ("uint32", "C1HWNCoC0")
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U32_NCHW = ("uint32", "NCHW")
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U32_NHWC = ("uint32", "NHWC")
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U32_HWCN = ("uint32", "HWCN")
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U32_NDHWC = ("uint32", "NDHWC")
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U32_ChannelLast = ("uint32", "ChannelLast")
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I64_None = ("int64", "")
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I64_Default = ("int64", "DefaultFormat")
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I64_5HD = ("int64", "NC1HWC0")
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I64_FracZ = ("int64", "FracZ")
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I64_FracNZ = ("int64", "FRACTAL_NZ")
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I64_C1HWNCoC0 = ("int64", "C1HWNCoC0")
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I64_NCHW = ("int64", "NCHW")
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I64_NHWC = ("int64", "NHWC")
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I64_HWCN = ("int64", "HWCN")
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I64_NDHWC = ("int64", "NDHWC")
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I64_ChannelLast = ("int64", "ChannelLast")
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U64_None = ("uint64", "")
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U64_Default = ("uint64", "DefaultFormat")
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U64_5HD = ("uint64", "NC1HWC0")
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U64_FracZ = ("uint64", "FracZ")
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U64_FracNZ = ("uint64", "FRACTAL_NZ")
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U64_C1HWNCoC0 = ("uint64", "C1HWNCoC0")
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U64_NCHW = ("uint64", "NCHW")
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U64_NHWC = ("uint64", "NHWC")
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U64_HWCN = ("uint64", "HWCN")
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U64_NDHWC = ("uint64", "NDHWC")
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U64_ChannelLast = ("uint64", "ChannelLast")
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F16_None = ("float16", "")
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F16_Default = ("float16", "DefaultFormat")
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F16_5HD = ("float16", "NC1HWC0")
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F16_FracZ = ("float16", "FracZ")
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F16_FracNZ = ("float16", "FRACTAL_NZ")
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F16_C1HWNCoC0 = ("float16", "C1HWNCoC0")
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F16_NCHW = ("float16", "NCHW")
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F16_NHWC = ("float16", "NHWC")
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F16_HWCN = ("float16", "HWCN")
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F16_NDHWC = ("float16", "NDHWC")
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F16_NCDHW = ("float16", "NCDHW")
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F16_DHWCN = ("float16", "DHWCN")
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F16_NDC1HWC0 = ("float16", "NDC1HWC0")
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F16_FRACTAL_Z_3D = ("float16", "FRACTAL_Z_3D")
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F16_FracZNLSTM = ("float16", "FRACTAL_ZN_LSTM")
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F16_ChannelLast = ("float16", "ChannelLast")
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F32_None = ("float32", "")
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F32_Default = ("float32", "DefaultFormat")
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F32_5HD = ("float32", "NC1HWC0")
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F32_FracZ = ("float32", "FracZ")
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F32_FracNZ = ("float32", "FRACTAL_NZ")
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F32_C1HWNCoC0 = ("float32", "C1HWNCoC0")
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F32_NCHW = ("float32", "NCHW")
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F32_NHWC = ("float32", "NHWC")
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F32_HWCN = ("float32", "HWCN")
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F32_NDHWC = ("float32", "NDHWC")
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F32_NCDHW = ("float32", "NCDHW")
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F32_DHWCN = ("float32", "DHWCN")
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F32_NDC1HWC0 = ("float32", "NDC1HWC0")
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F32_FRACTAL_Z_3D = ("float32", "FRACTAL_Z_3D")
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F32_FracZNLSTM = ("float32", "FRACTAL_ZN_LSTM")
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F32_ChannelLast = ("float32", "ChannelLast")
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F64_None = ("float64", "")
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F64_Default = ("float64", "DefaultFormat")
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F64_5HD = ("float64", "NC1HWC0")
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F64_FracZ = ("float64", "FracZ")
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F64_FracNZ = ("float64", "FRACTAL_NZ")
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F64_C1HWNCoC0 = ("float64", "C1HWNCoC0")
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F64_NCHW = ("float64", "NCHW")
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F64_NHWC = ("float64", "NHWC")
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F64_HWCN = ("float64", "HWCN")
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F64_NDHWC = ("float64", "NDHWC")
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F64_ChannelLast = ("float64", "ChannelLast")
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"""
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None_None = ("", "")
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