forked from OSchip/UnityChipVerification
873 lines
80 KiB
Systemverilog
873 lines
80 KiB
Systemverilog
// Generated by CIRCT firtool-1.61.0
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// Standard header to adapt well known macros for register randomization.
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_MEM_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_MEM_INIT
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`endif // not def RANDOMIZE
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`ifndef RANDOMIZE
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`ifdef RANDOMIZE_REG_INIT
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`define RANDOMIZE
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`endif // RANDOMIZE_REG_INIT
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`endif // not def RANDOMIZE
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// RANDOM may be set to an expression that produces a 32-bit random unsigned value.
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`ifndef RANDOM
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`define RANDOM $random
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`endif // not def RANDOM
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// Users can define INIT_RANDOM as general code that gets injected into the
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// initializer block for modules with registers.
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`ifndef INIT_RANDOM
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`define INIT_RANDOM
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`endif // not def INIT_RANDOM
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// If using random initialization, you can also define RANDOMIZE_DELAY to
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// customize the delay used, otherwise 0.002 is used.
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`ifndef RANDOMIZE_DELAY
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`define RANDOMIZE_DELAY 0.002
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`endif // not def RANDOMIZE_DELAY
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// Define INIT_RANDOM_PROLOG_ for use in our modules below.
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`ifndef INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE
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`ifdef VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM
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`else // VERILATOR
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`define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end
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`endif // VERILATOR
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`else // RANDOMIZE
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`define INIT_RANDOM_PROLOG_
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`endif // RANDOMIZE
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`endif // not def INIT_RANDOM_PROLOG_
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// Include register initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_REG_
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`define ENABLE_INITIAL_REG_
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`endif // not def ENABLE_INITIAL_REG_
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`endif // not def SYNTHESIS
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// Include rmemory initializers in init blocks unless synthesis is set
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`ifndef SYNTHESIS
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`ifndef ENABLE_INITIAL_MEM_
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`define ENABLE_INITIAL_MEM_
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`endif // not def ENABLE_INITIAL_MEM_
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`endif // not def SYNTHESIS
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module RAS( // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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input clock,
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input reset,
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input [35:0] io_reset_vector, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_s0_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_s0_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_s0_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_s0_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [11:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [19:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
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input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s2_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s2_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s2_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s2_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s2_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s2_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_0_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_1_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_2_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [218:0] io_out_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_last_stage_spec_info_ssp, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [1:0] io_out_last_stage_spec_info_sctr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_spec_info_TOSW_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [4:0] io_out_last_stage_spec_info_TOSW_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_spec_info_TOSR_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [4:0] io_out_last_stage_spec_info_TOSR_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_spec_info_NOS_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [4:0] io_out_last_stage_spec_info_NOS_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [38:0] io_out_last_stage_spec_info_topAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output [3:0] io_out_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
output io_out_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_ctrl_ras_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s0_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s0_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s0_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s0_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s1_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s1_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s1_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s1_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s2_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s2_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s2_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s2_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s3_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_s3_redirect_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_cfi_idx_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [3:0] io_update_bits_cfi_idx_bits, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_update_bits_jmp_taken, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [218:0] io_update_bits_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_redirect_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_redirect_bits_level, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [38:0] io_redirect_bits_cfiUpdate_pc, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_redirect_bits_cfiUpdate_pd_isRVC, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_redirect_bits_cfiUpdate_pd_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_redirect_bits_cfiUpdate_pd_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [3:0] io_redirect_bits_cfiUpdate_ssp, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [1:0] io_redirect_bits_cfiUpdate_sctr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_redirect_bits_cfiUpdate_TOSW_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [4:0] io_redirect_bits_cfiUpdate_TOSW_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_redirect_bits_cfiUpdate_TOSR_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [4:0] io_redirect_bits_cfiUpdate_TOSR_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input io_redirect_bits_cfiUpdate_NOS_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
input [4:0] io_redirect_bits_cfiUpdate_NOS_value // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
);
|
|
|
|
wire [38:0] _RASStack_io_spec_pop_addr; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21
|
|
wire [3:0] _RASStack_io_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21
|
|
wire [2:0] _RASStack_io_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21
|
|
wire _RASStack_io_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21
|
|
wire [4:0] _RASStack_io_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21
|
|
wire _RASStack_io_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21
|
|
wire [4:0] _RASStack_io_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21
|
|
wire _RASStack_io_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21
|
|
wire [4:0] _RASStack_io_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21
|
|
wire [35:0] _reset_vector_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23
|
|
reg [38:0] s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86
|
|
reg [38:0] s1_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86
|
|
reg [38:0] s1_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86
|
|
reg [38:0] s1_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86
|
|
reg [38:0] s2_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:187:86
|
|
reg [38:0] s2_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:187:86
|
|
reg [38:0] s2_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:187:86
|
|
reg [38:0] s2_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:187:86
|
|
reg [38:0] s3_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:188:86
|
|
reg [38:0] s3_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:188:86
|
|
reg [38:0] s3_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:188:86
|
|
reg [38:0] s3_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:188:86
|
|
reg REG; // src/main/scala/xiangshan/frontend/BPU.scala:190:24
|
|
reg REG_1; // src/main/scala/xiangshan/frontend/BPU.scala:190:16
|
|
wire [38:0] _s2_spec_new_addr_T_1 =
|
|
39'(io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr
|
|
+ {37'h0, io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, 1'h0}); // src/main/scala/xiangshan/frontend/newRAS.scala:542:55, :637:45
|
|
wire _s2_spec_pop_WIRE_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0
|
|
& io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
wire _s2_spec_pop_T_9 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing
|
|
& io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25
|
|
wire s2_spec_push =
|
|
io_s2_fire_2 & ~(_s2_spec_pop_WIRE_0 & io_in_bits_resp_in_0_s2_full_pred_2_hit)
|
|
& io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1
|
|
& (_s2_spec_pop_T_9 | ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing)
|
|
& io_in_bits_resp_in_0_s2_full_pred_2_hit
|
|
& ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing
|
|
& io_in_bits_resp_in_0_s2_full_pred_2_is_call & ~io_s3_redirect_2; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :511:5, src/main/scala/xiangshan/frontend/newRAS.scala:548:{67,70}
|
|
wire s2_spec_pop =
|
|
io_s2_fire_2 & ~(_s2_spec_pop_WIRE_0 & io_in_bits_resp_in_0_s2_full_pred_2_hit)
|
|
& io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1
|
|
& (_s2_spec_pop_T_9 | ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing)
|
|
& io_in_bits_resp_in_0_s2_full_pred_2_hit
|
|
& ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing
|
|
& io_in_bits_resp_in_0_s2_full_pred_2_is_ret & ~io_s3_redirect_2; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :511:5, src/main/scala/xiangshan/frontend/newRAS.scala:548:70, :549:67
|
|
wire _GEN = io_in_bits_resp_in_0_s2_full_pred_2_is_ret & io_ctrl_ras_enable; // src/main/scala/xiangshan/frontend/newRAS.scala:558:18
|
|
reg [38:0] s3_top; // src/main/scala/xiangshan/frontend/newRAS.scala:574:25
|
|
reg [38:0] s3_spec_new_addr; // src/main/scala/xiangshan/frontend/newRAS.scala:575:35
|
|
wire _GEN_0 = io_in_bits_resp_in_0_s3_full_pred_2_is_ret & io_ctrl_ras_enable; // src/main/scala/xiangshan/frontend/newRAS.scala:583:18
|
|
reg s3_pushed_in_s2; // src/main/scala/xiangshan/frontend/newRAS.scala:592:34
|
|
reg s3_popped_in_s2; // src/main/scala/xiangshan/frontend/newRAS.scala:593:34
|
|
wire _s3_pop_WIRE_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0
|
|
& io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69
|
|
wire _s3_pop_T_9 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing
|
|
& io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25
|
|
wire s3_push =
|
|
~(_s3_pop_WIRE_0 & io_in_bits_resp_in_0_s3_full_pred_2_hit)
|
|
& io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1
|
|
& (_s3_pop_T_9 | ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing)
|
|
& io_in_bits_resp_in_0_s3_full_pred_2_hit
|
|
& ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing
|
|
& io_in_bits_resp_in_0_s3_full_pred_2_is_call; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :511:5, :513:44
|
|
wire s3_pop =
|
|
~(_s3_pop_WIRE_0 & io_in_bits_resp_in_0_s3_full_pred_2_hit)
|
|
& io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1
|
|
& (_s3_pop_T_9 | ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing)
|
|
& io_in_bits_resp_in_0_s3_full_pred_2_hit
|
|
& ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing
|
|
& io_in_bits_resp_in_0_s3_full_pred_2_is_ret; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :511:5, :514:44
|
|
reg [3:0] s3_meta_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26
|
|
reg [2:0] s3_meta_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26
|
|
reg s3_meta_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26
|
|
reg [4:0] s3_meta_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26
|
|
reg s3_meta_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26
|
|
reg [4:0] s3_meta_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26
|
|
reg s3_meta_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26
|
|
reg [4:0] s3_meta_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26
|
|
reg redirect_valid; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
reg redirect_bits_level; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
reg [38:0] redirect_bits_cfiUpdate_pc; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
reg redirect_bits_cfiUpdate_pd_isRVC; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
reg redirect_bits_cfiUpdate_pd_isCall; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
reg redirect_bits_cfiUpdate_pd_isRet; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
reg [3:0] redirect_bits_cfiUpdate_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
reg [1:0] redirect_bits_cfiUpdate_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
reg redirect_bits_cfiUpdate_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
reg [4:0] redirect_bits_cfiUpdate_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
reg redirect_bits_cfiUpdate_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
reg [4:0] redirect_bits_cfiUpdate_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
reg redirect_bits_cfiUpdate_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
reg [4:0] redirect_bits_cfiUpdate_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
wire _GEN_1 =
|
|
io_update_bits_cfi_idx_bits == io_update_bits_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:657:77
|
|
wire [38:0] _GEN_2 = {3'h0, _reset_vector_delay_io_out}; // src/main/scala/xiangshan/frontend/BPU.scala:191:39, utility/src/main/scala/utility/Hold.scala:97:23
|
|
always @(posedge clock) begin
|
|
if (REG_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:190:16
|
|
s1_pc_dup_0 <= _GEN_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39
|
|
s1_pc_dup_1 <= _GEN_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39
|
|
s1_pc_dup_2 <= _GEN_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39
|
|
s1_pc_dup_3 <= _GEN_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39
|
|
end
|
|
else begin // src/main/scala/xiangshan/frontend/BPU.scala:190:16
|
|
if (io_s0_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s1_pc_dup_0 <= io_in_bits_s0_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86
|
|
if (io_s0_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s1_pc_dup_1 <= io_in_bits_s0_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86
|
|
if (io_s0_fire_2) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s1_pc_dup_2 <= io_in_bits_s0_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86
|
|
if (io_s0_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s1_pc_dup_3 <= io_in_bits_s0_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86
|
|
end
|
|
if (io_s1_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s2_pc_dup_0 <= s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86
|
|
if (io_s1_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s2_pc_dup_1 <= s1_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86
|
|
if (io_s1_fire_2) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s2_pc_dup_2 <= s1_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86
|
|
if (io_s1_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s2_pc_dup_3 <= s1_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86
|
|
if (io_s2_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s3_pc_dup_0 <= s2_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86
|
|
if (io_s2_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s3_pc_dup_1 <= s2_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86
|
|
if (io_s2_fire_2) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s3_pc_dup_2 <= s2_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86
|
|
s3_top <= _RASStack_io_spec_pop_addr; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :574:25
|
|
s3_spec_new_addr <= _s2_spec_new_addr_T_1; // src/main/scala/xiangshan/frontend/newRAS.scala:542:55, :575:35
|
|
s3_pushed_in_s2 <= s2_spec_push; // src/main/scala/xiangshan/frontend/newRAS.scala:548:67, :592:34
|
|
s3_popped_in_s2 <= s2_spec_pop; // src/main/scala/xiangshan/frontend/newRAS.scala:549:67, :593:34
|
|
s3_meta_ssp <= _RASStack_io_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26
|
|
s3_meta_sctr <= _RASStack_io_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26
|
|
s3_meta_TOSW_flag <= _RASStack_io_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26
|
|
s3_meta_TOSW_value <= _RASStack_io_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26
|
|
s3_meta_TOSR_flag <= _RASStack_io_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26
|
|
s3_meta_TOSR_value <= _RASStack_io_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26
|
|
s3_meta_NOS_flag <= _RASStack_io_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26
|
|
s3_meta_NOS_value <= _RASStack_io_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26
|
|
end
|
|
if (io_s2_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14
|
|
s3_pc_dup_3 <= s2_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86
|
|
REG <= reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:24
|
|
REG_1 <= REG & ~reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:{16,24,39,42}
|
|
redirect_valid <= io_redirect_valid; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
redirect_bits_level <= io_redirect_bits_level; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
redirect_bits_cfiUpdate_pc <= io_redirect_bits_cfiUpdate_pc; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
redirect_bits_cfiUpdate_pd_isRVC <= io_redirect_bits_cfiUpdate_pd_isRVC; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
redirect_bits_cfiUpdate_pd_isCall <= io_redirect_bits_cfiUpdate_pd_isCall; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
redirect_bits_cfiUpdate_pd_isRet <= io_redirect_bits_cfiUpdate_pd_isRet; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
redirect_bits_cfiUpdate_ssp <= io_redirect_bits_cfiUpdate_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
redirect_bits_cfiUpdate_sctr <= io_redirect_bits_cfiUpdate_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
redirect_bits_cfiUpdate_TOSW_flag <= io_redirect_bits_cfiUpdate_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
redirect_bits_cfiUpdate_TOSW_value <= io_redirect_bits_cfiUpdate_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
redirect_bits_cfiUpdate_TOSR_flag <= io_redirect_bits_cfiUpdate_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
redirect_bits_cfiUpdate_TOSR_value <= io_redirect_bits_cfiUpdate_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
redirect_bits_cfiUpdate_NOS_flag <= io_redirect_bits_cfiUpdate_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
redirect_bits_cfiUpdate_NOS_value <= io_redirect_bits_cfiUpdate_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
end // always @(posedge)
|
|
`ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
`ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
`FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
`endif // FIRRTL_BEFORE_INITIAL
|
|
logic [31:0] _RANDOM[0:20]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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initial begin // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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`ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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`INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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`endif // INIT_RANDOM_PROLOG_
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`ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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for (logic [4:0] i = 5'h0; i < 5'h15; i += 5'h1) begin
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_RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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end // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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s1_pc_dup_0 = {_RANDOM[5'h0], _RANDOM[5'h1][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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s1_pc_dup_1 = {_RANDOM[5'h1][31:7], _RANDOM[5'h2][13:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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s1_pc_dup_2 = {_RANDOM[5'h2][31:14], _RANDOM[5'h3][20:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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s1_pc_dup_3 = {_RANDOM[5'h3][31:21], _RANDOM[5'h4][27:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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s2_pc_dup_0 = {_RANDOM[5'h4][31:28], _RANDOM[5'h5], _RANDOM[5'h6][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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s2_pc_dup_1 = {_RANDOM[5'h6][31:3], _RANDOM[5'h7][9:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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s2_pc_dup_2 = {_RANDOM[5'h7][31:10], _RANDOM[5'h8][16:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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s2_pc_dup_3 = {_RANDOM[5'h8][31:17], _RANDOM[5'h9][23:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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s3_pc_dup_0 = {_RANDOM[5'h9][31:24], _RANDOM[5'hA][30:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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s3_pc_dup_1 = {_RANDOM[5'hA][31], _RANDOM[5'hB], _RANDOM[5'hC][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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s3_pc_dup_2 = {_RANDOM[5'hC][31:6], _RANDOM[5'hD][12:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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s3_pc_dup_3 = {_RANDOM[5'hD][31:13], _RANDOM[5'hE][19:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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REG = _RANDOM[5'hE][20]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, :190:24, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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REG_1 = _RANDOM[5'hE][21]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, :190:16, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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|
s3_top = {_RANDOM[5'hE][31:22], _RANDOM[5'hF][28:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25
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|
s3_spec_new_addr = {_RANDOM[5'hF][31:29], _RANDOM[5'h10], _RANDOM[5'h11][3:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :575:35
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s3_pushed_in_s2 = _RANDOM[5'h11][4]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :592:34
|
|
s3_popped_in_s2 = _RANDOM[5'h11][5]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :593:34
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|
s3_meta_ssp = _RANDOM[5'h11][9:6]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26
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s3_meta_sctr = _RANDOM[5'h11][12:10]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26
|
|
s3_meta_TOSW_flag = _RANDOM[5'h11][13]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26
|
|
s3_meta_TOSW_value = _RANDOM[5'h11][18:14]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26
|
|
s3_meta_TOSR_flag = _RANDOM[5'h11][19]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26
|
|
s3_meta_TOSR_value = _RANDOM[5'h11][24:20]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26
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|
s3_meta_NOS_flag = _RANDOM[5'h11][25]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26
|
|
s3_meta_NOS_value = _RANDOM[5'h11][30:26]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26
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|
redirect_valid = _RANDOM[5'h11][31]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :621:25
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|
redirect_bits_level = _RANDOM[5'h12][21]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25
|
|
redirect_bits_cfiUpdate_pc = {_RANDOM[5'h12][31:23], _RANDOM[5'h13][29:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25
|
|
redirect_bits_cfiUpdate_pd_isRVC = _RANDOM[5'h13][31]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25
|
|
redirect_bits_cfiUpdate_pd_isCall = _RANDOM[5'h14][2]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25
|
|
redirect_bits_cfiUpdate_pd_isRet = _RANDOM[5'h14][3]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25
|
|
redirect_bits_cfiUpdate_ssp = _RANDOM[5'h14][7:4]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25
|
|
redirect_bits_cfiUpdate_sctr = _RANDOM[5'h14][9:8]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25
|
|
redirect_bits_cfiUpdate_TOSW_flag = _RANDOM[5'h14][10]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25
|
|
redirect_bits_cfiUpdate_TOSW_value = _RANDOM[5'h14][15:11]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25
|
|
redirect_bits_cfiUpdate_TOSR_flag = _RANDOM[5'h14][16]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25
|
|
redirect_bits_cfiUpdate_TOSR_value = _RANDOM[5'h14][21:17]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25
|
|
redirect_bits_cfiUpdate_NOS_flag = _RANDOM[5'h14][22]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25
|
|
redirect_bits_cfiUpdate_NOS_value = _RANDOM[5'h14][27:23]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25
|
|
`endif // RANDOMIZE_REG_INIT
|
|
end // initial
|
|
`ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
`FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
`endif // FIRRTL_AFTER_INITIAL
|
|
`endif // ENABLE_INITIAL_REG_
|
|
DelayN_2 reset_vector_delay ( // utility/src/main/scala/utility/Hold.scala:97:23
|
|
.clock (clock),
|
|
.io_in (io_reset_vector),
|
|
.io_out (_reset_vector_delay_io_out)
|
|
);
|
|
RASStack RASStack ( // src/main/scala/xiangshan/frontend/newRAS.scala:536:21
|
|
.clock (clock),
|
|
.reset (reset),
|
|
.io_spec_push_valid (s2_spec_push), // src/main/scala/xiangshan/frontend/newRAS.scala:548:67
|
|
.io_spec_pop_valid (s2_spec_pop), // src/main/scala/xiangshan/frontend/newRAS.scala:549:67
|
|
.io_spec_push_addr (_s2_spec_new_addr_T_1), // src/main/scala/xiangshan/frontend/newRAS.scala:542:55
|
|
.io_s2_fire (io_s2_fire_2),
|
|
.io_s3_fire (io_s3_fire_2),
|
|
.io_s3_cancel
|
|
(io_s3_fire_2 & (s3_pushed_in_s2 != s3_push | s3_popped_in_s2 != s3_pop)), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:513:44, :514:44, src/main/scala/xiangshan/frontend/newRAS.scala:592:34, :593:34, :597:{33,53,65,84}
|
|
.io_s3_meta_ssp (s3_meta_ssp), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26
|
|
.io_s3_meta_sctr (s3_meta_sctr), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26
|
|
.io_s3_meta_TOSW_flag (s3_meta_TOSW_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26
|
|
.io_s3_meta_TOSW_value (s3_meta_TOSW_value), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26
|
|
.io_s3_meta_TOSR_flag (s3_meta_TOSR_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26
|
|
.io_s3_meta_TOSR_value (s3_meta_TOSR_value), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26
|
|
.io_s3_meta_NOS_flag (s3_meta_NOS_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26
|
|
.io_s3_meta_NOS_value (s3_meta_NOS_value), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26
|
|
.io_s3_missed_pop (s3_pop & ~s3_popped_in_s2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:514:44, src/main/scala/xiangshan/frontend/newRAS.scala:593:34, :606:{33,36}
|
|
.io_s3_missed_push (s3_push & ~s3_pushed_in_s2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:513:44, src/main/scala/xiangshan/frontend/newRAS.scala:592:34, :607:{35,38}
|
|
.io_s3_pushAddr (s3_spec_new_addr), // src/main/scala/xiangshan/frontend/newRAS.scala:575:35
|
|
.io_spec_pop_addr (_RASStack_io_spec_pop_addr),
|
|
.io_commit_push_valid
|
|
(io_update_valid & io_update_bits_ftb_entry_tailSlot_valid
|
|
& io_update_bits_ftb_entry_isCall & io_update_bits_jmp_taken
|
|
& io_update_bits_cfi_idx_valid & _GEN_1), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:657:77, src/main/scala/xiangshan/frontend/newRAS.scala:643:42
|
|
.io_commit_pop_valid
|
|
(io_update_valid & io_update_bits_ftb_entry_tailSlot_valid
|
|
& io_update_bits_ftb_entry_isRet & io_update_bits_jmp_taken
|
|
& io_update_bits_cfi_idx_valid & _GEN_1), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:657:77, src/main/scala/xiangshan/frontend/newRAS.scala:644:41
|
|
.io_commit_meta_TOSW_flag (io_update_bits_meta[17]), // src/main/scala/xiangshan/frontend/newRAS.scala:640:48
|
|
.io_commit_meta_TOSW_value (io_update_bits_meta[16:12]), // src/main/scala/xiangshan/frontend/newRAS.scala:640:48
|
|
.io_commit_meta_ssp (io_update_bits_meta[24:21]), // src/main/scala/xiangshan/frontend/newRAS.scala:640:48
|
|
.io_redirect_valid (redirect_valid), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
.io_redirect_isCall
|
|
(redirect_valid & ~redirect_bits_level & redirect_bits_cfiUpdate_pd_isCall), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25, :625:56, :626:64
|
|
.io_redirect_isRet
|
|
(redirect_valid & ~redirect_bits_level & redirect_bits_cfiUpdate_pd_isRet), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25, :625:{56,64}
|
|
.io_redirect_meta_ssp (redirect_bits_cfiUpdate_ssp), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
.io_redirect_meta_sctr ({1'h0, redirect_bits_cfiUpdate_sctr}), // src/main/scala/xiangshan/frontend/newRAS.scala:542:55, :621:25, :633:28
|
|
.io_redirect_meta_TOSW_flag (redirect_bits_cfiUpdate_TOSW_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
.io_redirect_meta_TOSW_value (redirect_bits_cfiUpdate_TOSW_value), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
.io_redirect_meta_TOSR_flag (redirect_bits_cfiUpdate_TOSR_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
.io_redirect_meta_TOSR_value (redirect_bits_cfiUpdate_TOSR_value), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
.io_redirect_meta_NOS_flag (redirect_bits_cfiUpdate_NOS_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
.io_redirect_meta_NOS_value (redirect_bits_cfiUpdate_NOS_value), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25
|
|
.io_redirect_callAddr
|
|
(39'(redirect_bits_cfiUpdate_pc
|
|
+ {36'h0, redirect_bits_cfiUpdate_pd_isRVC ? 3'h2 : 3'h4})), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25, :637:{45,50}
|
|
.io_ssp (_RASStack_io_ssp),
|
|
.io_sctr (_RASStack_io_sctr),
|
|
.io_TOSR_flag (_RASStack_io_TOSR_flag),
|
|
.io_TOSR_value (_RASStack_io_TOSR_value),
|
|
.io_TOSW_flag (_RASStack_io_TOSW_flag),
|
|
.io_TOSW_value (_RASStack_io_TOSW_value),
|
|
.io_NOS_flag (_RASStack_io_NOS_flag),
|
|
.io_NOS_value (_RASStack_io_NOS_value)
|
|
);
|
|
assign io_out_s2_pc_0 = s2_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_pc_1 = s2_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_pc_2 = s2_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_pc_3 = s2_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_0_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_0_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_0_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_0_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_0_targets_0 = io_in_bits_resp_in_0_s2_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_0_targets_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_is_jalr
|
|
? (_GEN
|
|
? _RASStack_io_spec_pop_addr
|
|
: io_in_bits_resp_in_0_s2_full_pred_0_jalr_target)
|
|
: io_in_bits_resp_in_0_s2_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :536:21, :558:{18,41}, :559:54, :564:26
|
|
assign io_out_s2_full_pred_0_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_0_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_0_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_0_is_br_sharing =
|
|
io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_0_hit = io_in_bits_resp_in_0_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_1_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_1_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_1_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_1_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_1_targets_0 = io_in_bits_resp_in_0_s2_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_1_targets_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_is_jalr
|
|
? (_GEN
|
|
? _RASStack_io_spec_pop_addr
|
|
: io_in_bits_resp_in_0_s2_full_pred_1_jalr_target)
|
|
: io_in_bits_resp_in_0_s2_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :536:21, :558:{18,41}, :559:54, :564:26
|
|
assign io_out_s2_full_pred_1_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_1_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_1_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_1_is_br_sharing =
|
|
io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_1_hit = io_in_bits_resp_in_0_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_2_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_2_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_2_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_2_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_2_targets_0 = io_in_bits_resp_in_0_s2_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_2_targets_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_is_jalr
|
|
? (_GEN
|
|
? _RASStack_io_spec_pop_addr
|
|
: io_in_bits_resp_in_0_s2_full_pred_2_jalr_target)
|
|
: io_in_bits_resp_in_0_s2_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :536:21, :558:{18,41}, :559:54, :564:26
|
|
assign io_out_s2_full_pred_2_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_2_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_2_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_2_is_br_sharing =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_2_hit = io_in_bits_resp_in_0_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_3_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_3_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_3_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_3_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_3_targets_0 = io_in_bits_resp_in_0_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_3_targets_1 =
|
|
io_in_bits_resp_in_0_s2_full_pred_2_is_jalr
|
|
? (_GEN
|
|
? _RASStack_io_spec_pop_addr
|
|
: io_in_bits_resp_in_0_s2_full_pred_3_jalr_target)
|
|
: io_in_bits_resp_in_0_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :536:21, :558:{18,41}, :559:54, :564:26
|
|
assign io_out_s2_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_3_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_3_fallThroughErr =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_3_is_br_sharing =
|
|
io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s2_full_pred_3_hit = io_in_bits_resp_in_0_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_pc_0 = s3_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_pc_1 = s3_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_pc_2 = s3_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_pc_3 = s3_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_0_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_0_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_0_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_0_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_0_targets_0 = io_in_bits_resp_in_0_s3_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_0_targets_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_is_jalr
|
|
? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_0_jalr_target)
|
|
: io_in_bits_resp_in_0_s3_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :583:{18,41}, :584:54, :589:26
|
|
assign io_out_s3_full_pred_0_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_0_fallThroughErr =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_0_is_br_sharing =
|
|
io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_0_hit = io_in_bits_resp_in_0_s3_full_pred_0_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_1_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_1_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_1_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_1_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_1_targets_0 = io_in_bits_resp_in_0_s3_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_1_targets_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_is_jalr
|
|
? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_1_jalr_target)
|
|
: io_in_bits_resp_in_0_s3_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :583:{18,41}, :584:54, :589:26
|
|
assign io_out_s3_full_pred_1_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_1_fallThroughErr =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_1_is_br_sharing =
|
|
io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_1_hit = io_in_bits_resp_in_0_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_2_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_2_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_2_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_2_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_2_targets_0 = io_in_bits_resp_in_0_s3_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_2_targets_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_is_jalr
|
|
? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_2_jalr_target)
|
|
: io_in_bits_resp_in_0_s3_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :583:{18,41}, :584:54, :589:26
|
|
assign io_out_s3_full_pred_2_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_2_fallThroughErr =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_2_is_br_sharing =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_2_hit = io_in_bits_resp_in_0_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_3_br_taken_mask_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_3_br_taken_mask_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_3_slot_valids_0 =
|
|
io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_3_slot_valids_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_3_targets_0 = io_in_bits_resp_in_0_s3_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_3_targets_1 =
|
|
io_in_bits_resp_in_0_s3_full_pred_2_is_jalr
|
|
? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_3_jalr_target)
|
|
: io_in_bits_resp_in_0_s3_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :583:{18,41}, :584:54, :589:26
|
|
assign io_out_s3_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_3_fallThroughAddr =
|
|
io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_3_fallThroughErr =
|
|
io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_3_is_br_sharing =
|
|
io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_s3_full_pred_3_hit = io_in_bits_resp_in_0_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_last_stage_meta =
|
|
{194'h0,
|
|
s3_meta_ssp,
|
|
s3_meta_sctr,
|
|
s3_meta_TOSW_flag,
|
|
s3_meta_TOSW_value,
|
|
s3_meta_TOSR_flag,
|
|
s3_meta_TOSR_value,
|
|
s3_meta_NOS_flag,
|
|
s3_meta_NOS_value}; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26, :618:26
|
|
assign io_out_last_stage_spec_info_ssp = s3_meta_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26
|
|
assign io_out_last_stage_spec_info_sctr = s3_meta_sctr[1:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26, :612:37
|
|
assign io_out_last_stage_spec_info_TOSW_flag = s3_meta_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26
|
|
assign io_out_last_stage_spec_info_TOSW_value = s3_meta_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26
|
|
assign io_out_last_stage_spec_info_TOSR_flag = s3_meta_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26
|
|
assign io_out_last_stage_spec_info_TOSR_value = s3_meta_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26
|
|
assign io_out_last_stage_spec_info_NOS_flag = s3_meta_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26
|
|
assign io_out_last_stage_spec_info_NOS_value = s3_meta_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26
|
|
assign io_out_last_stage_spec_info_topAddr = s3_top; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25
|
|
assign io_out_last_stage_ftb_entry_valid =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_valid; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_last_stage_ftb_entry_brSlots_0_offset =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_last_stage_ftb_entry_brSlots_0_lower =
|
|
io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
|
|
assign io_out_last_stage_ftb_entry_brSlots_0_tarStat =
|
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io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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assign io_out_last_stage_ftb_entry_brSlots_0_sharing =
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io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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assign io_out_last_stage_ftb_entry_brSlots_0_valid =
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io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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assign io_out_last_stage_ftb_entry_tailSlot_offset =
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io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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assign io_out_last_stage_ftb_entry_tailSlot_lower =
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io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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assign io_out_last_stage_ftb_entry_tailSlot_tarStat =
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io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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assign io_out_last_stage_ftb_entry_tailSlot_sharing =
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io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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assign io_out_last_stage_ftb_entry_tailSlot_valid =
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io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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assign io_out_last_stage_ftb_entry_pftAddr =
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io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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assign io_out_last_stage_ftb_entry_carry =
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io_in_bits_resp_in_0_last_stage_ftb_entry_carry; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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assign io_out_last_stage_ftb_entry_isCall =
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io_in_bits_resp_in_0_last_stage_ftb_entry_isCall; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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assign io_out_last_stage_ftb_entry_isRet =
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io_in_bits_resp_in_0_last_stage_ftb_entry_isRet; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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assign io_out_last_stage_ftb_entry_isJalr =
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io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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assign io_out_last_stage_ftb_entry_last_may_be_rvi_call =
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io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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assign io_out_last_stage_ftb_entry_always_taken_0 =
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io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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assign io_out_last_stage_ftb_entry_always_taken_1 =
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io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7
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endmodule
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