diff --git a/Makefile b/Makefile index c72e6b5..0dd5c94 100644 --- a/Makefile +++ b/Makefile @@ -1,4 +1,4 @@ -export LANG ?= python +export TL ?= python export WAVE ?= true export VERBOSE ?= false export EXAMPLE ?= false @@ -9,17 +9,19 @@ export TARGET default: echo "TODO" +uftb: + make -f ./mk/uFTB.mk uftb tage_sc: make -f ./mk/Tage.mk tage_sc -uftb: - make -f ./mk/uFTB.mk uftb - ftb: make -f ./mk/FTB.mk ftb +ras: + make -f ./mk/RAS.mk ras + filter: cat log|grep Cannot |awk '{print $8}'| sort| uniq|tr -d "'" -all: tage_sc uftb ftb +all: uftb tage_sc ftb ras diff --git a/Readme.md b/Readme.md index ce82fde..43fe950 100644 --- a/Readme.md +++ b/Readme.md @@ -15,7 +15,7 @@ Install the following tools before running the testcases. ### uFTB ```bash -make uftb LANG=python +make uftb TL=python ``` Then you will see the following files in the `out` directory. The whole directory is the python module of uFTB of XiangShan. @@ -61,11 +61,11 @@ The other modules such as Tage_SC are similar to uFTB. You can import them in th ### Tage SC ```bash -make tage_sc LANG=python +make tage_sc TL=python ``` ### FTB ```bash -make ftb LANG=python +make ftb TL=python ``` \ No newline at end of file diff --git a/mk/FTB.mk b/mk/FTB.mk index 309fa57..802bc6f 100644 --- a/mk/FTB.mk +++ b/mk/FTB.mk @@ -1,6 +1,6 @@ TOP_ENTRY := ./src/FTB/FTB.sv TOP_FILES := ./src/FTB.txt -LANG ?= cpp +TL ?= cpp ifneq ($(TARGET),) TARGET := $(TARGET) @@ -30,7 +30,7 @@ _WAVEFORM ?= ftb: @echo "Building tage module with parameters: " - @echo "LANG=${LANG}" + @echo "TL=${TL}" @echo "TOP_ENTRY=${TOP_ENTRY}" @echo "TOP_FILES=${TOP_FILES}" @echo "TARGET=${TARGET}" @@ -40,7 +40,7 @@ ftb: @mkdir -p out rm -rf ${TARGET} - picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${LANG} \ + picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${TL} \ -t ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE} cd ${TARGET} && make diff --git a/mk/RAS.mk b/mk/RAS.mk new file mode 100644 index 0000000..0248d25 --- /dev/null +++ b/mk/RAS.mk @@ -0,0 +1,47 @@ +TOP_ENTRY := ./src/RAS/RAS.sv +TOP_FILES := ./src/RAS.txt +TL ?= cpp + +ifneq ($(TARGET),) + TARGET := $(TARGET) +else + TARGET := out/picker_out_RAS +endif + +# if EXAMPLE is set, then _EXAMPLE is set to -e +ifneq ($(EXAMPLE), false) + _EXAMPLE := -e +endif +_EXAMPLE ?= +# if VERBOSE is set, then _VERBOSE is set to -v +ifneq ($(VERBOSE), false) + _VERBOSE := -v +endif +_VERBOSE ?= +# if WAVE is set, then _WAVEFORM is set to -w +ifneq ($(WAVE), false) + ifneq ($(WAVE), true) + _WAVEFORM := -w $(WAVE) + else + _WAVEFORM := -w RAS.fst + endif +endif +_WAVEFORM ?= + +ras: + @echo "Building tage module with parameters: " + @echo "TL=${TL}" + @echo "TOP_ENTRY=${TOP_ENTRY}" + @echo "TOP_FILES=${TOP_FILES}" + @echo "TARGET=${TARGET}" + @echo "WAVEFORM=${_WAVEFORM}" + @echo "VERBOSE=${_VERBOSE}" + @echo "EXAMPLE=${_EXAMPLE}" + + @mkdir -p out + rm -rf ${TARGET} + picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${TL} \ + -t ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE} + + cd ${TARGET} && make + diff --git a/mk/Tage.mk b/mk/Tage.mk index 27c45ca..d674ed1 100644 --- a/mk/Tage.mk +++ b/mk/Tage.mk @@ -1,6 +1,6 @@ TOP_ENTRY := ./src/TageSC/Tage_SC.sv TOP_FILES := ./src/Tage_SC.txt -LANG ?= cpp +TL ?= cpp ifneq ($(TARGET),) TARGET := $(TARGET) @@ -30,7 +30,7 @@ _WAVEFORM ?= tage_sc: @echo "Building tage module with parameters: " - @echo "LANG=${LANG}" + @echo "TL=${TL}" @echo "TOP_ENTRY=${TOP_ENTRY}" @echo "TOP_FILES=${TOP_FILES}" @echo "TARGET=${TARGET}" @@ -40,7 +40,7 @@ tage_sc: @mkdir -p out rm -rf ${TARGET} - picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${LANG} \ + picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${TL} \ -t ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE} cd ${TARGET} && make diff --git a/mk/uFTB.mk b/mk/uFTB.mk index 5fe02a7..77f8173 100644 --- a/mk/uFTB.mk +++ b/mk/uFTB.mk @@ -1,6 +1,6 @@ TOP_ENTRY := ./src/uFTB/FauFTB.sv TOP_FILES := ./src/uFTB.txt -LANG ?= cpp +TL ?= cpp ifneq ($(TARGET),) TARGET := $(TARGET) @@ -30,7 +30,7 @@ _WAVEFORM ?= uftb: @echo "Building tage module with parameters: " - @echo "LANG=${LANG}" + @echo "TL=${TL}" @echo "TOP_ENTRY=${TOP_ENTRY}" @echo "TOP_FILES=${TOP_FILES}" @echo "TARGET=${TARGET}" @@ -40,7 +40,7 @@ uftb: @mkdir -p out rm -rf ${TARGET} - picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${LANG} \ + picker ${TOP_ENTRY} -f ${TOP_FILES} -l ${TL} \ -t ${TARGET} ${_WAVEFORM}${_EXAMPLE} ${_VERBOSE} cd ${TARGET} && make diff --git a/src/RAS.txt b/src/RAS.txt new file mode 100644 index 0000000..a162349 --- /dev/null +++ b/src/RAS.txt @@ -0,0 +1,3 @@ +./src/RAS/RASStack.sv +./src/common/ext_sram.v +./src/common/DelayN_2.sv \ No newline at end of file diff --git a/src/RAS/RAS.sv b/src/RAS/RAS.sv new file mode 100644 index 0000000..6235572 --- /dev/null +++ b/src/RAS/RAS.sv @@ -0,0 +1,872 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module RAS( // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + input clock, + input reset, + input [35:0] io_reset_vector, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_s0_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s2_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s2_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s2_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_is_jalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_is_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_is_ret, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_jalr_target, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [11:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [19:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [1:0] io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_0_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_0_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_1_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_1_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_2_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_2_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s2_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s2_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s2_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_pc_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_pc_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_pc_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_pc_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_0_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_0_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_0_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_0_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_1_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_1_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_1_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_1_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_2_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_2_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_2_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_2_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_br_taken_mask_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_br_taken_mask_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_slot_valids_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_slot_valids_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_3_targets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_3_targets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s3_full_pred_3_offsets_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_s3_full_pred_3_offsets_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_s3_full_pred_3_fallThroughAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_fallThroughErr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_is_br_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_s3_full_pred_3_hit, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [218:0] io_out_last_stage_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_last_stage_spec_info_ssp, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [1:0] io_out_last_stage_spec_info_sctr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_spec_info_TOSW_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [4:0] io_out_last_stage_spec_info_TOSW_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_spec_info_TOSR_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [4:0] io_out_last_stage_spec_info_TOSR_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_spec_info_NOS_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [4:0] io_out_last_stage_spec_info_NOS_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [38:0] io_out_last_stage_spec_info_topAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_last_stage_ftb_entry_brSlots_0_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [11:0] io_out_last_stage_ftb_entry_brSlots_0_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [1:0] io_out_last_stage_ftb_entry_brSlots_0_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_brSlots_0_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_brSlots_0_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_last_stage_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [19:0] io_out_last_stage_ftb_entry_tailSlot_lower, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [1:0] io_out_last_stage_ftb_entry_tailSlot_tarStat, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_tailSlot_sharing, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output [3:0] io_out_last_stage_ftb_entry_pftAddr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_carry, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_isJalr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_last_may_be_rvi_call, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_always_taken_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + output io_out_last_stage_ftb_entry_always_taken_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_ctrl_ras_enable, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s0_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s1_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_0, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_1, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s2_fire_3, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s3_fire_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_s3_redirect_2, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_update_bits_ftb_entry_tailSlot_offset, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_tailSlot_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_ftb_entry_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_cfi_idx_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_update_bits_cfi_idx_bits, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_update_bits_jmp_taken, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [218:0] io_update_bits_meta, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_redirect_valid, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_redirect_bits_level, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [38:0] io_redirect_bits_cfiUpdate_pc, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_redirect_bits_cfiUpdate_pd_isRVC, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_redirect_bits_cfiUpdate_pd_isCall, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_redirect_bits_cfiUpdate_pd_isRet, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [3:0] io_redirect_bits_cfiUpdate_ssp, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [1:0] io_redirect_bits_cfiUpdate_sctr, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_redirect_bits_cfiUpdate_TOSW_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [4:0] io_redirect_bits_cfiUpdate_TOSW_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_redirect_bits_cfiUpdate_TOSR_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [4:0] io_redirect_bits_cfiUpdate_TOSR_value, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input io_redirect_bits_cfiUpdate_NOS_flag, // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + input [4:0] io_redirect_bits_cfiUpdate_NOS_value // src/main/scala/xiangshan/frontend/BPU.scala:171:14 +); + + wire [38:0] _RASStack_io_spec_pop_addr; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 + wire [3:0] _RASStack_io_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 + wire [2:0] _RASStack_io_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 + wire _RASStack_io_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 + wire [4:0] _RASStack_io_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 + wire _RASStack_io_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 + wire [4:0] _RASStack_io_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 + wire _RASStack_io_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 + wire [4:0] _RASStack_io_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 + wire [35:0] _reset_vector_delay_io_out; // utility/src/main/scala/utility/Hold.scala:97:23 + reg [38:0] s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + reg [38:0] s1_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + reg [38:0] s1_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + reg [38:0] s1_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + reg [38:0] s2_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:187:86 + reg [38:0] s2_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:187:86 + reg [38:0] s2_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:187:86 + reg [38:0] s2_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:187:86 + reg [38:0] s3_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:188:86 + reg [38:0] s3_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:188:86 + reg [38:0] s3_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:188:86 + reg [38:0] s3_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:188:86 + reg REG; // src/main/scala/xiangshan/frontend/BPU.scala:190:24 + reg REG_1; // src/main/scala/xiangshan/frontend/BPU.scala:190:16 + wire [38:0] _s2_spec_new_addr_T_1 = + 39'(io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr + + {37'h0, io_in_bits_resp_in_0_s2_full_pred_2_last_may_be_rvi_call, 1'h0}); // src/main/scala/xiangshan/frontend/newRAS.scala:542:55, :637:45 + wire _s2_spec_pop_WIRE_0 = + io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0 + & io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _s2_spec_pop_T_9 = + io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing + & io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + wire s2_spec_push = + io_s2_fire_2 & ~(_s2_spec_pop_WIRE_0 & io_in_bits_resp_in_0_s2_full_pred_2_hit) + & io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1 + & (_s2_spec_pop_T_9 | ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing) + & io_in_bits_resp_in_0_s2_full_pred_2_hit + & ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing + & io_in_bits_resp_in_0_s2_full_pred_2_is_call & ~io_s3_redirect_2; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :511:5, src/main/scala/xiangshan/frontend/newRAS.scala:548:{67,70} + wire s2_spec_pop = + io_s2_fire_2 & ~(_s2_spec_pop_WIRE_0 & io_in_bits_resp_in_0_s2_full_pred_2_hit) + & io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1 + & (_s2_spec_pop_T_9 | ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing) + & io_in_bits_resp_in_0_s2_full_pred_2_hit + & ~io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing + & io_in_bits_resp_in_0_s2_full_pred_2_is_ret & ~io_s3_redirect_2; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :511:5, src/main/scala/xiangshan/frontend/newRAS.scala:548:70, :549:67 + wire _GEN = io_in_bits_resp_in_0_s2_full_pred_2_is_ret & io_ctrl_ras_enable; // src/main/scala/xiangshan/frontend/newRAS.scala:558:18 + reg [38:0] s3_top; // src/main/scala/xiangshan/frontend/newRAS.scala:574:25 + reg [38:0] s3_spec_new_addr; // src/main/scala/xiangshan/frontend/newRAS.scala:575:35 + wire _GEN_0 = io_in_bits_resp_in_0_s3_full_pred_2_is_ret & io_ctrl_ras_enable; // src/main/scala/xiangshan/frontend/newRAS.scala:583:18 + reg s3_pushed_in_s2; // src/main/scala/xiangshan/frontend/newRAS.scala:592:34 + reg s3_popped_in_s2; // src/main/scala/xiangshan/frontend/newRAS.scala:593:34 + wire _s3_pop_WIRE_0 = + io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0 + & io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69 + wire _s3_pop_T_9 = + io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing + & io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:460:25 + wire s3_push = + ~(_s3_pop_WIRE_0 & io_in_bits_resp_in_0_s3_full_pred_2_hit) + & io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1 + & (_s3_pop_T_9 | ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing) + & io_in_bits_resp_in_0_s3_full_pred_2_hit + & ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing + & io_in_bits_resp_in_0_s3_full_pred_2_is_call; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :511:5, :513:44 + wire s3_pop = + ~(_s3_pop_WIRE_0 & io_in_bits_resp_in_0_s3_full_pred_2_hit) + & io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1 + & (_s3_pop_T_9 | ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing) + & io_in_bits_resp_in_0_s3_full_pred_2_hit + & ~io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing + & io_in_bits_resp_in_0_s3_full_pred_2_is_ret; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:458:69, :460:{25,47,50}, :467:38, :511:5, :514:44 + reg [3:0] s3_meta_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 + reg [2:0] s3_meta_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 + reg s3_meta_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 + reg [4:0] s3_meta_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 + reg s3_meta_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 + reg [4:0] s3_meta_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 + reg s3_meta_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 + reg [4:0] s3_meta_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 + reg redirect_valid; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + reg redirect_bits_level; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + reg [38:0] redirect_bits_cfiUpdate_pc; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + reg redirect_bits_cfiUpdate_pd_isRVC; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + reg redirect_bits_cfiUpdate_pd_isCall; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + reg redirect_bits_cfiUpdate_pd_isRet; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + reg [3:0] redirect_bits_cfiUpdate_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + reg [1:0] redirect_bits_cfiUpdate_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + reg redirect_bits_cfiUpdate_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + reg [4:0] redirect_bits_cfiUpdate_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + reg redirect_bits_cfiUpdate_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + reg [4:0] redirect_bits_cfiUpdate_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + reg redirect_bits_cfiUpdate_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + reg [4:0] redirect_bits_cfiUpdate_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + wire _GEN_1 = + io_update_bits_cfi_idx_bits == io_update_bits_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/FrontendBundle.scala:657:77 + wire [38:0] _GEN_2 = {3'h0, _reset_vector_delay_io_out}; // src/main/scala/xiangshan/frontend/BPU.scala:191:39, utility/src/main/scala/utility/Hold.scala:97:23 + always @(posedge clock) begin + if (REG_1) begin // src/main/scala/xiangshan/frontend/BPU.scala:190:16 + s1_pc_dup_0 <= _GEN_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 + s1_pc_dup_1 <= _GEN_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 + s1_pc_dup_2 <= _GEN_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 + s1_pc_dup_3 <= _GEN_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :191:39 + end + else begin // src/main/scala/xiangshan/frontend/BPU.scala:190:16 + if (io_s0_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s1_pc_dup_0 <= io_in_bits_s0_pc_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + if (io_s0_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s1_pc_dup_1 <= io_in_bits_s0_pc_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + if (io_s0_fire_2) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s1_pc_dup_2 <= io_in_bits_s0_pc_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + if (io_s0_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s1_pc_dup_3 <= io_in_bits_s0_pc_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86 + end + if (io_s1_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s2_pc_dup_0 <= s1_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86 + if (io_s1_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s2_pc_dup_1 <= s1_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86 + if (io_s1_fire_2) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s2_pc_dup_2 <= s1_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86 + if (io_s1_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s2_pc_dup_3 <= s1_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86 + if (io_s2_fire_0) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_pc_dup_0 <= s2_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86 + if (io_s2_fire_1) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_pc_dup_1 <= s2_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86 + if (io_s2_fire_2) begin // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_pc_dup_2 <= s2_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86 + s3_top <= _RASStack_io_spec_pop_addr; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :574:25 + s3_spec_new_addr <= _s2_spec_new_addr_T_1; // src/main/scala/xiangshan/frontend/newRAS.scala:542:55, :575:35 + s3_pushed_in_s2 <= s2_spec_push; // src/main/scala/xiangshan/frontend/newRAS.scala:548:67, :592:34 + s3_popped_in_s2 <= s2_spec_pop; // src/main/scala/xiangshan/frontend/newRAS.scala:549:67, :593:34 + s3_meta_ssp <= _RASStack_io_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26 + s3_meta_sctr <= _RASStack_io_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26 + s3_meta_TOSW_flag <= _RASStack_io_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26 + s3_meta_TOSW_value <= _RASStack_io_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26 + s3_meta_TOSR_flag <= _RASStack_io_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26 + s3_meta_TOSR_value <= _RASStack_io_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26 + s3_meta_NOS_flag <= _RASStack_io_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26 + s3_meta_NOS_value <= _RASStack_io_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:536:21, :603:26 + end + if (io_s2_fire_3) // src/main/scala/xiangshan/frontend/BPU.scala:171:14 + s3_pc_dup_3 <= s2_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86 + REG <= reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:24 + REG_1 <= REG & ~reset; // src/main/scala/xiangshan/frontend/BPU.scala:190:{16,24,39,42} + redirect_valid <= io_redirect_valid; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + redirect_bits_level <= io_redirect_bits_level; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + redirect_bits_cfiUpdate_pc <= io_redirect_bits_cfiUpdate_pc; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + redirect_bits_cfiUpdate_pd_isRVC <= io_redirect_bits_cfiUpdate_pd_isRVC; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + redirect_bits_cfiUpdate_pd_isCall <= io_redirect_bits_cfiUpdate_pd_isCall; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + redirect_bits_cfiUpdate_pd_isRet <= io_redirect_bits_cfiUpdate_pd_isRet; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + redirect_bits_cfiUpdate_ssp <= io_redirect_bits_cfiUpdate_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + redirect_bits_cfiUpdate_sctr <= io_redirect_bits_cfiUpdate_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + redirect_bits_cfiUpdate_TOSW_flag <= io_redirect_bits_cfiUpdate_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + redirect_bits_cfiUpdate_TOSW_value <= io_redirect_bits_cfiUpdate_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + redirect_bits_cfiUpdate_TOSR_flag <= io_redirect_bits_cfiUpdate_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + redirect_bits_cfiUpdate_TOSR_value <= io_redirect_bits_cfiUpdate_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + redirect_bits_cfiUpdate_NOS_flag <= io_redirect_bits_cfiUpdate_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + redirect_bits_cfiUpdate_NOS_value <= io_redirect_bits_cfiUpdate_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:20]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + initial begin // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + for (logic [4:0] i = 5'h0; i < 5'h15; i += 5'h1) begin + _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + end // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + s1_pc_dup_0 = {_RANDOM[5'h0], _RANDOM[5'h1][6:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + s1_pc_dup_1 = {_RANDOM[5'h1][31:7], _RANDOM[5'h2][13:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + s1_pc_dup_2 = {_RANDOM[5'h2][31:14], _RANDOM[5'h3][20:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + s1_pc_dup_3 = {_RANDOM[5'h3][31:21], _RANDOM[5'h4][27:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + s2_pc_dup_0 = {_RANDOM[5'h4][31:28], _RANDOM[5'h5], _RANDOM[5'h6][2:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:186:86, :187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + s2_pc_dup_1 = {_RANDOM[5'h6][31:3], _RANDOM[5'h7][9:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + s2_pc_dup_2 = {_RANDOM[5'h7][31:10], _RANDOM[5'h8][16:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + s2_pc_dup_3 = {_RANDOM[5'h8][31:17], _RANDOM[5'h9][23:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + s3_pc_dup_0 = {_RANDOM[5'h9][31:24], _RANDOM[5'hA][30:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, :188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + s3_pc_dup_1 = {_RANDOM[5'hA][31], _RANDOM[5'hB], _RANDOM[5'hC][5:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + s3_pc_dup_2 = {_RANDOM[5'hC][31:6], _RANDOM[5'hD][12:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + s3_pc_dup_3 = {_RANDOM[5'hD][31:13], _RANDOM[5'hE][19:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + REG = _RANDOM[5'hE][20]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, :190:24, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + REG_1 = _RANDOM[5'hE][21]; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, :190:16, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + s3_top = {_RANDOM[5'hE][31:22], _RANDOM[5'hF][28:0]}; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25 + s3_spec_new_addr = {_RANDOM[5'hF][31:29], _RANDOM[5'h10], _RANDOM[5'h11][3:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :575:35 + s3_pushed_in_s2 = _RANDOM[5'h11][4]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :592:34 + s3_popped_in_s2 = _RANDOM[5'h11][5]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :593:34 + s3_meta_ssp = _RANDOM[5'h11][9:6]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26 + s3_meta_sctr = _RANDOM[5'h11][12:10]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26 + s3_meta_TOSW_flag = _RANDOM[5'h11][13]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26 + s3_meta_TOSW_value = _RANDOM[5'h11][18:14]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26 + s3_meta_TOSR_flag = _RANDOM[5'h11][19]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26 + s3_meta_TOSR_value = _RANDOM[5'h11][24:20]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26 + s3_meta_NOS_flag = _RANDOM[5'h11][25]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26 + s3_meta_NOS_value = _RANDOM[5'h11][30:26]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :603:26 + redirect_valid = _RANDOM[5'h11][31]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :575:35, :621:25 + redirect_bits_level = _RANDOM[5'h12][21]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 + redirect_bits_cfiUpdate_pc = {_RANDOM[5'h12][31:23], _RANDOM[5'h13][29:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 + redirect_bits_cfiUpdate_pd_isRVC = _RANDOM[5'h13][31]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 + redirect_bits_cfiUpdate_pd_isCall = _RANDOM[5'h14][2]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 + redirect_bits_cfiUpdate_pd_isRet = _RANDOM[5'h14][3]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 + redirect_bits_cfiUpdate_ssp = _RANDOM[5'h14][7:4]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 + redirect_bits_cfiUpdate_sctr = _RANDOM[5'h14][9:8]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 + redirect_bits_cfiUpdate_TOSW_flag = _RANDOM[5'h14][10]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 + redirect_bits_cfiUpdate_TOSW_value = _RANDOM[5'h14][15:11]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 + redirect_bits_cfiUpdate_TOSR_flag = _RANDOM[5'h14][16]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 + redirect_bits_cfiUpdate_TOSR_value = _RANDOM[5'h14][21:17]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 + redirect_bits_cfiUpdate_NOS_flag = _RANDOM[5'h14][22]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 + redirect_bits_cfiUpdate_NOS_value = _RANDOM[5'h14][27:23]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :621:25 + `endif // RANDOMIZE_REG_INIT + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + DelayN_2 reset_vector_delay ( // utility/src/main/scala/utility/Hold.scala:97:23 + .clock (clock), + .io_in (io_reset_vector), + .io_out (_reset_vector_delay_io_out) + ); + RASStack RASStack ( // src/main/scala/xiangshan/frontend/newRAS.scala:536:21 + .clock (clock), + .reset (reset), + .io_spec_push_valid (s2_spec_push), // src/main/scala/xiangshan/frontend/newRAS.scala:548:67 + .io_spec_pop_valid (s2_spec_pop), // src/main/scala/xiangshan/frontend/newRAS.scala:549:67 + .io_spec_push_addr (_s2_spec_new_addr_T_1), // src/main/scala/xiangshan/frontend/newRAS.scala:542:55 + .io_s2_fire (io_s2_fire_2), + .io_s3_fire (io_s3_fire_2), + .io_s3_cancel + (io_s3_fire_2 & (s3_pushed_in_s2 != s3_push | s3_popped_in_s2 != s3_pop)), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:513:44, :514:44, src/main/scala/xiangshan/frontend/newRAS.scala:592:34, :593:34, :597:{33,53,65,84} + .io_s3_meta_ssp (s3_meta_ssp), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 + .io_s3_meta_sctr (s3_meta_sctr), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 + .io_s3_meta_TOSW_flag (s3_meta_TOSW_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 + .io_s3_meta_TOSW_value (s3_meta_TOSW_value), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 + .io_s3_meta_TOSR_flag (s3_meta_TOSR_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 + .io_s3_meta_TOSR_value (s3_meta_TOSR_value), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 + .io_s3_meta_NOS_flag (s3_meta_NOS_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 + .io_s3_meta_NOS_value (s3_meta_NOS_value), // src/main/scala/xiangshan/frontend/newRAS.scala:603:26 + .io_s3_missed_pop (s3_pop & ~s3_popped_in_s2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:514:44, src/main/scala/xiangshan/frontend/newRAS.scala:593:34, :606:{33,36} + .io_s3_missed_push (s3_push & ~s3_pushed_in_s2), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:513:44, src/main/scala/xiangshan/frontend/newRAS.scala:592:34, :607:{35,38} + .io_s3_pushAddr (s3_spec_new_addr), // src/main/scala/xiangshan/frontend/newRAS.scala:575:35 + .io_spec_pop_addr (_RASStack_io_spec_pop_addr), + .io_commit_push_valid + (io_update_valid & io_update_bits_ftb_entry_tailSlot_valid + & io_update_bits_ftb_entry_isCall & io_update_bits_jmp_taken + & io_update_bits_cfi_idx_valid & _GEN_1), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:657:77, src/main/scala/xiangshan/frontend/newRAS.scala:643:42 + .io_commit_pop_valid + (io_update_valid & io_update_bits_ftb_entry_tailSlot_valid + & io_update_bits_ftb_entry_isRet & io_update_bits_jmp_taken + & io_update_bits_cfi_idx_valid & _GEN_1), // src/main/scala/xiangshan/frontend/FrontendBundle.scala:657:77, src/main/scala/xiangshan/frontend/newRAS.scala:644:41 + .io_commit_meta_TOSW_flag (io_update_bits_meta[17]), // src/main/scala/xiangshan/frontend/newRAS.scala:640:48 + .io_commit_meta_TOSW_value (io_update_bits_meta[16:12]), // src/main/scala/xiangshan/frontend/newRAS.scala:640:48 + .io_commit_meta_ssp (io_update_bits_meta[24:21]), // src/main/scala/xiangshan/frontend/newRAS.scala:640:48 + .io_redirect_valid (redirect_valid), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + .io_redirect_isCall + (redirect_valid & ~redirect_bits_level & redirect_bits_cfiUpdate_pd_isCall), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25, :625:56, :626:64 + .io_redirect_isRet + (redirect_valid & ~redirect_bits_level & redirect_bits_cfiUpdate_pd_isRet), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25, :625:{56,64} + .io_redirect_meta_ssp (redirect_bits_cfiUpdate_ssp), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + .io_redirect_meta_sctr ({1'h0, redirect_bits_cfiUpdate_sctr}), // src/main/scala/xiangshan/frontend/newRAS.scala:542:55, :621:25, :633:28 + .io_redirect_meta_TOSW_flag (redirect_bits_cfiUpdate_TOSW_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + .io_redirect_meta_TOSW_value (redirect_bits_cfiUpdate_TOSW_value), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + .io_redirect_meta_TOSR_flag (redirect_bits_cfiUpdate_TOSR_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + .io_redirect_meta_TOSR_value (redirect_bits_cfiUpdate_TOSR_value), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + .io_redirect_meta_NOS_flag (redirect_bits_cfiUpdate_NOS_flag), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + .io_redirect_meta_NOS_value (redirect_bits_cfiUpdate_NOS_value), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25 + .io_redirect_callAddr + (39'(redirect_bits_cfiUpdate_pc + + {36'h0, redirect_bits_cfiUpdate_pd_isRVC ? 3'h2 : 3'h4})), // src/main/scala/xiangshan/frontend/newRAS.scala:621:25, :637:{45,50} + .io_ssp (_RASStack_io_ssp), + .io_sctr (_RASStack_io_sctr), + .io_TOSR_flag (_RASStack_io_TOSR_flag), + .io_TOSR_value (_RASStack_io_TOSR_value), + .io_TOSW_flag (_RASStack_io_TOSW_flag), + .io_TOSW_value (_RASStack_io_TOSW_value), + .io_NOS_flag (_RASStack_io_NOS_flag), + .io_NOS_value (_RASStack_io_NOS_value) + ); + assign io_out_s2_pc_0 = s2_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_pc_1 = s2_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_pc_2 = s2_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_pc_3 = s2_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:187:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_0_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_0_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_0_slot_valids_0 = + io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_0_slot_valids_1 = + io_in_bits_resp_in_0_s2_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_0_targets_0 = io_in_bits_resp_in_0_s2_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_0_targets_1 = + io_in_bits_resp_in_0_s2_full_pred_2_is_jalr + ? (_GEN + ? _RASStack_io_spec_pop_addr + : io_in_bits_resp_in_0_s2_full_pred_0_jalr_target) + : io_in_bits_resp_in_0_s2_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :536:21, :558:{18,41}, :559:54, :564:26 + assign io_out_s2_full_pred_0_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_0_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_0_offsets_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_0_fallThroughAddr = + io_in_bits_resp_in_0_s2_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_0_is_br_sharing = + io_in_bits_resp_in_0_s2_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_0_hit = io_in_bits_resp_in_0_s2_full_pred_0_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_1_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_1_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_1_slot_valids_0 = + io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_1_slot_valids_1 = + io_in_bits_resp_in_0_s2_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_1_targets_0 = io_in_bits_resp_in_0_s2_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_1_targets_1 = + io_in_bits_resp_in_0_s2_full_pred_2_is_jalr + ? (_GEN + ? _RASStack_io_spec_pop_addr + : io_in_bits_resp_in_0_s2_full_pred_1_jalr_target) + : io_in_bits_resp_in_0_s2_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :536:21, :558:{18,41}, :559:54, :564:26 + assign io_out_s2_full_pred_1_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_1_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_1_offsets_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_1_fallThroughAddr = + io_in_bits_resp_in_0_s2_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_1_is_br_sharing = + io_in_bits_resp_in_0_s2_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_1_hit = io_in_bits_resp_in_0_s2_full_pred_1_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_2_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_2_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_2_slot_valids_0 = + io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_2_slot_valids_1 = + io_in_bits_resp_in_0_s2_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_2_targets_0 = io_in_bits_resp_in_0_s2_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_2_targets_1 = + io_in_bits_resp_in_0_s2_full_pred_2_is_jalr + ? (_GEN + ? _RASStack_io_spec_pop_addr + : io_in_bits_resp_in_0_s2_full_pred_2_jalr_target) + : io_in_bits_resp_in_0_s2_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :536:21, :558:{18,41}, :559:54, :564:26 + assign io_out_s2_full_pred_2_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_2_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_2_offsets_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_2_fallThroughAddr = + io_in_bits_resp_in_0_s2_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_2_is_br_sharing = + io_in_bits_resp_in_0_s2_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_2_hit = io_in_bits_resp_in_0_s2_full_pred_2_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_3_br_taken_mask_0 = + io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_3_br_taken_mask_1 = + io_in_bits_resp_in_0_s2_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_3_slot_valids_0 = + io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_3_slot_valids_1 = + io_in_bits_resp_in_0_s2_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_3_targets_0 = io_in_bits_resp_in_0_s2_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_3_targets_1 = + io_in_bits_resp_in_0_s2_full_pred_2_is_jalr + ? (_GEN + ? _RASStack_io_spec_pop_addr + : io_in_bits_resp_in_0_s2_full_pred_3_jalr_target) + : io_in_bits_resp_in_0_s2_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :536:21, :558:{18,41}, :559:54, :564:26 + assign io_out_s2_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s2_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_3_fallThroughAddr = + io_in_bits_resp_in_0_s2_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_3_fallThroughErr = + io_in_bits_resp_in_0_s2_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_3_is_br_sharing = + io_in_bits_resp_in_0_s2_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s2_full_pred_3_hit = io_in_bits_resp_in_0_s2_full_pred_3_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_pc_0 = s3_pc_dup_0; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_pc_1 = s3_pc_dup_1; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_pc_2 = s3_pc_dup_2; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_pc_3 = s3_pc_dup_3; // src/main/scala/xiangshan/frontend/BPU.scala:188:86, src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_0_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_0_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_0_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_0_slot_valids_0 = + io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_0_slot_valids_1 = + io_in_bits_resp_in_0_s3_full_pred_0_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_0_targets_0 = io_in_bits_resp_in_0_s3_full_pred_0_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_0_targets_1 = + io_in_bits_resp_in_0_s3_full_pred_2_is_jalr + ? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_0_jalr_target) + : io_in_bits_resp_in_0_s3_full_pred_0_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :583:{18,41}, :584:54, :589:26 + assign io_out_s3_full_pred_0_fallThroughAddr = + io_in_bits_resp_in_0_s3_full_pred_0_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_0_fallThroughErr = + io_in_bits_resp_in_0_s3_full_pred_0_fallThroughErr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_0_is_br_sharing = + io_in_bits_resp_in_0_s3_full_pred_0_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_0_hit = io_in_bits_resp_in_0_s3_full_pred_0_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_1_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_1_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_1_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_1_slot_valids_0 = + io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_1_slot_valids_1 = + io_in_bits_resp_in_0_s3_full_pred_1_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_1_targets_0 = io_in_bits_resp_in_0_s3_full_pred_1_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_1_targets_1 = + io_in_bits_resp_in_0_s3_full_pred_2_is_jalr + ? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_1_jalr_target) + : io_in_bits_resp_in_0_s3_full_pred_1_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :583:{18,41}, :584:54, :589:26 + assign io_out_s3_full_pred_1_fallThroughAddr = + io_in_bits_resp_in_0_s3_full_pred_1_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_1_fallThroughErr = + io_in_bits_resp_in_0_s3_full_pred_1_fallThroughErr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_1_is_br_sharing = + io_in_bits_resp_in_0_s3_full_pred_1_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_1_hit = io_in_bits_resp_in_0_s3_full_pred_1_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_2_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_2_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_2_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_2_slot_valids_0 = + io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_2_slot_valids_1 = + io_in_bits_resp_in_0_s3_full_pred_2_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_2_targets_0 = io_in_bits_resp_in_0_s3_full_pred_2_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_2_targets_1 = + io_in_bits_resp_in_0_s3_full_pred_2_is_jalr + ? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_2_jalr_target) + : io_in_bits_resp_in_0_s3_full_pred_2_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :583:{18,41}, :584:54, :589:26 + assign io_out_s3_full_pred_2_fallThroughAddr = + io_in_bits_resp_in_0_s3_full_pred_2_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_2_fallThroughErr = + io_in_bits_resp_in_0_s3_full_pred_2_fallThroughErr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_2_is_br_sharing = + io_in_bits_resp_in_0_s3_full_pred_2_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_2_hit = io_in_bits_resp_in_0_s3_full_pred_2_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_3_br_taken_mask_0 = + io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_3_br_taken_mask_1 = + io_in_bits_resp_in_0_s3_full_pred_3_br_taken_mask_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_3_slot_valids_0 = + io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_3_slot_valids_1 = + io_in_bits_resp_in_0_s3_full_pred_3_slot_valids_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_3_targets_0 = io_in_bits_resp_in_0_s3_full_pred_3_targets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_3_targets_1 = + io_in_bits_resp_in_0_s3_full_pred_2_is_jalr + ? (_GEN_0 ? s3_top : io_in_bits_resp_in_0_s3_full_pred_3_jalr_target) + : io_in_bits_resp_in_0_s3_full_pred_3_targets_1; // src/main/scala/xiangshan/frontend/BPU.scala:173:10, src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25, :583:{18,41}, :584:54, :589:26 + assign io_out_s3_full_pred_3_offsets_0 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_3_offsets_1 = io_in_bits_resp_in_0_s3_full_pred_3_offsets_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_3_fallThroughAddr = + io_in_bits_resp_in_0_s3_full_pred_3_fallThroughAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_3_fallThroughErr = + io_in_bits_resp_in_0_s3_full_pred_3_fallThroughErr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_3_is_br_sharing = + io_in_bits_resp_in_0_s3_full_pred_3_is_br_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_s3_full_pred_3_hit = io_in_bits_resp_in_0_s3_full_pred_3_hit; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_meta = + {194'h0, + s3_meta_ssp, + s3_meta_sctr, + s3_meta_TOSW_flag, + s3_meta_TOSW_value, + s3_meta_TOSR_flag, + s3_meta_TOSR_value, + s3_meta_NOS_flag, + s3_meta_NOS_value}; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26, :618:26 + assign io_out_last_stage_spec_info_ssp = s3_meta_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26 + assign io_out_last_stage_spec_info_sctr = s3_meta_sctr[1:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26, :612:37 + assign io_out_last_stage_spec_info_TOSW_flag = s3_meta_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26 + assign io_out_last_stage_spec_info_TOSW_value = s3_meta_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26 + assign io_out_last_stage_spec_info_TOSR_flag = s3_meta_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26 + assign io_out_last_stage_spec_info_TOSR_value = s3_meta_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26 + assign io_out_last_stage_spec_info_NOS_flag = s3_meta_NOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26 + assign io_out_last_stage_spec_info_NOS_value = s3_meta_NOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :603:26 + assign io_out_last_stage_spec_info_topAddr = s3_top; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7, :574:25 + assign io_out_last_stage_ftb_entry_valid = + io_in_bits_resp_in_0_last_stage_ftb_entry_valid; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_brSlots_0_offset = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_offset; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_brSlots_0_lower = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_lower; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_brSlots_0_tarStat = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_tarStat; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_brSlots_0_sharing = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_brSlots_0_valid = + io_in_bits_resp_in_0_last_stage_ftb_entry_brSlots_0_valid; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_tailSlot_offset = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_offset; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_tailSlot_lower = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_lower; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_tailSlot_tarStat = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_tarStat; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_tailSlot_sharing = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_sharing; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_tailSlot_valid = + io_in_bits_resp_in_0_last_stage_ftb_entry_tailSlot_valid; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_pftAddr = + io_in_bits_resp_in_0_last_stage_ftb_entry_pftAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_carry = + io_in_bits_resp_in_0_last_stage_ftb_entry_carry; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_isCall = + io_in_bits_resp_in_0_last_stage_ftb_entry_isCall; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_isRet = + io_in_bits_resp_in_0_last_stage_ftb_entry_isRet; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_isJalr = + io_in_bits_resp_in_0_last_stage_ftb_entry_isJalr; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_last_may_be_rvi_call = + io_in_bits_resp_in_0_last_stage_ftb_entry_last_may_be_rvi_call; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_always_taken_0 = + io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_0; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 + assign io_out_last_stage_ftb_entry_always_taken_1 = + io_in_bits_resp_in_0_last_stage_ftb_entry_always_taken_1; // src/main/scala/xiangshan/frontend/newRAS.scala:75:7 +endmodule + diff --git a/src/RAS/RASStack.sv b/src/RAS/RASStack.sv new file mode 100644 index 0000000..50652e1 --- /dev/null +++ b/src/RAS/RASStack.sv @@ -0,0 +1,1931 @@ +// Generated by CIRCT firtool-1.61.0 +// Standard header to adapt well known macros for register randomization. +`ifndef RANDOMIZE + `ifdef RANDOMIZE_MEM_INIT + `define RANDOMIZE + `endif // RANDOMIZE_MEM_INIT +`endif // not def RANDOMIZE +`ifndef RANDOMIZE + `ifdef RANDOMIZE_REG_INIT + `define RANDOMIZE + `endif // RANDOMIZE_REG_INIT +`endif // not def RANDOMIZE + +// RANDOM may be set to an expression that produces a 32-bit random unsigned value. +`ifndef RANDOM + `define RANDOM $random +`endif // not def RANDOM + +// Users can define INIT_RANDOM as general code that gets injected into the +// initializer block for modules with registers. +`ifndef INIT_RANDOM + `define INIT_RANDOM +`endif // not def INIT_RANDOM + +// If using random initialization, you can also define RANDOMIZE_DELAY to +// customize the delay used, otherwise 0.002 is used. +`ifndef RANDOMIZE_DELAY + `define RANDOMIZE_DELAY 0.002 +`endif // not def RANDOMIZE_DELAY + +// Define INIT_RANDOM_PROLOG_ for use in our modules below. +`ifndef INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE + `ifdef VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM + `else // VERILATOR + `define INIT_RANDOM_PROLOG_ `INIT_RANDOM #`RANDOMIZE_DELAY begin end + `endif // VERILATOR + `else // RANDOMIZE + `define INIT_RANDOM_PROLOG_ + `endif // RANDOMIZE +`endif // not def INIT_RANDOM_PROLOG_ + +// Include register initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_REG_ + `define ENABLE_INITIAL_REG_ + `endif // not def ENABLE_INITIAL_REG_ +`endif // not def SYNTHESIS + +// Include rmemory initializers in init blocks unless synthesis is set +`ifndef SYNTHESIS + `ifndef ENABLE_INITIAL_MEM_ + `define ENABLE_INITIAL_MEM_ + `endif // not def ENABLE_INITIAL_MEM_ +`endif // not def SYNTHESIS + +module RASStack( // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 + input clock, + input reset, + input io_spec_push_valid, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_spec_pop_valid, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input [38:0] io_spec_push_addr, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_s2_fire, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_s3_fire, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_s3_cancel, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input [3:0] io_s3_meta_ssp, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input [2:0] io_s3_meta_sctr, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_s3_meta_TOSW_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input [4:0] io_s3_meta_TOSW_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_s3_meta_TOSR_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input [4:0] io_s3_meta_TOSR_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_s3_meta_NOS_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input [4:0] io_s3_meta_NOS_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_s3_missed_pop, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_s3_missed_push, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input [38:0] io_s3_pushAddr, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + output [38:0] io_spec_pop_addr, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_commit_push_valid, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_commit_pop_valid, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_commit_meta_TOSW_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input [4:0] io_commit_meta_TOSW_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input [3:0] io_commit_meta_ssp, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_redirect_valid, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_redirect_isCall, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_redirect_isRet, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input [3:0] io_redirect_meta_ssp, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input [2:0] io_redirect_meta_sctr, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_redirect_meta_TOSW_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input [4:0] io_redirect_meta_TOSW_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_redirect_meta_TOSR_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input [4:0] io_redirect_meta_TOSR_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input io_redirect_meta_NOS_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input [4:0] io_redirect_meta_NOS_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + input [38:0] io_redirect_callAddr, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + output [3:0] io_ssp, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + output [2:0] io_sctr, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + output io_TOSR_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + output [4:0] io_TOSR_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + output io_TOSW_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + output [4:0] io_TOSW_value, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + output io_NOS_flag, // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + output [4:0] io_NOS_value // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 +); + + reg [38:0] commit_stack_0_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [7:0] commit_stack_0_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [38:0] commit_stack_1_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [7:0] commit_stack_1_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [38:0] commit_stack_2_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [7:0] commit_stack_2_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [38:0] commit_stack_3_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [7:0] commit_stack_3_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [38:0] commit_stack_4_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [7:0] commit_stack_4_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [38:0] commit_stack_5_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [7:0] commit_stack_5_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [38:0] commit_stack_6_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [7:0] commit_stack_6_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [38:0] commit_stack_7_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [7:0] commit_stack_7_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [38:0] commit_stack_8_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [7:0] commit_stack_8_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [38:0] commit_stack_9_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [7:0] commit_stack_9_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [38:0] commit_stack_10_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [7:0] commit_stack_10_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [38:0] commit_stack_11_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [7:0] commit_stack_11_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [38:0] commit_stack_12_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [7:0] commit_stack_12_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [38:0] commit_stack_13_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [7:0] commit_stack_13_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [38:0] commit_stack_14_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [7:0] commit_stack_14_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [38:0] commit_stack_15_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [7:0] commit_stack_15_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31 + reg [38:0] spec_queue_0_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_0_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_1_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_1_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_2_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_2_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_3_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_3_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_4_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_4_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_5_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_5_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_6_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_6_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_7_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_7_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_8_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_8_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_9_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_9_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_10_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_10_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_11_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_11_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_12_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_12_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_13_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_13_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_14_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_14_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_15_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_15_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_16_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_16_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_17_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_17_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_18_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_18_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_19_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_19_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_20_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_20_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_21_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_21_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_22_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_22_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_23_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_23_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_24_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_24_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_25_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_25_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_26_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_26_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_27_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_27_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_28_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_28_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_29_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_29_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_30_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_30_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [38:0] spec_queue_31_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg [7:0] spec_queue_31_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29 + reg spec_nos_0_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_0_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_1_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_1_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_2_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_2_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_3_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_3_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_4_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_4_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_5_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_5_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_6_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_6_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_7_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_7_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_8_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_8_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_9_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_9_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_10_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_10_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_11_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_11_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_12_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_12_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_13_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_13_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_14_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_14_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_15_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_15_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_16_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_16_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_17_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_17_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_18_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_18_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_19_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_19_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_20_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_20_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_21_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_21_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_22_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_22_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_23_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_23_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_24_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_24_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_25_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_25_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_26_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_26_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_27_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_27_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_28_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_28_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_29_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_29_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_30_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_30_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg spec_nos_31_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [4:0] spec_nos_31_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27 + reg [3:0] nsp; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22 + reg [3:0] ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:139:22 + reg [2:0] sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23 + reg TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23 + reg [4:0] TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23 + reg TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23 + reg [4:0] TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23 + reg BOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22 + reg [4:0] BOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22 + reg spec_overflowed; // src/main/scala/xiangshan/frontend/newRAS.scala:146:34 + reg [38:0] writeBypassEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:148:31 + reg [7:0] writeBypassEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:148:31 + reg writeBypassNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:149:29 + reg [4:0] writeBypassNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:149:29 + reg writeBypassValid; // src/main/scala/xiangshan/frontend/newRAS.scala:151:35 + wire _realPush_T_4 = io_redirect_valid & io_redirect_isCall; // src/main/scala/xiangshan/frontend/newRAS.scala:216:29 + wire _GEN = TOSR_value >= BOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 + wire topEntry_inflightValid = + (TOSR_flag ^ BOS_flag ^ _GEN) & (TOSR_flag ^ TOSW_flag ^ TOSR_value < TOSW_value); // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :143:23, :144:22, :157:{13,41}, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30, :74:19 + wire [31:0][38:0] _GEN_0 = + {{spec_queue_31_retAddr}, + {spec_queue_30_retAddr}, + {spec_queue_29_retAddr}, + {spec_queue_28_retAddr}, + {spec_queue_27_retAddr}, + {spec_queue_26_retAddr}, + {spec_queue_25_retAddr}, + {spec_queue_24_retAddr}, + {spec_queue_23_retAddr}, + {spec_queue_22_retAddr}, + {spec_queue_21_retAddr}, + {spec_queue_20_retAddr}, + {spec_queue_19_retAddr}, + {spec_queue_18_retAddr}, + {spec_queue_17_retAddr}, + {spec_queue_16_retAddr}, + {spec_queue_15_retAddr}, + {spec_queue_14_retAddr}, + {spec_queue_13_retAddr}, + {spec_queue_12_retAddr}, + {spec_queue_11_retAddr}, + {spec_queue_10_retAddr}, + {spec_queue_9_retAddr}, + {spec_queue_8_retAddr}, + {spec_queue_7_retAddr}, + {spec_queue_6_retAddr}, + {spec_queue_5_retAddr}, + {spec_queue_4_retAddr}, + {spec_queue_3_retAddr}, + {spec_queue_2_retAddr}, + {spec_queue_1_retAddr}, + {spec_queue_0_retAddr}}; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :187:15 + wire [38:0] _GEN_1 = _GEN_0[TOSR_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :187:15 + wire [31:0][7:0] _GEN_2 = + {{spec_queue_31_ctr}, + {spec_queue_30_ctr}, + {spec_queue_29_ctr}, + {spec_queue_28_ctr}, + {spec_queue_27_ctr}, + {spec_queue_26_ctr}, + {spec_queue_25_ctr}, + {spec_queue_24_ctr}, + {spec_queue_23_ctr}, + {spec_queue_22_ctr}, + {spec_queue_21_ctr}, + {spec_queue_20_ctr}, + {spec_queue_19_ctr}, + {spec_queue_18_ctr}, + {spec_queue_17_ctr}, + {spec_queue_16_ctr}, + {spec_queue_15_ctr}, + {spec_queue_14_ctr}, + {spec_queue_13_ctr}, + {spec_queue_12_ctr}, + {spec_queue_11_ctr}, + {spec_queue_10_ctr}, + {spec_queue_9_ctr}, + {spec_queue_8_ctr}, + {spec_queue_7_ctr}, + {spec_queue_6_ctr}, + {spec_queue_5_ctr}, + {spec_queue_4_ctr}, + {spec_queue_3_ctr}, + {spec_queue_2_ctr}, + {spec_queue_1_ctr}, + {spec_queue_0_ctr}}; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :187:15 + wire [15:0][38:0] _GEN_3 = + {{commit_stack_15_retAddr}, + {commit_stack_14_retAddr}, + {commit_stack_13_retAddr}, + {commit_stack_12_retAddr}, + {commit_stack_11_retAddr}, + {commit_stack_10_retAddr}, + {commit_stack_9_retAddr}, + {commit_stack_8_retAddr}, + {commit_stack_7_retAddr}, + {commit_stack_6_retAddr}, + {commit_stack_5_retAddr}, + {commit_stack_4_retAddr}, + {commit_stack_3_retAddr}, + {commit_stack_2_retAddr}, + {commit_stack_1_retAddr}, + {commit_stack_0_retAddr}}; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :189:15 + wire [38:0] _GEN_4 = _GEN_3[ssp]; // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :189:15 + wire [15:0][7:0] _GEN_5 = + {{commit_stack_15_ctr}, + {commit_stack_14_ctr}, + {commit_stack_13_ctr}, + {commit_stack_12_ctr}, + {commit_stack_11_ctr}, + {commit_stack_10_ctr}, + {commit_stack_9_ctr}, + {commit_stack_8_ctr}, + {commit_stack_7_ctr}, + {commit_stack_6_ctr}, + {commit_stack_5_ctr}, + {commit_stack_4_ctr}, + {commit_stack_3_ctr}, + {commit_stack_2_ctr}, + {commit_stack_1_ctr}, + {commit_stack_0_ctr}}; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :189:15 + wire [31:0] _GEN_6 = + {{spec_nos_31_flag}, + {spec_nos_30_flag}, + {spec_nos_29_flag}, + {spec_nos_28_flag}, + {spec_nos_27_flag}, + {spec_nos_26_flag}, + {spec_nos_25_flag}, + {spec_nos_24_flag}, + {spec_nos_23_flag}, + {spec_nos_22_flag}, + {spec_nos_21_flag}, + {spec_nos_20_flag}, + {spec_nos_19_flag}, + {spec_nos_18_flag}, + {spec_nos_17_flag}, + {spec_nos_16_flag}, + {spec_nos_15_flag}, + {spec_nos_14_flag}, + {spec_nos_13_flag}, + {spec_nos_12_flag}, + {spec_nos_11_flag}, + {spec_nos_10_flag}, + {spec_nos_9_flag}, + {spec_nos_8_flag}, + {spec_nos_7_flag}, + {spec_nos_6_flag}, + {spec_nos_5_flag}, + {spec_nos_4_flag}, + {spec_nos_3_flag}, + {spec_nos_2_flag}, + {spec_nos_1_flag}, + {spec_nos_0_flag}}; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :173:15 + wire [31:0][4:0] _GEN_7 = + {{spec_nos_31_value}, + {spec_nos_30_value}, + {spec_nos_29_value}, + {spec_nos_28_value}, + {spec_nos_27_value}, + {spec_nos_26_value}, + {spec_nos_25_value}, + {spec_nos_24_value}, + {spec_nos_23_value}, + {spec_nos_22_value}, + {spec_nos_21_value}, + {spec_nos_20_value}, + {spec_nos_19_value}, + {spec_nos_18_value}, + {spec_nos_17_value}, + {spec_nos_16_value}, + {spec_nos_15_value}, + {spec_nos_14_value}, + {spec_nos_13_value}, + {spec_nos_12_value}, + {spec_nos_11_value}, + {spec_nos_10_value}, + {spec_nos_9_value}, + {spec_nos_8_value}, + {spec_nos_7_value}, + {spec_nos_6_value}, + {spec_nos_5_value}, + {spec_nos_4_value}, + {spec_nos_3_value}, + {spec_nos_2_value}, + {spec_nos_1_value}, + {spec_nos_0_value}}; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :173:15 + wire [4:0] _GEN_8 = _GEN_7[TOSR_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :173:15 + wire topNos_flag = + writeBypassValid ? writeBypassNos_flag : _GEN_6[TOSR_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :149:29, :151:35, :170:33, :171:15, :173:15 + wire [4:0] topNos_value = writeBypassValid ? writeBypassNos_value : _GEN_8; // src/main/scala/xiangshan/frontend/newRAS.scala:149:29, :151:35, :170:33, :171:15, :173:15 + wire differentFlag_15 = io_redirect_meta_TOSR_flag ^ BOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35 + wire compare_15 = io_redirect_meta_TOSR_value < BOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 + wire differentFlag_16 = + io_redirect_meta_TOSR_flag ^ io_redirect_meta_TOSW_flag; // utility/src/main/scala/utility/CircularQueuePtr.scala:72:35 + wire compare_16 = + io_redirect_meta_TOSR_value < io_redirect_meta_TOSW_value; // utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 + wire redirectTopEntry_inflightValid = + (differentFlag_15 ^ ~compare_15) & (differentFlag_16 ^ compare_16); // src/main/scala/xiangshan/frontend/newRAS.scala:157:{13,41}, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35, :73:30, :74:19 + wire [38:0] writeEntry_retAddr = + _realPush_T_4 ? io_redirect_callAddr : io_spec_push_addr; // src/main/scala/xiangshan/frontend/newRAS.scala:216:29, :244:30 + wire _writeEntry_ctr_T_1 = + (redirectTopEntry_inflightValid + ? _GEN_0[io_redirect_meta_TOSR_value] + : _GEN_3[io_redirect_meta_ssp]) == io_redirect_callAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:157:41, :187:15, :189:15, :192:54, :193:15, :195:15, :246:36 + wire [2:0] _sctr_T_12 = 3'(io_redirect_meta_sctr + 3'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:246:117, :478:38 + wire _writeEntry_ctr_T_7 = + (writeBypassValid + ? writeBypassEntry_retAddr + : topEntry_inflightValid ? _GEN_1 : _GEN_4) == io_spec_push_addr; // src/main/scala/xiangshan/frontend/newRAS.scala:148:31, :151:35, :157:41, :184:33, :185:15, :186:61, :187:15, :189:15, :247:28 + wire [2:0] _sctr_T = 3'(sctr + 3'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :247:81, :478:38 + reg [38:0] timingTop_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:259:28 + reg [38:0] realWriteEntry_next_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:361:40 + reg [7:0] realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:361:40 + wire _GEN_9 = io_redirect_isCall | ~io_s3_missed_push; // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + wire [38:0] realWriteEntry_retAddr = + _GEN_9 ? realWriteEntry_next_retAddr : io_s3_pushAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:361:40, :373:26 + reg [4:0] realWriteAddr_next_value; // src/main/scala/xiangshan/frontend/newRAS.scala:377:39 + reg realNos_next_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:381:33 + reg [4:0] realNos_next_value; // src/main/scala/xiangshan/frontend/newRAS.scala:381:33 + reg realPush_r; // src/main/scala/xiangshan/frontend/newRAS.scala:386:59 + reg realPush_REG; // src/main/scala/xiangshan/frontend/newRAS.scala:386:125 + wire realPush = + io_s3_fire & (~io_s3_cancel & realPush_r | io_s3_missed_push) | realPush_REG; // src/main/scala/xiangshan/frontend/newRAS.scala:386:{29,33,47,59,92,115,125} + wire _GEN_10 = _writeEntry_ctr_T_1 & io_redirect_meta_sctr != 3'h7; // src/main/scala/xiangshan/frontend/newRAS.scala:246:{36,85}, :397:{42,57} + wire _GEN_11 = + io_redirect_isRet & (differentFlag_15 ^ ~compare_15) + & (differentFlag_16 ^ compare_16); // src/main/scala/xiangshan/frontend/newRAS.scala:157:13, :415:52, :416:14, :523:33, :526:32, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35, :73:30, :74:19 + wire [3:0] _sctr_T_16 = 4'(io_redirect_meta_ssp - 4'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:206:33 + wire [3:0] _sctr_T_8 = 4'(io_s3_meta_ssp - 4'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:206:33 + wire _GEN_12 = _writeEntry_ctr_T_7 & sctr != 3'h7; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :246:85, :247:28, :397:{42,57} + wire [3:0] _sctr_T_4 = 4'(ssp - 4'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :206:33 + wire writeBypassValidWire = + _realPush_T_4 | ~io_redirect_valid + & (io_s2_fire ? io_spec_push_valid : ~io_s3_fire & writeBypassValid); // src/main/scala/xiangshan/frontend/newRAS.scala:151:35, :216:{29,52}, :218:24, :219:37, :222:24, :223:30, :225:24, :226:30, :228:24 + wire differentFlag_10 = io_s3_meta_TOSR_flag ^ BOS_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35 + wire compare_10 = io_s3_meta_TOSR_value < BOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 + wire differentFlag_11 = io_s3_meta_TOSR_flag ^ io_s3_meta_TOSW_flag; // utility/src/main/scala/utility/CircularQueuePtr.scala:72:35 + wire compare_11 = io_s3_meta_TOSR_value < io_s3_meta_TOSW_value; // utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 + wire s3TopEntry_inflightValid = + (differentFlag_10 ^ ~compare_10) & (differentFlag_11 ^ compare_11); // src/main/scala/xiangshan/frontend/newRAS.scala:157:{13,41}, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35, :73:30, :74:19 + wire _GEN_13 = io_redirect_meta_NOS_value >= BOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 + wire _GEN_14 = io_redirect_meta_NOS_flag ^ BOS_flag ^ _GEN_13; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :157:13, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 + wire _GEN_15 = topNos_value >= BOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :170:33, :171:15, :173:15, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 + wire _GEN_16 = topNos_flag ^ BOS_flag ^ _GEN_15; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :157:13, :170:33, :171:15, :173:15, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 + wire _GEN_17 = io_s3_meta_NOS_value >= BOS_value; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 + wire _GEN_18 = io_s3_meta_NOS_flag ^ BOS_flag ^ _GEN_17; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :157:13, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30 + wire _s3_missPushEntry_ctr_T = + (s3TopEntry_inflightValid + ? _GEN_0[io_s3_meta_TOSR_value] + : _GEN_3[io_s3_meta_ssp]) == io_s3_pushAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:157:41, :187:15, :189:15, :192:54, :193:15, :195:15, :367:52 + wire [2:0] _sctr_T_10 = 3'(io_s3_meta_sctr + 3'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:367:115, :478:38 + wire [7:0] s3_missPushEntry_ctr = + {5'h0, + _s3_missPushEntry_ctr_T + & (s3TopEntry_inflightValid + ? _GEN_2[io_s3_meta_TOSR_value] + : _GEN_5[io_s3_meta_ssp]) < 8'h7 + ? _sctr_T_10 + : 3'h0}; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :157:41, :187:15, :189:15, :192:54, :193:15, :195:15, :246:85, :260:41, :367:{26,32,52,71,89,115} + wire [4:0] realWriteAddr_value = + _GEN_9 ? realWriteAddr_next_value : io_s3_meta_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:373:26, :377:39, :378:28 + wire realNos_flag = _GEN_9 ? realNos_next_flag : io_s3_meta_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:373:26, :381:33, :382:22 + wire [4:0] realNos_value = _GEN_9 ? realNos_next_value : io_s3_meta_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:373:26, :381:33, :382:22 + wire [5:0] _GEN_19 = {TOSW_flag, TOSW_value}; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [5:0] _GEN_20 = {BOS_flag, BOS_value}; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire _GEN_21 = + io_spec_push_valid & 6'(_GEN_19 + 6'h1) == {BOS_flag, BOS_value}; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :404:46, :405:13, :410:31, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :61:{47,56} + wire [5:0] _GEN_22 = {io_s3_meta_TOSW_flag, io_s3_meta_TOSW_value}; // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire _GEN_23 = 6'(_GEN_22 + 6'h1) == {BOS_flag, BOS_value}; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :61:{47,56} + wire [7:0] _GEN_24 = _GEN_5[nsp]; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :189:15, :477:27 + wire [7:0] _commit_stack_ctr_T = 8'(_GEN_24 - 8'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:477:27, :478:55 + wire _GEN_25 = io_commit_meta_ssp == 4'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :478:38 + wire _GEN_26 = io_commit_pop_valid & (|_GEN_24) & _GEN_25; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 + wire _GEN_27 = io_commit_meta_ssp == 4'h1; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + wire _GEN_28 = io_commit_pop_valid & (|_GEN_24) & _GEN_27; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 + wire _GEN_29 = io_commit_meta_ssp == 4'h2; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + wire _GEN_30 = io_commit_pop_valid & (|_GEN_24) & _GEN_29; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 + wire _GEN_31 = io_commit_meta_ssp == 4'h3; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + wire _GEN_32 = io_commit_pop_valid & (|_GEN_24) & _GEN_31; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 + wire _GEN_33 = io_commit_meta_ssp == 4'h4; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + wire _GEN_34 = io_commit_pop_valid & (|_GEN_24) & _GEN_33; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 + wire _GEN_35 = io_commit_meta_ssp == 4'h5; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + wire _GEN_36 = io_commit_pop_valid & (|_GEN_24) & _GEN_35; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 + wire _GEN_37 = io_commit_meta_ssp == 4'h6; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + wire _GEN_38 = io_commit_pop_valid & (|_GEN_24) & _GEN_37; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 + wire _GEN_39 = io_commit_meta_ssp == 4'h7; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + wire _GEN_40 = io_commit_pop_valid & (|_GEN_24) & _GEN_39; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 + wire _GEN_41 = io_commit_meta_ssp == 4'h8; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + wire _GEN_42 = io_commit_pop_valid & (|_GEN_24) & _GEN_41; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 + wire _GEN_43 = io_commit_meta_ssp == 4'h9; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + wire _GEN_44 = io_commit_pop_valid & (|_GEN_24) & _GEN_43; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 + wire _GEN_45 = io_commit_meta_ssp == 4'hA; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + wire _GEN_46 = io_commit_pop_valid & (|_GEN_24) & _GEN_45; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 + wire _GEN_47 = io_commit_meta_ssp == 4'hB; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + wire _GEN_48 = io_commit_pop_valid & (|_GEN_24) & _GEN_47; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 + wire _GEN_49 = io_commit_meta_ssp == 4'hC; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + wire _GEN_50 = io_commit_pop_valid & (|_GEN_24) & _GEN_49; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 + wire _GEN_51 = io_commit_meta_ssp == 4'hD; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + wire _GEN_52 = io_commit_pop_valid & (|_GEN_24) & _GEN_51; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 + wire _GEN_53 = io_commit_meta_ssp == 4'hE; // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + wire _GEN_54 = io_commit_pop_valid & (|_GEN_24) & _GEN_53; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 + wire _GEN_55 = io_commit_pop_valid & (|_GEN_24) & (&io_commit_meta_ssp); // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:{27,34}, :478:38 + wire _GEN_56 = + _GEN_24 < 8'h7 & _GEN_3[nsp] == _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :187:15, :189:15, :246:85, :477:27, :499:{27,36,57} + wire [3:0] _nsp_T_2 = 4'(io_commit_meta_ssp + 4'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38 + wire _GEN_57 = _nsp_T_2 == 4'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :205:33, :504:50 + wire _GEN_58 = _nsp_T_2 == 4'h1; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 + wire _GEN_59 = _nsp_T_2 == 4'h2; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 + wire _GEN_60 = _nsp_T_2 == 4'h3; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 + wire _GEN_61 = _nsp_T_2 == 4'h4; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 + wire _GEN_62 = _nsp_T_2 == 4'h5; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 + wire _GEN_63 = _nsp_T_2 == 4'h6; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 + wire _GEN_64 = _nsp_T_2 == 4'h7; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 + wire _GEN_65 = _nsp_T_2 == 4'h8; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 + wire _GEN_66 = _nsp_T_2 == 4'h9; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 + wire _GEN_67 = _nsp_T_2 == 4'hA; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 + wire _GEN_68 = _nsp_T_2 == 4'hB; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 + wire _GEN_69 = _nsp_T_2 == 4'hC; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 + wire _GEN_70 = _nsp_T_2 == 4'hD; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 + wire _GEN_71 = _nsp_T_2 == 4'hE; // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :478:38, :504:50 + wire [5:0] _GEN_72 = {io_commit_meta_TOSW_flag, io_commit_meta_TOSW_value}; // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [5:0] _new_ptr_WIRE_5 = 6'(_GEN_72 + 6'h1); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire _GEN_73 = + io_commit_push_valid + & (~spec_overflowed | _new_ptr_WIRE_5[5] ^ BOS_flag + ^ _new_ptr_WIRE_5[4:0] > BOS_value); // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :146:34, :447:25, :490:33, :508:{13,30,80}, :509:13, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59}, :67:30, :68:19 + wire [5:0] _GEN_74 = {io_redirect_meta_TOSW_flag, io_redirect_meta_TOSW_value}; // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire _GEN_75 = + io_redirect_valid & io_redirect_isCall & 6'(_GEN_74 + 6'h1) == {BOS_flag, BOS_value}; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :404:46, :405:13, :490:33, :517:30, :523:33, utility/src/main/scala/utility/CircularQueuePtr.scala:39:46, :61:{47,56} + wire [7:0] _commit_stack_ctr_T_2 = 8'(_GEN_24 + 8'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:477:27, :478:55, :500:55 + wire [5:0] _GEN_76 = 6'(_GEN_74 + 6'h1); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire inflightValid_8 = + _GEN_14 + & (io_redirect_meta_NOS_flag ^ io_redirect_meta_TOSW_flag + ^ io_redirect_meta_NOS_value < io_redirect_meta_TOSW_value); // src/main/scala/xiangshan/frontend/newRAS.scala:157:{13,41}, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30, :74:19 + wire _GEN_77 = + io_s3_missed_pop & (differentFlag_10 ^ ~compare_10) & (differentFlag_11 ^ compare_11); // src/main/scala/xiangshan/frontend/newRAS.scala:157:13, :415:52, :416:14, :449:12, :455:31, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35, :73:30, :74:19 + wire inflightValid_6 = + _GEN_18 + & (io_s3_meta_NOS_flag ^ io_s3_meta_TOSW_flag + ^ io_s3_meta_NOS_value < io_s3_meta_TOSW_value); // src/main/scala/xiangshan/frontend/newRAS.scala:157:{13,41}, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30, :74:19 + wire [5:0] _GEN_78 = 6'(_GEN_22 + 6'h1); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire _GEN_79 = _s3_missPushEntry_ctr_T & io_s3_meta_sctr != 3'h7; // src/main/scala/xiangshan/frontend/newRAS.scala:246:85, :367:52, :397:{42,57} + wire inflightValid_4 = + _GEN_16 & (topNos_flag ^ TOSW_flag ^ topNos_value < TOSW_value); // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :157:{13,41}, :170:33, :171:15, :173:15, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30, :74:19 + wire [5:0] _GEN_80 = 6'(_GEN_19 + 6'h1); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [5:0] _BOS_new_ptr_WIRE_7 = 6'(_GEN_20 + 6'h1); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [5:0] _BOS_new_ptr_WIRE_5 = 6'(_GEN_72 + 6'h1); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [5:0] _BOS_new_ptr_WIRE_3 = 6'(_GEN_20 + 6'h1); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + wire [5:0] _BOS_new_ptr_WIRE_1 = 6'(_GEN_20 + 6'h1); // utility/src/main/scala/utility/CircularQueuePtr.scala:39:46 + always @(posedge clock or posedge reset) begin + if (reset) begin + commit_stack_0_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_0_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_1_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_1_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_2_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_2_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_3_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_3_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_4_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_4_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_5_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_5_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_6_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_6_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_7_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_7_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_8_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_8_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_9_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_9_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_10_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_10_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_11_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_11_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_12_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_12_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_13_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_13_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_14_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_14_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_15_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_15_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + spec_queue_0_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_0_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_1_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_1_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_2_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_2_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_3_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_3_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_4_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_4_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_5_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_5_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_6_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_6_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_7_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_7_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_8_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_8_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_9_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_9_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_10_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_10_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_11_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_11_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_12_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_12_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_13_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_13_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_14_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_14_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_15_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_15_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_16_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_16_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_17_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_17_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_18_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_18_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_19_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_19_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_20_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_20_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_21_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_21_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_22_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_22_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_23_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_23_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_24_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_24_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_25_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_25_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_26_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_26_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_27_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_27_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_28_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_28_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_29_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_29_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_30_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_30_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_31_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_31_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_nos_0_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_0_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_1_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_1_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_2_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_2_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_3_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_3_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_4_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_4_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_5_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_5_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_6_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_6_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_7_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_7_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_8_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_8_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_9_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_9_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_10_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_10_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_11_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_11_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_12_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_12_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_13_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_13_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_14_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_14_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_15_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_15_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_16_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_16_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_17_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_17_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_18_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_18_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_19_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_19_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_20_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_20_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_21_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_21_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_22_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_22_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_23_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_23_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_24_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_24_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_25_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_25_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_26_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_26_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_27_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_27_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_28_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_28_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_29_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_29_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_30_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_30_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_31_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_31_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + nsp <= 4'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22 + ssp <= 4'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :139:22 + sctr <= 3'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23 + TOSR_flag <= 1'h1; // src/main/scala/xiangshan/frontend/newRAS.scala:40:14, :142:23 + TOSR_value <= 5'h1F; // src/main/scala/xiangshan/frontend/newRAS.scala:41:15, :142:23 + TOSW_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :143:23 + TOSW_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :260:41 + BOS_flag <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :144:22 + BOS_value <= 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :260:41 + spec_overflowed <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :146:34 + writeBypassValid <= 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :151:35 + timingTop_retAddr <= 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:259:{28,41} + end + else begin + if (~io_commit_push_valid | _GEN_56 | ~_GEN_57) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + end + else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 + commit_stack_0_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 + if (io_commit_push_valid) begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + if (_GEN_56) begin // src/main/scala/xiangshan/frontend/newRAS.scala:499:36 + if (_GEN_25) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + commit_stack_0_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 + else if (_GEN_26) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_0_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_27) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + commit_stack_1_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 + else if (_GEN_28) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_1_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_29) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + commit_stack_2_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 + else if (_GEN_30) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_2_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_31) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + commit_stack_3_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 + else if (_GEN_32) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_3_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_33) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + commit_stack_4_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 + else if (_GEN_34) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_4_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_35) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + commit_stack_5_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 + else if (_GEN_36) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_5_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_37) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + commit_stack_6_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 + else if (_GEN_38) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_6_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_39) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + commit_stack_7_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 + else if (_GEN_40) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_7_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_41) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + commit_stack_8_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 + else if (_GEN_42) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_8_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_43) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + commit_stack_9_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 + else if (_GEN_44) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_9_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_45) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + commit_stack_10_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 + else if (_GEN_46) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_10_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_47) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + commit_stack_11_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 + else if (_GEN_48) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_11_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_49) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + commit_stack_12_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 + else if (_GEN_50) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_12_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_51) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + commit_stack_13_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 + else if (_GEN_52) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_13_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_53) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + commit_stack_14_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 + else if (_GEN_54) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_14_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (&io_commit_meta_ssp) // src/main/scala/xiangshan/frontend/newRAS.scala:478:38 + commit_stack_15_ctr <= _commit_stack_ctr_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :500:55 + else if (_GEN_55) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_15_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + nsp <= io_commit_meta_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22 + end + else begin // src/main/scala/xiangshan/frontend/newRAS.scala:499:36 + if (_GEN_57) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 + commit_stack_0_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + else if (_GEN_26) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_0_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_58) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 + commit_stack_1_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + else if (_GEN_28) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_1_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_59) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 + commit_stack_2_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + else if (_GEN_30) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_2_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_60) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 + commit_stack_3_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + else if (_GEN_32) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_3_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_61) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 + commit_stack_4_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + else if (_GEN_34) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_4_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_62) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 + commit_stack_5_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + else if (_GEN_36) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_5_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_63) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 + commit_stack_6_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + else if (_GEN_38) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_6_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_64) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 + commit_stack_7_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + else if (_GEN_40) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_7_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_65) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 + commit_stack_8_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + else if (_GEN_42) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_8_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_66) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 + commit_stack_9_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + else if (_GEN_44) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_9_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_67) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 + commit_stack_10_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + else if (_GEN_46) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_10_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_68) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 + commit_stack_11_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + else if (_GEN_48) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_11_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_69) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 + commit_stack_12_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + else if (_GEN_50) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_12_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_70) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 + commit_stack_13_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + else if (_GEN_52) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_13_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_71) // src/main/scala/xiangshan/frontend/newRAS.scala:504:50 + commit_stack_14_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + else if (_GEN_54) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_14_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (&_nsp_T_2) // src/main/scala/xiangshan/frontend/newRAS.scala:205:33, :504:50 + commit_stack_15_ctr <= 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + else if (_GEN_55) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_15_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + nsp <= _nsp_T_2; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :205:33 + end + end + else begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + if (_GEN_26) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_0_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_28) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_1_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_30) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_2_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_32) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_3_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_34) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_4_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_36) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_5_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_38) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_6_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_40) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_7_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_42) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_8_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_44) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_9_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_46) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_10_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_48) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_11_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_50) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_12_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_52) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_13_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_54) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_14_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (_GEN_55) // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :466:32, :477:34, :478:38 + commit_stack_15_ctr <= _commit_stack_ctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :478:55 + if (io_commit_pop_valid) begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + if (|_GEN_24) // src/main/scala/xiangshan/frontend/newRAS.scala:477:27 + nsp <= io_commit_meta_ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22 + else // src/main/scala/xiangshan/frontend/newRAS.scala:477:27 + nsp <= 4'(io_commit_meta_ssp - 4'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :206:33 + end + end + if (~io_commit_push_valid | _GEN_56 | ~_GEN_58) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + end + else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 + commit_stack_1_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 + if (~io_commit_push_valid | _GEN_56 | ~_GEN_59) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + end + else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 + commit_stack_2_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 + if (~io_commit_push_valid | _GEN_56 | ~_GEN_60) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + end + else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 + commit_stack_3_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 + if (~io_commit_push_valid | _GEN_56 | ~_GEN_61) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + end + else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 + commit_stack_4_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 + if (~io_commit_push_valid | _GEN_56 | ~_GEN_62) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + end + else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 + commit_stack_5_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 + if (~io_commit_push_valid | _GEN_56 | ~_GEN_63) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + end + else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 + commit_stack_6_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 + if (~io_commit_push_valid | _GEN_56 | ~_GEN_64) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + end + else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 + commit_stack_7_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 + if (~io_commit_push_valid | _GEN_56 | ~_GEN_65) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + end + else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 + commit_stack_8_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 + if (~io_commit_push_valid | _GEN_56 | ~_GEN_66) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + end + else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 + commit_stack_9_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 + if (~io_commit_push_valid | _GEN_56 | ~_GEN_67) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + end + else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 + commit_stack_10_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 + if (~io_commit_push_valid | _GEN_56 | ~_GEN_68) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + end + else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 + commit_stack_11_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 + if (~io_commit_push_valid | _GEN_56 | ~_GEN_69) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + end + else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 + commit_stack_12_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 + if (~io_commit_push_valid | _GEN_56 | ~_GEN_70) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + end + else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 + commit_stack_13_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 + if (~io_commit_push_valid | _GEN_56 | ~_GEN_71) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:{36,79}, :504:50 + end + else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 + commit_stack_14_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 + if (~io_commit_push_valid | _GEN_56 | ~(&_nsp_T_2)) begin // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :205:33, :490:33, :499:{36,79}, :504:50 + end + else // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :490:33, :499:79 + commit_stack_15_retAddr <= _GEN_0[io_commit_meta_TOSW_value]; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :187:15, :499:57 + if (realPush & realWriteAddr_value == 5'h0) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :260:41, :378:28, :386:115, :388:21, :389:39 + spec_queue_0_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_0_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_0_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_0_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_0_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h1) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_1_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_1_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_1_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_1_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_1_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h2) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_2_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_2_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_2_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_2_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_2_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h3) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_3_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_3_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_3_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_3_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_3_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h4) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_4_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_4_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_4_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_4_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_4_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h5) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_5_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_5_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_5_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_5_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_5_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h6) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_6_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_6_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_6_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_6_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_6_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h7) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_7_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_7_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_7_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_7_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_7_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h8) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_8_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_8_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_8_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_8_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_8_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h9) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_9_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_9_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_9_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_9_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_9_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'hA) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_10_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_10_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_10_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_10_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_10_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'hB) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_11_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_11_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_11_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_11_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_11_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'hC) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_12_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_12_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_12_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_12_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_12_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'hD) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_13_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_13_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_13_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_13_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_13_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'hE) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_14_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_14_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_14_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_14_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_14_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'hF) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_15_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_15_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_15_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_15_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_15_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h10) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_16_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_16_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_16_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_16_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_16_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h11) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_17_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_17_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_17_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_17_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_17_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h12) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_18_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_18_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_18_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_18_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_18_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h13) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_19_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_19_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_19_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_19_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_19_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h14) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_20_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_20_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_20_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_20_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_20_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h15) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_21_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_21_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_21_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_21_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_21_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h16) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_22_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_22_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_22_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_22_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_22_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h17) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_23_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_23_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_23_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_23_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_23_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h18) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_24_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_24_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_24_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_24_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_24_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h19) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_25_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_25_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_25_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_25_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_25_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h1A) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_26_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_26_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_26_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_26_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_26_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h1B) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_27_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_27_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_27_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_27_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_27_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h1C) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_28_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_28_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_28_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_28_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_28_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h1D) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_29_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_29_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_29_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_29_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_29_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & realWriteAddr_value == 5'h1E) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_30_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_30_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_30_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_30_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_30_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (realPush & (&realWriteAddr_value)) begin // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :378:28, :386:115, :388:21, :389:39 + spec_queue_31_retAddr <= realWriteEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :373:26 + if (_GEN_9) // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_31_ctr <= realWriteEntry_next_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :361:40 + else // src/main/scala/xiangshan/frontend/newRAS.scala:373:26 + spec_queue_31_ctr <= s3_missPushEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :367:26 + spec_nos_31_flag <= realNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + spec_nos_31_value <= realNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :382:22 + end + if (io_redirect_valid) begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + ssp <= + ~io_redirect_isRet | (|io_redirect_meta_sctr) + ? (~io_redirect_isCall | _GEN_10 + ? io_redirect_meta_ssp + : 4'(io_redirect_meta_ssp + 4'h1)) + : inflightValid_8 ? 4'(io_redirect_meta_ssp - 4'h1) : _sctr_T_16; // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :157:41, :205:33, :206:33, :278:35, :397:{42,67}, :419:32, :421:61, :423:13, :427:13, :478:38, :520:11, :523:33, :526:32 + sctr <= + io_redirect_isRet + ? ((|io_redirect_meta_sctr) + ? 3'(io_redirect_meta_sctr - 3'h1) + : inflightValid_8 + ? _GEN_2[io_redirect_meta_NOS_value][2:0] + : _GEN_5[_sctr_T_16][2:0]) + : io_redirect_isCall ? (_GEN_10 ? _sctr_T_12 : 3'h0) : io_redirect_meta_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :157:41, :187:15, :189:15, :206:33, :246:117, :278:35, :397:{42,67}, :398:14, :401:14, :419:32, :420:{14,29}, :421:61, :424:14, :428:14, :521:12, :523:33, :526:32 + TOSR_flag <= + _GEN_11 + ? io_redirect_meta_NOS_flag + : io_redirect_isCall + ? io_redirect_meta_TOSW_flag + : io_redirect_meta_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :394:12, :415:52, :416:14, :518:12, :523:33, :526:32 + TOSR_value <= + _GEN_11 + ? io_redirect_meta_NOS_value + : io_redirect_isCall + ? io_redirect_meta_TOSW_value + : io_redirect_meta_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :394:12, :415:52, :416:14, :518:12, :523:33, :526:32 + TOSW_flag <= io_redirect_isCall ? _GEN_76[5] : io_redirect_meta_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :395:12, :519:12, :523:33, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + TOSW_value <= io_redirect_isCall ? _GEN_76[4:0] : io_redirect_meta_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :395:12, :519:12, :523:33, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + end + else if (io_s3_cancel) begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + ssp <= + ~io_s3_missed_push | _GEN_79 + ? (~io_s3_missed_pop | (|io_s3_meta_sctr) + ? io_s3_meta_ssp + : inflightValid_6 ? 4'(io_s3_meta_ssp - 4'h1) : _sctr_T_8) + : 4'(io_s3_meta_ssp + 4'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :157:41, :205:33, :206:33, :335:31, :373:26, :397:{42,67}, :419:32, :421:61, :423:13, :427:13, :451:11, :455:31, :458:32, :478:38 + sctr <= + io_s3_missed_push + ? (_GEN_79 ? _sctr_T_10 : 3'h0) + : io_s3_missed_pop + ? ((|io_s3_meta_sctr) + ? 3'(io_s3_meta_sctr - 3'h1) + : inflightValid_6 + ? _GEN_2[io_s3_meta_NOS_value][2:0] + : _GEN_5[_sctr_T_8][2:0]) + : io_s3_meta_sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :157:41, :187:15, :189:15, :206:33, :335:31, :367:115, :397:{42,67}, :398:14, :401:14, :419:32, :420:{14,29}, :421:61, :424:14, :428:14, :452:12, :455:31, :458:32 + TOSR_flag <= + io_s3_missed_push + ? io_s3_meta_TOSW_flag + : _GEN_77 ? io_s3_meta_NOS_flag : io_s3_meta_TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :394:12, :415:52, :416:14, :449:12, :455:31, :458:32 + TOSR_value <= + io_s3_missed_push + ? io_s3_meta_TOSW_value + : _GEN_77 ? io_s3_meta_NOS_value : io_s3_meta_TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :394:12, :415:52, :416:14, :449:12, :455:31, :458:32 + TOSW_flag <= io_s3_missed_push ? _GEN_78[5] : io_s3_meta_TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :395:12, :450:12, :458:32, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + TOSW_value <= io_s3_missed_push ? _GEN_78[4:0] : io_s3_meta_TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :395:12, :450:12, :458:32, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + end + else begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + if (~io_spec_pop_valid | (|sctr)) begin // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :306:18, :410:31, :419:32, :432:30 + if (~io_spec_push_valid | _GEN_12) begin // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :397:{42,67}, :410:31 + end + else // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :397:67, :410:31 + ssp <= 4'(ssp + 4'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :205:33, :478:38 + end + else if (inflightValid_4) // src/main/scala/xiangshan/frontend/newRAS.scala:157:41 + ssp <= 4'(ssp - 4'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :206:33 + else // src/main/scala/xiangshan/frontend/newRAS.scala:157:41 + ssp <= _sctr_T_4; // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :206:33 + if (io_spec_pop_valid) begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + if (|sctr) // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :306:18 + sctr <= 3'(sctr - 3'h1); // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :420:29 + else // src/main/scala/xiangshan/frontend/newRAS.scala:306:18 + sctr <= inflightValid_4 ? _GEN_2[topNos_value][2:0] : _GEN_5[_sctr_T_4][2:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :157:41, :170:33, :171:15, :173:15, :187:15, :189:15, :206:33, :421:61, :424:14, :428:14 + end + else if (io_spec_push_valid) begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + if (_GEN_12) // src/main/scala/xiangshan/frontend/newRAS.scala:397:42 + sctr <= _sctr_T; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23, :247:81 + else // src/main/scala/xiangshan/frontend/newRAS.scala:397:42 + sctr <= 3'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23 + end + if (io_spec_pop_valid & (TOSR_flag ^ BOS_flag ^ _GEN) + & (TOSR_flag ^ TOSW_flag ^ TOSR_value < TOSW_value)) begin // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :143:23, :144:22, :157:13, :410:31, :415:52, :416:14, :432:30, utility/src/main/scala/utility/CircularQueuePtr.scala:73:30, :74:19 + TOSR_flag <= topNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :170:33, :171:15, :173:15 + if (writeBypassValid) // src/main/scala/xiangshan/frontend/newRAS.scala:151:35 + TOSR_value <= writeBypassNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :149:29 + else // src/main/scala/xiangshan/frontend/newRAS.scala:151:35 + TOSR_value <= _GEN_8; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :173:15 + end + else if (io_spec_push_valid) begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + TOSR_flag <= TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :143:23 + TOSR_value <= TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :143:23 + end + if (io_spec_push_valid) begin // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + TOSW_flag <= _GEN_80[5]; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + TOSW_value <= _GEN_80[4:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + end + end + if (_GEN_75) begin // src/main/scala/xiangshan/frontend/newRAS.scala:404:46, :405:13, :490:33, :517:30, :523:33 + BOS_flag <= _BOS_new_ptr_WIRE_7[5]; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + BOS_value <= _BOS_new_ptr_WIRE_7[4:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + end + else if (_GEN_73) begin // src/main/scala/xiangshan/frontend/newRAS.scala:447:25, :490:33, :508:80, :509:13 + BOS_flag <= _BOS_new_ptr_WIRE_5[5]; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + BOS_value <= _BOS_new_ptr_WIRE_5[4:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + end + else if (io_s3_cancel & io_s3_missed_push & _GEN_23) begin // src/main/scala/xiangshan/frontend/newRAS.scala:404:46, :405:13, :410:31, :447:25, :458:32, utility/src/main/scala/utility/CircularQueuePtr.scala:61:47 + BOS_flag <= _BOS_new_ptr_WIRE_3[5]; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + BOS_value <= _BOS_new_ptr_WIRE_3[4:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + end + else if (_GEN_21) begin // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :404:46, :405:13, :410:31 + BOS_flag <= _BOS_new_ptr_WIRE_1[5]; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + BOS_value <= _BOS_new_ptr_WIRE_1[4:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, utility/src/main/scala/utility/CircularQueuePtr.scala:39:{46,59} + end + spec_overflowed <= + _GEN_75 | ~_GEN_73 + & (io_s3_cancel & io_s3_missed_push + ? _GEN_23 | _GEN_21 | spec_overflowed + : _GEN_21 | spec_overflowed); // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :146:34, :404:46, :405:13, :406:25, :410:31, :447:25, :458:32, :490:33, :508:80, :509:13, :510:25, :517:30, :523:33, utility/src/main/scala/utility/CircularQueuePtr.scala:61:47 + writeBypassValid <= writeBypassValidWire; // src/main/scala/xiangshan/frontend/newRAS.scala:151:35, :216:52, :218:24, :219:37 + timingTop_retAddr <= + writeBypassValidWire + ? (_realPush_T_4 | io_spec_push_valid + ? writeEntry_retAddr + : writeBypassEntry_retAddr) + : io_redirect_valid & io_redirect_isRet + ? ((io_redirect_meta_NOS_flag ^ BOS_flag ^ _GEN_13) + & (io_redirect_meta_NOS_flag ^ io_redirect_meta_TOSW_flag + ^ io_redirect_meta_NOS_value < io_redirect_meta_TOSW_value) + ? _GEN_0[io_redirect_meta_NOS_value] + : _GEN_3[(|io_redirect_meta_sctr) + ? io_redirect_meta_ssp + : _GEN_14 + & (io_redirect_meta_NOS_flag ^ TOSW_flag + ^ io_redirect_meta_NOS_value < TOSW_value) + ? 4'(io_redirect_meta_ssp - 4'h1) + : 4'(io_redirect_meta_ssp - 4'h1)]) + : io_redirect_valid + ? ((differentFlag_15 ^ ~compare_15) & (differentFlag_16 ^ compare_16) + ? _GEN_0[io_redirect_meta_TOSR_value] + : _GEN_3[io_redirect_meta_ssp]) + : io_spec_pop_valid + ? ((topNos_flag ^ BOS_flag ^ _GEN_15) + & (topNos_flag ^ TOSW_flag ^ topNos_value < TOSW_value) + ? _GEN_0[topNos_value] + : _GEN_3[(|sctr) + ? ssp + : _GEN_16 + & (topNos_flag ^ TOSW_flag + ^ topNos_value < TOSW_value) + ? 4'(ssp - 4'h1) + : 4'(ssp - 4'h1)]) + : realPush + ? realWriteEntry_retAddr + : io_s3_cancel + ? (io_s3_missed_push + ? io_s3_pushAddr + : io_s3_missed_pop + ? ((io_s3_meta_NOS_flag ^ BOS_flag ^ _GEN_17) + & (io_s3_meta_NOS_flag ^ io_s3_meta_TOSW_flag + ^ io_s3_meta_NOS_value < io_s3_meta_TOSW_value) + ? _GEN_0[io_s3_meta_NOS_value] + : _GEN_3[(|io_s3_meta_sctr) + ? io_s3_meta_ssp + : _GEN_18 + & (io_s3_meta_NOS_flag + ^ io_s3_meta_TOSW_flag + ^ io_s3_meta_NOS_value < io_s3_meta_TOSW_value) + ? 4'(io_s3_meta_ssp - 4'h1) + : 4'(io_s3_meta_ssp - 4'h1)]) + : (differentFlag_10 ^ ~compare_10) + & (differentFlag_11 ^ compare_11) + ? _GEN_0[io_s3_meta_TOSR_value] + : _GEN_3[io_s3_meta_ssp]) + : (TOSR_flag ^ BOS_flag ^ _GEN) + & (TOSR_flag ^ TOSW_flag ^ TOSR_value < TOSW_value) + ? _GEN_1 + : _GEN_4; // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :141:23, :142:23, :143:23, :144:22, :148:31, :157:{13,41}, :170:33, :171:15, :173:15, :187:15, :189:15, :192:54, :193:15, :195:15, :206:33, :216:{29,52}, :218:24, :219:37, :244:30, :259:28, :262:33, :263:{55,78}, :264:19, :267:19, :271:{36,58}, :278:{35,42}, :280:19, :281:51, :282:19, :285:19, :289:17, :290:37, :297:17, :299:37, :306:{18,25}, :308:16, :309:48, :310:16, :313:16, :317:17, :318:28, :320:17, :321:32, :323:17, :324:32, :326:19, :329:38, :335:{31,38}, :337:24, :338:65, :339:24, :342:24, :346:19, :354:17, :373:26, :386:115, utility/src/main/scala/utility/CircularQueuePtr.scala:72:35, :73:30, :74:19 + end + end // always @(posedge, posedge) + wire [7:0] writeEntry_ctr = + {5'h0, + _realPush_T_4 + ? (_writeEntry_ctr_T_1 + & (redirectTopEntry_inflightValid + ? _GEN_2[io_redirect_meta_TOSR_value] + : _GEN_5[io_redirect_meta_ssp]) < 8'h7 + ? _sctr_T_12 + : 3'h0) + : _writeEntry_ctr_T_7 + & (writeBypassValid + ? writeBypassEntry_ctr + : topEntry_inflightValid ? _GEN_2[TOSR_value] : _GEN_5[ssp]) < 8'h7 + ? _sctr_T + : 3'h0}; // src/main/scala/xiangshan/frontend/newRAS.scala:139:22, :141:23, :142:23, :148:31, :151:35, :157:41, :184:33, :185:15, :186:61, :187:15, :189:15, :192:54, :193:15, :195:15, :216:29, :245:{20,26}, :246:{10,36,61,85,117}, :247:{10,28,50,66,81}, :260:41 + always @(posedge clock) begin + if (io_spec_push_valid | _realPush_T_4) begin // src/main/scala/xiangshan/frontend/newRAS.scala:216:29, :252:30 + writeBypassEntry_retAddr <= writeEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:148:31, :244:30 + writeBypassEntry_ctr <= writeEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:148:31, :245:20 + writeBypassNos_flag <= _realPush_T_4 ? io_redirect_meta_NOS_flag : TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :149:29, :216:29, :249:20 + writeBypassNos_value <= _realPush_T_4 ? io_redirect_meta_NOS_value : TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :149:29, :216:29, :249:20 + end + if (io_s2_fire | io_redirect_isCall) begin // src/main/scala/xiangshan/frontend/newRAS.scala:361:64 + realWriteEntry_next_retAddr <= writeEntry_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:244:30, :361:40 + realWriteEntry_next_ctr <= writeEntry_ctr; // src/main/scala/xiangshan/frontend/newRAS.scala:245:20, :361:40 + end + if (io_s2_fire | _realPush_T_4) // src/main/scala/xiangshan/frontend/newRAS.scala:216:29, :377:126 + realWriteAddr_next_value <= + _realPush_T_4 ? io_redirect_meta_TOSW_value : TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :216:29, :377:{39,43} + if (io_s2_fire | _realPush_T_4) begin // src/main/scala/xiangshan/frontend/newRAS.scala:216:29, :381:120 + realNos_next_flag <= _realPush_T_4 ? io_redirect_meta_TOSR_flag : TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :216:29, :381:{33,37} + realNos_next_value <= _realPush_T_4 ? io_redirect_meta_TOSR_value : TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:142:23, :216:29, :381:{33,37} + end + if (io_s2_fire) // src/main/scala/xiangshan/frontend/newRAS.scala:89:16 + realPush_r <= io_spec_push_valid; // src/main/scala/xiangshan/frontend/newRAS.scala:386:59 + realPush_REG <= _realPush_T_4; // src/main/scala/xiangshan/frontend/newRAS.scala:216:29, :386:125 + end // always @(posedge) + `ifdef ENABLE_INITIAL_REG_ // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 + `ifdef FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 + `FIRRTL_BEFORE_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 + `endif // FIRRTL_BEFORE_INITIAL + logic [31:0] _RANDOM[0:82]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 + initial begin // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 + `ifdef INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 + `INIT_RANDOM_PROLOG_ // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 + `endif // INIT_RANDOM_PROLOG_ + `ifdef RANDOMIZE_REG_INIT // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 + for (logic [6:0] i = 7'h0; i < 7'h53; i += 7'h1) begin + _RANDOM[i] = `RANDOM; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 + end // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 + commit_stack_0_retAddr = {_RANDOM[7'h0], _RANDOM[7'h1][6:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_0_ctr = _RANDOM[7'h1][14:7]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_1_retAddr = {_RANDOM[7'h1][31:15], _RANDOM[7'h2][21:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_1_ctr = _RANDOM[7'h2][29:22]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_2_retAddr = + {_RANDOM[7'h2][31:30], _RANDOM[7'h3], _RANDOM[7'h4][4:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_2_ctr = _RANDOM[7'h4][12:5]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_3_retAddr = {_RANDOM[7'h4][31:13], _RANDOM[7'h5][19:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_3_ctr = _RANDOM[7'h5][27:20]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_4_retAddr = + {_RANDOM[7'h5][31:28], _RANDOM[7'h6], _RANDOM[7'h7][2:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_4_ctr = _RANDOM[7'h7][10:3]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_5_retAddr = {_RANDOM[7'h7][31:11], _RANDOM[7'h8][17:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_5_ctr = _RANDOM[7'h8][25:18]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_6_retAddr = {_RANDOM[7'h8][31:26], _RANDOM[7'h9], _RANDOM[7'hA][0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_6_ctr = _RANDOM[7'hA][8:1]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_7_retAddr = {_RANDOM[7'hA][31:9], _RANDOM[7'hB][15:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_7_ctr = _RANDOM[7'hB][23:16]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_8_retAddr = {_RANDOM[7'hB][31:24], _RANDOM[7'hC][30:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_8_ctr = {_RANDOM[7'hC][31], _RANDOM[7'hD][6:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_9_retAddr = {_RANDOM[7'hD][31:7], _RANDOM[7'hE][13:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_9_ctr = _RANDOM[7'hE][21:14]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_10_retAddr = {_RANDOM[7'hE][31:22], _RANDOM[7'hF][28:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_10_ctr = {_RANDOM[7'hF][31:29], _RANDOM[7'h10][4:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_11_retAddr = {_RANDOM[7'h10][31:5], _RANDOM[7'h11][11:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_11_ctr = _RANDOM[7'h11][19:12]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_12_retAddr = {_RANDOM[7'h11][31:20], _RANDOM[7'h12][26:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_12_ctr = {_RANDOM[7'h12][31:27], _RANDOM[7'h13][2:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_13_retAddr = {_RANDOM[7'h13][31:3], _RANDOM[7'h14][9:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_13_ctr = _RANDOM[7'h14][17:10]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_14_retAddr = {_RANDOM[7'h14][31:18], _RANDOM[7'h15][24:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_14_ctr = {_RANDOM[7'h15][31:25], _RANDOM[7'h16][0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_15_retAddr = {_RANDOM[7'h16][31:1], _RANDOM[7'h17][7:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + commit_stack_15_ctr = _RANDOM[7'h17][15:8]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31 + spec_queue_0_retAddr = {_RANDOM[7'h17][31:16], _RANDOM[7'h18][22:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :134:31, :135:29 + spec_queue_0_ctr = _RANDOM[7'h18][30:23]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_1_retAddr = {_RANDOM[7'h18][31], _RANDOM[7'h19], _RANDOM[7'h1A][5:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_1_ctr = _RANDOM[7'h1A][13:6]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_2_retAddr = {_RANDOM[7'h1A][31:14], _RANDOM[7'h1B][20:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_2_ctr = _RANDOM[7'h1B][28:21]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_3_retAddr = + {_RANDOM[7'h1B][31:29], _RANDOM[7'h1C], _RANDOM[7'h1D][3:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_3_ctr = _RANDOM[7'h1D][11:4]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_4_retAddr = {_RANDOM[7'h1D][31:12], _RANDOM[7'h1E][18:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_4_ctr = _RANDOM[7'h1E][26:19]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_5_retAddr = + {_RANDOM[7'h1E][31:27], _RANDOM[7'h1F], _RANDOM[7'h20][1:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_5_ctr = _RANDOM[7'h20][9:2]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_6_retAddr = {_RANDOM[7'h20][31:10], _RANDOM[7'h21][16:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_6_ctr = _RANDOM[7'h21][24:17]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_7_retAddr = {_RANDOM[7'h21][31:25], _RANDOM[7'h22]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_7_ctr = _RANDOM[7'h23][7:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_8_retAddr = {_RANDOM[7'h23][31:8], _RANDOM[7'h24][14:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_8_ctr = _RANDOM[7'h24][22:15]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_9_retAddr = {_RANDOM[7'h24][31:23], _RANDOM[7'h25][29:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_9_ctr = {_RANDOM[7'h25][31:30], _RANDOM[7'h26][5:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_10_retAddr = {_RANDOM[7'h26][31:6], _RANDOM[7'h27][12:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_10_ctr = _RANDOM[7'h27][20:13]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_11_retAddr = {_RANDOM[7'h27][31:21], _RANDOM[7'h28][27:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_11_ctr = {_RANDOM[7'h28][31:28], _RANDOM[7'h29][3:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_12_retAddr = {_RANDOM[7'h29][31:4], _RANDOM[7'h2A][10:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_12_ctr = _RANDOM[7'h2A][18:11]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_13_retAddr = {_RANDOM[7'h2A][31:19], _RANDOM[7'h2B][25:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_13_ctr = {_RANDOM[7'h2B][31:26], _RANDOM[7'h2C][1:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_14_retAddr = {_RANDOM[7'h2C][31:2], _RANDOM[7'h2D][8:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_14_ctr = _RANDOM[7'h2D][16:9]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_15_retAddr = {_RANDOM[7'h2D][31:17], _RANDOM[7'h2E][23:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_15_ctr = _RANDOM[7'h2E][31:24]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_16_retAddr = {_RANDOM[7'h2F], _RANDOM[7'h30][6:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_16_ctr = _RANDOM[7'h30][14:7]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_17_retAddr = {_RANDOM[7'h30][31:15], _RANDOM[7'h31][21:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_17_ctr = _RANDOM[7'h31][29:22]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_18_retAddr = + {_RANDOM[7'h31][31:30], _RANDOM[7'h32], _RANDOM[7'h33][4:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_18_ctr = _RANDOM[7'h33][12:5]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_19_retAddr = {_RANDOM[7'h33][31:13], _RANDOM[7'h34][19:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_19_ctr = _RANDOM[7'h34][27:20]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_20_retAddr = + {_RANDOM[7'h34][31:28], _RANDOM[7'h35], _RANDOM[7'h36][2:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_20_ctr = _RANDOM[7'h36][10:3]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_21_retAddr = {_RANDOM[7'h36][31:11], _RANDOM[7'h37][17:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_21_ctr = _RANDOM[7'h37][25:18]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_22_retAddr = + {_RANDOM[7'h37][31:26], _RANDOM[7'h38], _RANDOM[7'h39][0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_22_ctr = _RANDOM[7'h39][8:1]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_23_retAddr = {_RANDOM[7'h39][31:9], _RANDOM[7'h3A][15:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_23_ctr = _RANDOM[7'h3A][23:16]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_24_retAddr = {_RANDOM[7'h3A][31:24], _RANDOM[7'h3B][30:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_24_ctr = {_RANDOM[7'h3B][31], _RANDOM[7'h3C][6:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_25_retAddr = {_RANDOM[7'h3C][31:7], _RANDOM[7'h3D][13:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_25_ctr = _RANDOM[7'h3D][21:14]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_26_retAddr = {_RANDOM[7'h3D][31:22], _RANDOM[7'h3E][28:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_26_ctr = {_RANDOM[7'h3E][31:29], _RANDOM[7'h3F][4:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_27_retAddr = {_RANDOM[7'h3F][31:5], _RANDOM[7'h40][11:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_27_ctr = _RANDOM[7'h40][19:12]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_28_retAddr = {_RANDOM[7'h40][31:20], _RANDOM[7'h41][26:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_28_ctr = {_RANDOM[7'h41][31:27], _RANDOM[7'h42][2:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_29_retAddr = {_RANDOM[7'h42][31:3], _RANDOM[7'h43][9:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_29_ctr = _RANDOM[7'h43][17:10]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_30_retAddr = {_RANDOM[7'h43][31:18], _RANDOM[7'h44][24:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_30_ctr = {_RANDOM[7'h44][31:25], _RANDOM[7'h45][0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_31_retAddr = {_RANDOM[7'h45][31:1], _RANDOM[7'h46][7:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_queue_31_ctr = _RANDOM[7'h46][15:8]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29 + spec_nos_0_flag = _RANDOM[7'h46][16]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27 + spec_nos_0_value = _RANDOM[7'h46][21:17]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27 + spec_nos_1_flag = _RANDOM[7'h46][22]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27 + spec_nos_1_value = _RANDOM[7'h46][27:23]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27 + spec_nos_2_flag = _RANDOM[7'h46][28]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27 + spec_nos_2_value = {_RANDOM[7'h46][31:29], _RANDOM[7'h47][1:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :135:29, :136:27 + spec_nos_3_flag = _RANDOM[7'h47][2]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_3_value = _RANDOM[7'h47][7:3]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_4_flag = _RANDOM[7'h47][8]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_4_value = _RANDOM[7'h47][13:9]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_5_flag = _RANDOM[7'h47][14]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_5_value = _RANDOM[7'h47][19:15]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_6_flag = _RANDOM[7'h47][20]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_6_value = _RANDOM[7'h47][25:21]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_7_flag = _RANDOM[7'h47][26]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_7_value = _RANDOM[7'h47][31:27]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_8_flag = _RANDOM[7'h48][0]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_8_value = _RANDOM[7'h48][5:1]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_9_flag = _RANDOM[7'h48][6]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_9_value = _RANDOM[7'h48][11:7]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_10_flag = _RANDOM[7'h48][12]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_10_value = _RANDOM[7'h48][17:13]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_11_flag = _RANDOM[7'h48][18]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_11_value = _RANDOM[7'h48][23:19]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_12_flag = _RANDOM[7'h48][24]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_12_value = _RANDOM[7'h48][29:25]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_13_flag = _RANDOM[7'h48][30]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_13_value = {_RANDOM[7'h48][31], _RANDOM[7'h49][3:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_14_flag = _RANDOM[7'h49][4]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_14_value = _RANDOM[7'h49][9:5]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_15_flag = _RANDOM[7'h49][10]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_15_value = _RANDOM[7'h49][15:11]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_16_flag = _RANDOM[7'h49][16]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_16_value = _RANDOM[7'h49][21:17]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_17_flag = _RANDOM[7'h49][22]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_17_value = _RANDOM[7'h49][27:23]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_18_flag = _RANDOM[7'h49][28]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_18_value = {_RANDOM[7'h49][31:29], _RANDOM[7'h4A][1:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_19_flag = _RANDOM[7'h4A][2]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_19_value = _RANDOM[7'h4A][7:3]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_20_flag = _RANDOM[7'h4A][8]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_20_value = _RANDOM[7'h4A][13:9]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_21_flag = _RANDOM[7'h4A][14]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_21_value = _RANDOM[7'h4A][19:15]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_22_flag = _RANDOM[7'h4A][20]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_22_value = _RANDOM[7'h4A][25:21]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_23_flag = _RANDOM[7'h4A][26]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_23_value = _RANDOM[7'h4A][31:27]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_24_flag = _RANDOM[7'h4B][0]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_24_value = _RANDOM[7'h4B][5:1]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_25_flag = _RANDOM[7'h4B][6]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_25_value = _RANDOM[7'h4B][11:7]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_26_flag = _RANDOM[7'h4B][12]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_26_value = _RANDOM[7'h4B][17:13]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_27_flag = _RANDOM[7'h4B][18]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_27_value = _RANDOM[7'h4B][23:19]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_28_flag = _RANDOM[7'h4B][24]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_28_value = _RANDOM[7'h4B][29:25]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_29_flag = _RANDOM[7'h4B][30]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_29_value = {_RANDOM[7'h4B][31], _RANDOM[7'h4C][3:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_30_flag = _RANDOM[7'h4C][4]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_30_value = _RANDOM[7'h4C][9:5]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_31_flag = _RANDOM[7'h4C][10]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + spec_nos_31_value = _RANDOM[7'h4C][15:11]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27 + nsp = _RANDOM[7'h4C][19:16]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27, :138:22 + ssp = _RANDOM[7'h4C][23:20]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27, :139:22 + sctr = _RANDOM[7'h4C][26:24]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27, :141:23 + TOSR_flag = _RANDOM[7'h4C][27]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27, :142:23 + TOSR_value = {_RANDOM[7'h4C][31:28], _RANDOM[7'h4D][0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :136:27, :142:23 + TOSW_flag = _RANDOM[7'h4D][1]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :143:23 + TOSW_value = _RANDOM[7'h4D][6:2]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :143:23 + BOS_flag = _RANDOM[7'h4D][7]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :144:22 + BOS_value = _RANDOM[7'h4D][12:8]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :144:22 + spec_overflowed = _RANDOM[7'h4D][13]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :146:34 + writeBypassEntry_retAddr = {_RANDOM[7'h4D][31:14], _RANDOM[7'h4E][20:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23, :148:31 + writeBypassEntry_ctr = _RANDOM[7'h4E][28:21]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :148:31 + writeBypassNos_flag = _RANDOM[7'h4E][29]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :148:31, :149:29 + writeBypassNos_value = {_RANDOM[7'h4E][31:30], _RANDOM[7'h4F][2:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :148:31, :149:29 + writeBypassValid = _RANDOM[7'h4F][3]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :149:29, :151:35 + timingTop_retAddr = {_RANDOM[7'h4F][31:4], _RANDOM[7'h50][10:0]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :149:29, :259:28 + realWriteEntry_next_retAddr = {_RANDOM[7'h50][31:25], _RANDOM[7'h51]}; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :259:28, :361:40 + realWriteEntry_next_ctr = _RANDOM[7'h52][7:0]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40 + realWriteAddr_next_value = _RANDOM[7'h52][13:9]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40, :377:39 + realNos_next_flag = _RANDOM[7'h52][14]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40, :381:33 + realNos_next_value = _RANDOM[7'h52][19:15]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40, :381:33 + realPush_r = _RANDOM[7'h52][20]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40, :386:59 + realPush_REG = _RANDOM[7'h52][21]; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :361:40, :386:125 + `endif // RANDOMIZE_REG_INIT + if (reset) begin // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 + commit_stack_0_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_0_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_1_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_1_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_2_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_2_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_3_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_3_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_4_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_4_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_5_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_5_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_6_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_6_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_7_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_7_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_8_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_8_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_9_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_9_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_10_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_10_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_11_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_11_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_12_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_12_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_13_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_13_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_14_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_14_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_15_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + commit_stack_15_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:134:31, :259:41 + spec_queue_0_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_0_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_1_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_1_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_2_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_2_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_3_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_3_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_4_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_4_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_5_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_5_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_6_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_6_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_7_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_7_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_8_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_8_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_9_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_9_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_10_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_10_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_11_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_11_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_12_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_12_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_13_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_13_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_14_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_14_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_15_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_15_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_16_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_16_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_17_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_17_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_18_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_18_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_19_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_19_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_20_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_20_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_21_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_21_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_22_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_22_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_23_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_23_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_24_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_24_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_25_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_25_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_26_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_26_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_27_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_27_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_28_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_28_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_29_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_29_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_30_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_30_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_31_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_queue_31_ctr = 8'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:135:29, :259:41 + spec_nos_0_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_0_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_1_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_1_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_2_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_2_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_3_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_3_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_4_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_4_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_5_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_5_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_6_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_6_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_7_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_7_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_8_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_8_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_9_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_9_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_10_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_10_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_11_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_11_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_12_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_12_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_13_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_13_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_14_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_14_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_15_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_15_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_16_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_16_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_17_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_17_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_18_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_18_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_19_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_19_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_20_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_20_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_21_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_21_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_22_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_22_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_23_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_23_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_24_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_24_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_25_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_25_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_26_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_26_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_27_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_27_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_28_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_28_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_29_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_29_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_30_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_30_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + spec_nos_31_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :136:27 + spec_nos_31_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:136:27, :260:41 + nsp = 4'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22 + ssp = 4'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:138:22, :139:22 + sctr = 3'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:141:23 + TOSR_flag = 1'h1; // src/main/scala/xiangshan/frontend/newRAS.scala:40:14, :142:23 + TOSR_value = 5'h1F; // src/main/scala/xiangshan/frontend/newRAS.scala:41:15, :142:23 + TOSW_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :143:23 + TOSW_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:143:23, :260:41 + BOS_flag = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :144:22 + BOS_value = 5'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:144:22, :260:41 + spec_overflowed = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :146:34 + writeBypassValid = 1'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:81:17, :151:35 + timingTop_retAddr = 39'h0; // src/main/scala/xiangshan/frontend/newRAS.scala:259:{28,41} + end + end // initial + `ifdef FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 + `FIRRTL_AFTER_INITIAL // src/main/scala/xiangshan/frontend/newRAS.scala:88:9 + `endif // FIRRTL_AFTER_INITIAL + `endif // ENABLE_INITIAL_REG_ + assign io_spec_pop_addr = timingTop_retAddr; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :259:28 + assign io_ssp = ssp; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :139:22 + assign io_sctr = sctr; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :141:23 + assign io_TOSR_flag = TOSR_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23 + assign io_TOSR_value = TOSR_value; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :142:23 + assign io_TOSW_flag = TOSW_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :143:23 + assign io_TOSW_value = TOSW_value; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :143:23 + assign io_NOS_flag = topNos_flag; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :170:33, :171:15, :173:15 + assign io_NOS_value = topNos_value; // src/main/scala/xiangshan/frontend/newRAS.scala:88:9, :170:33, :171:15, :173:15 +endmodule +