Change the name Interface to Bundle

This commit is contained in:
Miical 2024-05-06 10:47:47 +08:00
parent b5705bccf9
commit 8408155af8
3 changed files with 13 additions and 13 deletions

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@ -196,7 +196,7 @@ import mlvp
mlvp.debug("This is a debug message", extra={"log_id": "dut"})
mlvp.info("This is an info message")
mlvp.warning("This is a warning message", extra={"log_id": "interface"})
mlvp.warning("This is a warning message", extra={"log_id": "bundle"})
mlvp.error("This is an error message")
mlvp.critical("This is a critical message")
```

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@ -1,6 +1,6 @@
from mlvp import Interface
from mlvp import Bundle
class PipelineCtrlBundle(Interface):
class PipelineCtrlBundle(Bundle):
signals_list = ["s0_fire_0", "s0_fire_1", "s0_fire_2", "s0_fire_3",
"s1_fire_0", "s1_fire_1", "s1_fire_2", "s1_fire_3",
"s2_fire_0", "s2_fire_1", "s2_fire_2", "s2_fire_3",
@ -8,25 +8,25 @@ class PipelineCtrlBundle(Interface):
"s1_ready", "s2_ready", "s3_ready",
"s2_redirect", "s3_redirect"]
class EnableCtrlBundle(Interface):
class EnableCtrlBundle(Bundle):
signals_list = ["ubtb_enable", "btb_enable", "bim_enable", "tage_enable",
"sc_enable", "ras_enable", "loop_enable"]
class FTBEntryBundle(Interface):
class FTBEntryBundle(Bundle):
signals_list = ["brSlots_0_offset", "brSlots_0_lower", "brSlots_0_tarStat", "brSlots_0_valid",
"tailSlot_offset", "tailSlot_lower", "tailSlot_tarStat", "tailSlot_sharing", "tailSlot_valid",
"pftAddr", "carry", "isCall", "isRet", "isJalr", "last_may_be_rvi_call",
"always_taken_0", "always_taken_1"]
class UpdateBundle(Interface):
class UpdateBundle(Bundle):
signals_list = ["valid", "bits_pc", "bits_br_taken_mask_0", "bits_br_taken_mask_1"]
sub_interfaces = [
sub_bundles = [
("ftb_entry", lambda dut: FTBEntryBundle.from_prefix(dut, "bits_ftb_entry_"))
]
class FullBranchPredirectionBundle(Interface):
class FullBranchPredirectionBundle(Bundle):
signals_list = ["hit", "slot_valids_0", "slot_valids_1", "targets_0", "targets_1",
"offsets_0", "offsets_1", "fallThroughAddr", "fallThroughErr",
"is_jal", "is_jalr", "is_call", "is_ret", "is_br_sharing",
@ -34,16 +34,16 @@ class FullBranchPredirectionBundle(Interface):
"br_taken_mask_0", "br_taken_mask_1",
"jalr_target"]
class BranchPredictionBundle(Interface):
class BranchPredictionBundle(Bundle):
signals_list = ["pc_3", "valid", "hasRedirect", "ftq_idx"]
sub_interfaces = [
sub_bundles = [
("full_pred", lambda dut: FullBranchPredirectionBundle.from_regex(dut, r"full_pred_\d_(.*)"))
]
class BranchPredictionResp(Interface):
class BranchPredictionResp(Bundle):
signals_list = ["last_stage_meta"]
sub_interfaces = [
sub_bundles = [
("s1", lambda dut: BranchPredictionBundle.from_prefix(dut, "s1_")),
("s2", lambda dut: BranchPredictionBundle.from_prefix(dut, "s2_")),
("s3", lambda dut: BranchPredictionBundle.from_prefix(dut, "s3_")),

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@ -1,4 +1,4 @@
from mlvp.utils import PLRU, TwoBitsCounter
from mlvp.modules import PLRU, TwoBitsCounter
from mlvp import *
from .ftb import *