forked from OSchip/UnityChipVerification
update tage-sc src files
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parent
94900d287e
commit
7d833289fb
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@ -1,24 +1,30 @@
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./rtl/ITTAGE/CAMTemplate_41.sv
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./rtl/ITTAGE/CAMTemplate_43.sv
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./rtl/ITTAGE/Folded1WDataModuleTemplate.sv
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./rtl/ITTAGE/Folded1WDataModuleTemplate_2.sv
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./rtl/ITTAGE/FoldedSRAMTemplate_21.sv
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./rtl/ITTAGE/FoldedSRAMTemplate_25.sv
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./rtl/ITTAGE/ITTage.sv
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./rtl/ITTAGE/ITTageTable.sv
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./rtl/ITTAGE/ITTageTable_1.sv
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./rtl/ITTAGE/ITTageTable_2.sv
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./rtl/ITTAGE/ITTageTable_3.sv
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./rtl/ITTAGE/ITTageTable_4.sv
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./rtl/ITTAGE/SRAMTemplate_35.sv
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./rtl/ITTAGE/SRAMTemplate_39.sv
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./rtl/ITTAGE/WrBypass_41.sv
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./rtl/ITTAGE/WrBypass_43.sv
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./rtl/ITTAGE/array_0_0.sv
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./rtl/ITTAGE/array_8.sv
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./rtl/ITTAGE/data_16x16.sv
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./rtl/ITTAGE/data_32x16.sv
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./rtl/ITTAGE/data_mem_0_4x2.sv
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./rtl/TageSC/SRAMTemplate_31.sv
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./rtl/TageSC/data_mem_0_8x3.sv
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./rtl/TageSC/SCTable.sv
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./rtl/TageSC/SRAMTemplate_11.sv
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./rtl/TageSC/CAMTemplate_32.sv
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./rtl/TageSC/array_6.sv
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./rtl/TageSC/SCTable_1.sv
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./rtl/TageSC/array_5.sv
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./rtl/TageSC/TageTable_1.sv
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./rtl/TageSC/FoldedSRAMTemplate_1.sv
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./rtl/TageSC/SRAMTemplate_10.sv
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./rtl/TageSC/SRAMTemplate_30.sv
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./rtl/TageSC/FoldedSRAMTemplate.sv
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./rtl/TageSC/CAMTemplate_33.sv
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./rtl/TageSC/data_mem_16x12.sv
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./rtl/TageSC/TageBTable.sv
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./rtl/TageSC/TageTable_3.sv
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./rtl/TageSC/data_mem_8x4.sv
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./rtl/TageSC/array_4.sv
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./rtl/TageSC/TageTable_2.sv
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./rtl/TageSC/TageTable.sv
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./rtl/TageSC/array_7.sv
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./rtl/TageSC/SCTable_2.sv
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./rtl/TageSC/FoldedSRAMTemplate_20.sv
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./rtl/TageSC/CAMTemplate.sv
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./rtl/TageSC/Tage_SC.sv
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./rtl/TageSC/SCTable_3.sv
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#
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./rtl/WrBypass/WrBypass.sv
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./rtl/WrBypass/WrBypass_32.sv
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