Operator: LeakyReLU-Affine-Gate (Fused CUDA Kernel)

Goal
- Provide a fused affine–LeakyReLU–sigmoid gate operator optimized for throughput.

Inputs/Outputs
- Input `x`: [B, D], float32
- Parameters `scale`, `bias`: [D], float32
- Scalars `alpha`, `beta`: float32; negative slope fixed at 0.1
- Output `y`: [B, D], float32

Definition
- z = x * scale + bias
- m = leaky_relu(z, slope=0.1)
- g = sigmoid(alpha * m + beta)
- y = x * g

CUDA Design
- 2D grid slicing of D; 128 threads; ILP=1 with float4 vectorization
- Fast math, FMA for affine, branch-minimized leaky path

Validation
- Accuracy `torch.allclose(rtol=1e-3)`
- Speedup ≥ 1.30x at standard benchmark
 
 Extended Benchmark & Requirements
- Test 3 shapes (D=4096/16384/65536) and dtypes (FP32, FP16, BF16 where supported)
- Report times and speedup per case; synchronize appropriately
- Use `rtol=1e-3` for FP32, `rtol=1e-2` for FP16/BF16
- Print bottleneck analysis when speedup <1.3x and suggest improvements
