Operator: Sinh-Affine-Gate (Fused CUDA Kernel)

Goal
- Fuse affine, sinh activation, sigmoid gate, and multiply in one pass for throughput.

Inputs/Outputs
- Input `x`: [B, D], float32
- Parameters `scale`, `bias`: [D], float32
- Scalars `alpha`, `beta`: float32
- Output `y`: [B, D], float32

Definition
- z = x * scale + bias
- m = sinh(z)
- g = sigmoid(alpha * m + beta)
- y = x * g

CUDA Design
- 2D grid; block=128; ILP=1; float4 vectorization
- Use fast `__expf` to form sinh: 0.5*(exp(z) − exp(−z))

Validation
- Accuracy `torch.allclose(rtol=1e-3)`
- Speedup ≥ 1.30x at default benchmark
 
 Extended Benchmark & Requirements
- Cover 3 shapes (D=4096/16384/65536) and dtypes FP32/FP16/BF16 where supported
- Report wall-clock and speedup per case; 100 iterations with synchronization
- FP32 `rtol=1e-3`, FP16/BF16 `rtol=1e-2`
- If speedup <1.3x, print bottleneck analysis and optimization plan
