Operator: HardSigmoid-Affine-Gate (Fused CUDA Kernel)

Goal
- Implement a fused affine–HardSigmoid gate operator to reduce memory traffic and kernel launches, targeting ≥1.30x speedup.

Inputs/Outputs
- Input `x`: [B, D], float32 (contiguous)
- Parameters `scale`, `bias`: [D], float32 (contiguous)
- Scalars `alpha`, `beta`: float32
- Output `y`: [B, D], float32

Definition
- z = x * scale + bias
- g = hardsigmoid(alpha * z + beta) = clamp((alpha*z + beta) * (1/6) + 0.5, 0, 1)
- y = x * g

CUDA Design
- 2D grid: grid.x = B; grid.y = ceil(D / (block * ILP * 4))
- Block size: 128; ILP = 1 (1 x float4 per thread)
- Vectorized memory with float4; fast math intrinsics; FMA for affine
- Requires contiguous tensors; D multiple of 4 recommended

Build
- PyTorch inline extension; flags: `-O3`, `--use_fast_math`, `-std=c++14`

Validation
- Precision: `torch.allclose(rtol=1e-3)` vs PyTorch reference
- Performance: speedup ≥ 1.30x at B=16, D=16384, 100 iterations

How to Run
- Execute `run_code.py` to check precision and speedup
 
 Extended Benchmark & Requirements
- Cover at least 3 shapes (e.g., D=4096/16384/65536) and dtypes (FP32, FP16, BF16 if available)
- Report per-case wall-clock time and speedup; use multiple iterations and synchronization
- Use `rtol=1e-3` for FP32, relax to `rtol=1e-2` for FP16/BF16
- If speedup <1.3x for any case, print bottleneck analysis and next-step optimization plan
