Operator: Softplus^2-Affine-Gate (Fused CUDA Kernel)

Goal
- Fuse affine, Softplus, square, sigmoid gate, and multiply in one kernel to reduce memory traffic.

Inputs/Outputs
- Input `x`: [B, D], float32
- Parameters `scale`, `bias`: [D], float32
- Scalars `alpha`, `beta`: float32
- Output `y`: [B, D], float32

Definition
- z = x * scale + bias
- m = softplus(z); v = m * m
- g = sigmoid(alpha * v + beta)
- y = x * g

CUDA Design
- 2D grid with float4 vectorization; block=128; ILP=1
- Numerically stable softplus; fast math; FMA for affine

Validation
- Accuracy `torch.allclose(rtol=1e-3)`
- Speedup ≥ 1.30x at B=16, D=16384
 
 Extended Benchmark & Requirements
- Evaluate 3 shapes (D=4096/16384/65536) and FP32/FP16/BF16 if available
- Per-case timing and speedup; average over 100 iterations with synchronization
- FP32 uses `rtol=1e-3`, FP16/BF16 use `rtol=1e-2`
- Print bottleneck notes if any case <1.3x and list next-step optimizations
